JPH0452759A - Multiplex processing system for vector instruction - Google Patents

Abstract

PURPOSE:To process the vector data at a high speed by providing the status registers on a load/store pipeline and an arithmetic pipeline respectively. CONSTITUTION:If a page fault occurs on a load/store pipeline 21 which performs a memory access operation in the working states of the pipeline 21 and an arithmetic pipeline 20, the interruption of the page fault is informed and at the same time the processing is interrupted for all vector instructions on both pipelines 21 and 20. In this case, the vector instructions and the element Nos are held by the status registers 210 and 200 respectively. When a page is successfully acquired, the elements following the element Nos stored in both registers 210 and 200 are processed again. Thus the processing ability of a vector computer is improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology and Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Vector operations can be performed on a plurality of Process in pipeline.

In addition, regarding the method of processing vector instructions in the virtual memory space using the on-demand paging method, the main memory ( When a page fault occurs in a vibline that accesses the main storage unit (MSU), vector instruction processing in all multiple pipelines is interrupted, and the vibline that accesses the main storage unit (MSU) (load/store pipeline) ) and main memory unit f (MSU)
Vibration line that does not access (arithmetic power line)
and means for retaining the state (resuming element number, etc.) of the vector instruction being processed in each pipeline at the time of the above-mentioned interruption, so that the above-mentioned page fault does not occur.
The vector processing on each vibe line is interrupted and the operation 1/eating system (O
5) When the 42 interrupt occurs, the operating system (
Based on a restart instruction from the operating system (OS), the processing of the plurality of vector instructions suspended in each vibe line is resumed from the suspended state stored in the holding means.

(Industrial Application Field) The present invention relates to a method for processing vector operations using a plurality of vibe lines and processing vector instructions in a virtual storage space using an on-demand paging method.

With the spread of high-speed processing using vector pipeline computers in recent years, the demand for data processing by vector computers has increased from many users, and as a result, the amount of vector data processed has increased. The vector data has also increased, and it has become necessary to develop the vector data on a virtual storage space.

Therefore, there is a need for a vector instruction processing method that can quickly process vector data developed in such a virtual storage space.

[Prior art and problems to be solved by the invention] FIG.
A) shows a configuration example, and (lil) and (b2) show a schematic operation flow.

(a) Multiple vibe lines (calculation pipeline 20, load, 'store pipeline 2] as shown in the figure)
) of a vector calculator with
In υ) 2, if the vector data is developed in the main storage unit (MSU) 1, 2. By executing a plurality of vector instructions (1)'' (3) in parallel, the processing capacity of the vector data is improved.

However, recently, the use of vector calculators has become more diverse, and the J of vector data has become larger. Then, in the real storage space of the main storage device (SO) i, the huge vector operation cannot be completed and there are 4 operations, and a virtual storage space is constructed on the file storage device (DASD). The above real storage space (main storage unit (MSU)
) 1) Applicable to f in pages; - Rude
Q: It is necessary to process vector data before expanding it.
Q I Niru. This processing method is called an on-demand paging method.

In such a case, as a result of the processing in the load/store pipeline 21, there is no vector data to be loaded on the main storage unit (MSU) 1, resulting in a so-called page folder.
is detected, the processing in the load/store pipeline 21 is interrupted, and the index of the vector instruction currently being executed in the load/store pipeline 21 (i.e.,
The restart element number) is held in a specific status register 210 and interrupts the operating system (OS).

The interrupted operating system (O3) pages vector data from the virtual storage space into the main storage unit (MSU) 1 in page units.

When the page-in is completed, 1. Execution of the vector instruction is resumed from the element number held in the status register 2101 of the load/store pipeline 21.

At this time, vector instructions being executed in other arithmetic pipelines 20 are thrown away from the scalar unit (SU), which is the central processing unit of the vector computer system, and are independently operated in the vector unit (VU) 2. ing.

Therefore, as mentioned above, the load/store pipeline 2
When a page fault occurs in 1 and the processing in the load/store pipeline 21 is interrupted, processing in other calculation pipelines 20 may be similarly interrupted; The address of the vector instruction being executed (indicated by the program status word (PSW) of the scalar unit (SU)) as well as the element number at the time of interruption are not managed by the scalar unit (SLL). It is difficult not only to reissue the vector instruction but also to resume processing from the interrupted element.

Therefore, in the conventional method, when a page fault occurs in a vector computer that uses the virtual memory method as described above, the series of processes of interrupting the operating system (O3) → page acquisition → re-execution are as follows:
In order to execute without contradiction in any case, this figure (b2)
As shown in FIG. 1, the vector instruction that may cause the page fault is
Vector instructions (vector load instructions/vector store instructions) that involve access to are serialized and executed independently without overlapping with other vector instructions.

By providing a status register 210 in the load/store pipeline 21, when a page fault occurs,
The contents of the status register 210 are read according to the instruction of the operating system (O3), the interrupted vector instruction is reissued according to the read contents, and the interrupted vector instruction is started from the element immediately before the occurrence of the page fault. The method for executing the vector instruction is a technique disclosed by the applicant in Japanese Patent Application No. 1-53674 titled "Vector Instruction Processing Method."

In this conventional method, when a vector instruction that involves memory access is detected in a scalar unit (SU), vector operations (Vtl) of other subsequent vector instructions are detected.
2, it is not possible to process multiple vector instructions in an overlapping manner.

Therefore, the other arithmetic pipelines 20 other than the load/store pipeline 21 are in an unused state, and by making these arithmetic pipelines 20 that are originally usable into an unused state, the unused state is The performance of the vector computer is reduced by the amount of the calculation pipeline 20.

In view of the above conventional drawbacks, the present invention provides a vector computer that processes vector operations using a plurality of pipelines and processes vector instructions on a virtual storage space using an on-demand paging method, even under an on-demand paging mode. , it is an object of the present invention to provide a vector instruction multiprocessing method that allows the plurality of pipelines described above to be used in parallel as much as possible.

[Means to solve the problem]

The above problem can be achieved by a vector instruction multiple processing system configured as follows.

Process vector operations using multiple pipelines.

In addition, in a vector computer that uses a virtual storage system based on an on-demand paging system, the main storage unit (MSU)
When a page fault occurs in a pipeline that accesses a ) in both the pipelines that do not access When interrupting the operating system (O5) on the main storage unit (MSU), based on a restart instruction from the operating system (O3), the suspended state stored in the holding means is The configuration is configured to resume processing of a plurality of vector instructions suspended in each pipeline.

[Effect]

That is, according to the present invention, in a vector computer that processes vector operations using a plurality of vibe lines, a status register is provided for each of the load/store vibe line and other operation vibe lines.

Therefore, if a page fault occurs in the load/store pipeline that accesses memory while the above load/store pipeline and arithmetic vibe line are all in operation, a page fault interrupt is sent to the scalar unit (SU). is notified, and at the same time the corresponding load/
Not only the store pipeline but also 9 other calculation vibe lines,
Processing of all vector instructions is interrupted, and the vector instruction and element number at that time are held in the status register provided in each vibe line.

Scalar unit (SU) operating system (
O5) executes the autopsy processing routine (
Page fault routine) and performs page acquisition processing.

Here, if the page acquisition is successful, the vector instructions that were interrupted in each vibe line are reissued based on instructions from the operating system (O3), and the status registers provided in each vibe line are updated. Resumes processing for elements after the stored element number (element number).

At this time, if the vector instructions that are being executed in each operation vibe line have a processing order, they will be executed in the predetermined order according to the contents held in the separately provided process status register. .

Therefore, according to the present invention, even in vector processing on a virtual storage space, vector instructions can be processed in an overlapping manner, and the processing capacity of the hector computer can be improved.

(Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which a plurality of vibe lines, for example, a load/store pipeline 2
1. In each of the arithmetic vibe lines 20, when a page fault is detected while executing a memory access instruction in the load/vibe line 21 and vector processing in each pipeline is interrupted, each pipeline 21, 2
Providing status registers 210 and 200 for holding the vector instruction being executed at 0 and the restart element number is a necessary means for implementing the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the vector I/LE instruction multiple processing system of the present invention will be explained with reference to FIG.

In this vector unit (VIJ) 2, as shown, one mouth/store vibe line 21. It is composed of three operation vibe lines 20.
Normally, vector instructions are input to all pipelines 20 and 21, and the vector instructions are processed in parallel.

Currently, the one load/store pipeline 21 and the three arithmetic pipelines 20 are all in operation, and the load/store pipeline is executing memory access to the main storage unit (MSU) 1. If the above-mentioned page fault occurs in the vector instruction (vector load instruction or vector store instruction) being processed in step 21, an interrupt notification signal (■) is sent from the load/store vibe line 2, and at the same time, All vector operations on other operation vibe lines 20 are interrupted, and the vector instruction and element number at that time are stored in the corresponding status register 20.
The element number, which is displayed (held) as 00 and in which a page fault has occurred in the load/store pipeline 21, is displayed (held) in the status register 210 provided in the load/store pipeline 21.

Furthermore, the status of vector instructions issued from a scalar unit (SO), not shown, after the vector instruction being processed by the load/store vibe line 21 is as follows:
The process status register 22 displays (holds) information including vector instructions that have already been completed.

The operating system (O3) in the scalar unit (SU) branches to an interrupt processing routine (specifically, a page fault routine) in response to the interrupt notification signal (■) output from the vector unit (VU) 2, and acquires a page. Start processing.

If the page fault routine is successful, the operating system (OS)
The vector instruction in which the page fault occurred and the following vector instructions are stored in the vector unit (V
U) Reissue on 2.

When the vector instruction is reissued, the vector instruction in which the page fault occurred will process only the elements below the element indicated in the status register 210.

Regarding the vector instructions that follow, according to the contents held in the process status register 22, vector instructions that have already been completed are not executed (no operation), and vector instructions that are currently being executed are respectively In the calculation pipeline 20, the order of processing (for example, a vector calculation performed based on the calculation result in a certain calculation pipeline 20 is started after the vector calculation in the calculation pipeline 20 is finished) Accordingly, processing is restarted from the element held in the corresponding status register 200.

Of course, if the vector instruction before the vector instruction in which the page fault occurred was interrupted at the time the page fault occurred, processing is restarted from the interrupted element.

If the above page acquisition process fails to acquire a page, there is no point in executing the "program" that includes the vector instruction that caused the page fault. System (O
S) clears the process status register 22, clears the status registers 200 and 210 of each pipeline 20 and 21, and creates a new F program.
so that the reception can be attached.

In this way, the present invention provides a vector calculator (scalar unit) that processes vector operations using multiple pipelines.
SO), vector unit (VU), main memory (
vector unit (VU)
), for example, the load/store pipeline 21 and the arithmetic pipeline 20, a page fault is detected while executing a memory access instruction in the load/store pipeline 21, and each pipeline is Each pipeline 21 when vector processing in the line is interrupted.

Status registers 210 and 200 are provided to hold the vector instruction being executed in 20 and the restart element number, and when a page fault is detected in the load/store pipeline 21, the operating system of the scalar unit (SU) When a page fault is issued to the operating system (OS) and the page is acquired on the operating system (OS) side, the operating system (OS)
Based on the restart instruction (by reissuing the vector instruction) from the page fault, the page fault is restarted from the interrupted element in the load/store pipeline 21 and calculation pipeline 20, The feature is that even when a vector instruction that accesses memory is being executed in a vector computer that uses a virtual memory method, other vector instructions are executed in parallel in other calculation pipelines.

〔Effect of the invention〕

As described above in detail, the vector instruction multiprocessing method of the present invention is a vector computer that processes vector operations in multiple pipelines and processes vector instructions in a virtual storage space using an on-demand paging method. In the vector operation (VU), the main memory (MS
When a page fault occurs in a pipeline that accesses the main storage unit (MSU), vector instruction processing in all multiple pipelines is interrupted, and the pipeline that accesses the main storage unit (MSU) (load/store pipeline ) and the main memory 'It. A means (status register) is provided for both the bypass line (operation vibe line) that does not access the MSU (MSU) and the status of the vector instruction being processed on each vibe line (resuming element number, etc.) at the time of the above interruption. , the above page fault occurs,
Interrupt vector processing in each vibe line and the main memory bag above? ! (MSIJ) operating system (
O5), the operating system (
Based on a restart instruction from the operating system (OS), processing of a plurality of vector instructions suspended on each vibe line is restarted from the suspended state stored in the holding means (status register). Therefore, even in vector processing on the virtual memory space, it is possible to overlap and process multiple vector instructions other than vector load/store instructions, thereby significantly improving the processing capacity of the vector computer. It has the effect of

FIG. 2 is a diagram explaining a conventional vector instruction processing method.

It is.

In the drawing, The main storage unit (MSU).

2 is a vector unit (VU).

20 is the calculation vibe line.

200 is a status register.

21 is the load/store vibe line.

210 is a status register.

22 is a process status register.

■ is an interrupt notification signal or an interrupt.

are shown respectively.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

Claims (1)

[Claims] In a vector computer that processes vector operations using a plurality of pipelines (20, 21) and uses a virtual storage system using an on-demand paging system, the main storage (
When a page fault occurs in the pipeline (21) that accesses the main storage unit (MSU) (1), processing of vector instructions in all the pipelines (21, 20) is interrupted, and the main storage unit (MSU) ) (1) and the pipeline (20) that does not access the main storage unit (MSU) (1), each pipeline (21, 20) at the time of the above interruption. Means (210, 200) for holding the state of the vector instruction being processed is provided, so that when the page fault occurs, vector processing in each pipeline (21, 20) is interrupted, and the state of the vector instruction in the main storage unit (MSU) is interrupted. ) (1) When interrupting the operating system (OS) above, the holding means (2
10, 200), restarting processing of a plurality of vector instructions suspended in each pipeline (21, 20).