JPH08328854A - Pipeline data processor - Google Patents

Abstract

PURPOSE: To improve reliability for mis-cache processing and to improve performance by preventing a clock cycle from being lowered in a data processor of pipeline system. CONSTITUTION: When a main storage access instruction from an ISR 10 is executed and an error is detected in a cache directory 32, a mis-hit register 41 is set. Thereby, a pipeline control circuit 15 sets a mis-hazard flag 11 representing the numbers of a BR 13 and a GR 14 on which main storage data is loaded. Also, the circuit 15 cancels an instruction in a pipeline. The output of the flag 11 is compared with the numbers of the BR and the GR used by a new instruction in a hazard detection circuit 12, and when coincidence is obtained, the instruction is held with a D stage. When data is transferred from main storage, the flag 11 is reset, and the execution of the new instruction is started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline data processing device, and more particularly to a pipeline data processing device having a cache.

[0002]

2. Description of the Related Art In a conventional pipeline processing apparatus, while a cache miss is determined in a cache index and desired data is read from a main memory, the pipeline is held and data waiting is performed. Are controlled. Now, a conventional pipeline processing device having five stages shown in FIG. 4 will be described as an example. The 5 stages are an IF stage for fetching an instruction, a D stage for decoding an instruction and reading a register, an EA stage for executing an instruction or generating an address, and an operand access. There are a total of 5 stages including an O stage for performing the above and a W stage for storing the result. FIG. 4 shows an execution process of a pipeline processing an instruction in a steady state.

As described above, when the pipeline is flowing in an ideal state, the result of the instruction can be obtained every clock cycle. However, in the pipeline processing apparatus, pipeline stall occurs due to various factors. Typical of these are register hazard processing and cache miss processing.

The register hazard processing detects whether or not a register used in a certain instruction is updated by a preceding instruction, and if the register used is not yet updated,
If it is not usable, it means to stall the pipeline until it becomes usable. In order to perform the register hazard process, first, the register number obtained when the instruction is decoded in the D stage and the register update information indicating whether or not the register is updated are provided in the D stage and thereafter. The number of instructions existing in the stage is held. When the update of the register by one instruction is completed, the register update information about this instruction is invalidated. Then, when a new instruction is supplied to the D stage, the instruction on the D stage tries to use by comparing the register number used by this instruction with the register number updated by the preceding instruction held. It is detected whether the existing register is waiting for update, that is, whether a register hazard has occurred.
When the register hazard is detected, the IF stage and the D stage are held and the processing is made to wait until the contents of the register are updated. Register hazard processing is 1T depending on the difference in the pipeline control method and the number of pipeline stages.
Alternatively, it requires a processing time of 2T clock cycle.

The cache miss processing means that the desired data is not present in the cache when the cache is accessed, and the pipeline is stolen while the data is read from the main memory. FIG. 5 shows a state in which an operand cache miss occurs due to an operand access of instruction 2 in the conventional pipeline processing device. Because an operand mistake occurred in the O stage,
Until the desired data can be fetched from main memory, I
Holds F stage, D stage, AE stage, and O stage. When the desired data is fetched from the main memory, the IF stage, D stage and AE stage are fetched.
Processing is restarted. The cache miss process requires a processing time of 10's to 10's of Ts depending on the configuration of the main storage device. Since the pipeline data processing device continuously processes a plurality of instructions in each stage, when it is detected that a pipeline stall occurs, the stage where execution cannot be continued is immediately stopped. I have to hold it. Otherwise, the processing of multiple instructions will compete on the same stage, causing loss of instruction information, resource destruction, etc., and restarting the pipeline processing correctly when the stall is released. Because it will not be possible.

Pipeline strike due to cache miss
As a conventional technique for holding each stage in the case of occurrence of a rule, for example, Japanese Patent Laid-Open No. 2771/1993
There is a "memory access control system" described in Japanese Patent No. 843. In this technique, a clock is stopped by a signal that detects a cache miss, and a transition between each stage is suppressed by setting a stage transition inhibition signal so that each stage of the pipeline is controlled. There is a way to hold it.

[0007]

The method of stopping the clock used in the above-mentioned conventional pipeline data processing device increases the delay time of the entire device because the clock skew increases. It has a drawback that it greatly hinders the speedup of today's high-speed clock devices. Further, since the logical product of the clock and other logic is realized by the gate, noise is generated due to the time difference between this logic and the signal of the clock, and the reliability of the device is reduced.

Further, when a cache miss is made, a stage transition inhibiting signal is turned on, and the stage transition inhibiting signal is used to hold each stage of the pipeline. The target of the stage to be held is the stage in which the cache miss is detected and all the stages above (IF stage, D stage, AE stage and O stage) are held. Therefore, the delay time of the stage transition inhibiting signal is increased. Therefore, it is difficult to speed up the clock cycle of the pipeline data processing device, and there is a drawback that the system performance is deteriorated.

[0009]

A first pipeline data control device of the present invention is a copy of data in a main storage device.
Is a pipeline-type pipeline data processing device that has a cache for holding each block in block units and divides the execution of instructions into a plurality of stages for processing. (A) Cache hit or miss in a cache index (B) a canceling means for canceling the instruction in the pipeline when the cache miss is judged by the judging means, and (c) a cache miss display for displaying that the cache miss is being processed. Means, (d) a stagnation condition detection means for detecting a stagnation condition of pipeline processing, and (e) an output of the cache miss display means is input to the stagnation condition detection means, and the cache miss display means is lit. In this case, a newly issued instruction is detected, and the processing of the instruction is suspended until the lighting of the cache miss display means is extinguished. It includes a stage, a.

A second pipeline data control device of the present invention has a cache for holding a copy of data in a main memory in block units, and divides the execution of instructions into a plurality of stages. A pipeline data processing device of a pipeline system for processing, comprising: (a) a determining unit for determining a cache hit or miss in a cache index;
(B) canceling means for canceling an instruction in the pipeline when the judging means judges a cache miss, and (c) firmware notification for notifying the firmware when the judging means judges a cache miss. And (d) data reception notifying means for notifying the firmware that the request data has been received from the main storage device.

[0011]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a pipeline data processing apparatus showing a first embodiment of the present invention. In order to show the features of the present invention, non-important parts are omitted for the sake of clarity. In FIG. 1, an ISR 10 is a register that receives an instruction sent from an IF stage (not shown) through the signal line L1. ISR10
When the instruction is set to, processing according to the instruction is executed. In this embodiment, an instruction for loading the content of the main memory and storing it in a register will be described as an example.

FIG. 2 shows the instruction format used in this embodiment. The OP section is an operation code indicating the type of instruction,
The GR1 section is the number of a general-purpose register that stores the contents of the operand loaded from the main memory, and the BR section is the number of the base register that stores the base address for generating the address of the main memory to be loaded. The part indicates the number of the general-purpose register that stores the index value that modifies the address of the BR, and the part D indicates the displacement value from the address generated from the BR part and the GR part.

Next, the operation of the first embodiment will be described with reference to FIGS. 1, 2 and 3.

When the instruction shown in FIG. 2 is set in the ISR 10, the OP section, BR section and GR section are sent to the hazard detection circuit 12. The hazard detection circuit 12 learns from the OP section that the instruction is a load instruction from the main memory,
It is determined whether or not BR and GR required for address generation can be used, and the result is notified to the pipeline control circuit 15.

The pipeline control circuit 15 is a control circuit for controlling the entire pipeline, and is a hazard detection circuit 12
If the BR or GR specified by the command is not usable by the notification from, the D stage and IF stage are held to wait for the processing of the D stage until it becomes available. .

BR13 and GR14 are register files for holding a plurality of BRs and GRs designated by an instruction. BR number and G of instruction set in ISR10
The R number is supplied to BR13 and GR14 as an index address of BR13 and GR14. When the BR number and the GR number are supplied to BR13 and GR14, the desired BR and GR are read out, and BRD20,
It is set in GRD21.

BRD20 and GRD21 are registers for storing the contents of BR and GR read from BR13 and GR14, respectively. DD22 is ISR1
It is a register that stores the D part of the instruction set to 0.

ADD 23 is a 3-input address adder, and according to the load instruction set in ISR10, B
When the BR value, GR value and D value are set in RD20, GRD21 and DD22, a logical address is generated and L is generated.
Set to AR30.

The LAR 30 is a register for storing the logical address generated by the ADD 23. When the logical address is set, the content is supplied to the TLB 31, AA 32 and DA 33.

The TLB 31 is an address conversion buffer for converting a logical address into an absolute address designating an address on the main memory.

AA 32 is an address directory part of the operand cache, and DA 33 is a data array part of the open cache. The AA 32 stores the absolute address corresponding to the copy of the data on the main memory stored in the DA 33, and if it matches the absolute address converted by the TLB 31, the main memory data requested by the instruction is stored. −
If the data exists in the cache, that is, there is a hit, and there is a mismatch, the requested main memory data
Data does not exist in the cache, that is, it is missing.

The absolute address read from the TLB 31 and AA 32 is supplied to the comparator 34, and the addresses are compared. The comparator 34 outputs "1" when the values match, that is, a hit, and outputs "0" when the values do not match, that is, a miss. The comparison result of the comparator 34 is set in the hit-miss register 41 and notified to the pipeline control circuit 15.

When the operand cache is hit, the data read from the DA 33 is set in the DAR 40 through the selector 35. When the operand cache misses, the request to read the desired data is
It is output to a main storage device (not shown). The desired data read from the main memory is set in the DAR 40 from the signal line L5 through the selector 35 and DA3.
3 in the desired location.

The DAR 40 is a register for storing the operand data requested by the instruction, and the operand data is stored in the desired location of the BR 13 or GR 14 designated by the instruction. In this embodiment, the operand is stored at the position of GR14 designated by the GR1 part of the instruction.

Next, the operation of the cache miss process of the present invention will be described.

FIG. 3 shows a time chart when the instruction cache misses the instruction 2. At clock 5, a miss in the operand cache is detected at the O stage of instruction 2. Operand miss is hit miss register 4
It is set to 1 and notified to the pipeline control circuit 15.

The pipeline control circuit 15 uses the clock 6
Then, the entire pipeline is canceled through the signal line L3. Cancellation of the pipeline is an operation of resetting only the control circuit, and no control is performed on the data register. Therefore, conventional pipeline data
Processor, IF stage, D stage, AE
The load of delay is much smaller than that of holding all of the stage, O stage control circuit and data register.

By the way, since the instruction 1 has reached the W stage at the clock 5, only the instruction 1 is not canceled at the clock 6, and the instruction is completed. Thus, although not shown, the instruction counter, which is updated upon completion of the instruction, is updated to specify instruction 2 at clock 6.

The pipeline control circuit 15 uses the clock 7
At the same time, it requests the re-execution of the instruction 2 designated by the instruction counter from the IF stage, and at the same time sets the mishazard flag 11.

The mishazard flag 11 requests the hazard detection circuit 12 to unconditionally detect a hazard with respect to the instruction set in the ISR 10. Therefore, when the instruction 2 is set in the ISR 10 at the clock 8, the hazard is unconditionally detected and until the cause of the hazard is removed, that is, the mishazard flag 11 is reset. The IF stage and the D stage are held by the D stage hold signal sent from L4. This IF stage and D stage hold uses the existing hold detection circuit for hazard detection.
F stage, D stage, AE stage and O stage
The delay load is much less than holding the switch.

The main memory device notifies the pipeline data processing device through the signal line L2 that the data will arrive two clocks before the requested data reaches the pipeline data processing device. The signal on the signal line L2 resets the mishazard flag 11 to release the pipeline stall.

It has to be noted here that the instruction 2 has already completed the existing hazard check at clock 3. Therefore, no other hazard factor is detected in the instruction 2 and the processing is executed without delay. And clock N
The desired data sent from the main memory at the signal line L5
Is stored in the DA 33 through the selector 35 and is set in the DAR 40 through the selector 35. At this time, the hit-miss register 41 again informs the pipeline control circuit 15 of the miss of the operand cache. Processing is suppressed.

The data set in the DAR 40 is stored at a desired location in the GR 14 at the clock N + 1, and the processing of the instruction 2 is completed.

In the second embodiment of the present invention, instead of providing the mishazard flag 11, the pipeline control circuit 1
An interrupt is sent to the firmware in accordance with the instruction from 5, and the device waits in the idle state through the signal line L2 until there is a notification of the data transfer from the main storage device. After receiving the data transfer report, the instruction 2 Is re-executed from the IF stage to reduce the hardware. In order not to increase the number of cache miss processes T, the data transfer report from the main memory may be received 1T earlier.

[0036]

As described above, the pipeline data processing device of the present invention has the effect that noise is not generated and reliability is maintained because the clock is stopped when a cache miss is detected. Further, since it is not necessary to hold all the stages before the cache index stage by the stage transition inhibition signal, the clock skew is not increased, and the pipeline data processing device is provided. Pipeline ho, which was critical in constructing
Since the delay time of the clock signal can be significantly reduced, the clock cycle of the pipeline data processing device can be speeded up, and the processing performance of the system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a format diagram of a load instruction used in the embodiment of the present invention.

FIG. 3 is a timing chart showing cache miss processing according to the embodiment of this invention.

FIG. 4 is a timing diagram illustrating an embodiment of the present invention and prior art pipeline processing.

FIG. 5 is a timing diagram showing prior art cache miss processing.

[Explanation of symbols]

 10 instruction register (ISR) 11 miss hazard flag 12 hazard detection circuit 13 base register file (BR) 14 general purpose register file (GR) 15 pipeline control circuit 20 base register receiving register (BRD) 21 general register receiving Register (GRD) 22 Displacement receiving register (DD) 23 Address adder 30 Logical address register (LAR) 31 Address conversion buffer (TLB) 32 Address array (AA) 33 Data array (DA) 34 Comparator 35 Selector 40 Data register (DAR) 41 Hit miss register L1 to L5 Signal line

Claims (2)

[Claims] 1. A pipeline type pipeline data having a cache for holding a copy of data in a main memory in block units and dividing instruction execution into a plurality of stages for processing. In the processing device, (a) determining means for determining a cache hit or miss in the cache index, (b) canceling means for canceling an instruction in the pipeline when the determining means determines a cache miss, and (c) ) A cache miss display means for displaying that the cache miss processing is in progress, and (d) a stagnation condition detection means for detecting a stagnation condition of the pipeline processing,
(E) Until the output of the cache miss display means is input to the stagnation condition detection means and the newly issued instruction is detected when the cache miss display means is lit, and the lighting of the cache miss display means goes out. A pipeline data processing device comprising: a holding means for holding the processing of the instruction. 2. A pipeline data of a pipeline system having a cache for holding a copy of data in a main memory in block units and processing an instruction execution by dividing it into a plurality of stages. In the processing device, (a) determining means for determining a cache hit or miss in the cache index, (b) canceling means for canceling an instruction in the pipeline when the determining means determines a cache miss, and (c) ) Firmware notifying means for notifying the firmware when a cache miss is judged by the judging means, and (d) data reception for notifying the firmware that request data has been received from the main storage device. A pipeline data processing device comprising: a notification means.