JPH073147U - Integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Preventing the occurrence of latch-up phenomenon in CMOS integrated circuits. [Configuration] The first route 106 and the second route 107
Connected to the output terminal 101 along the boundary line between the p well 110 and the n substrate 111, the n bulk 108 for setting the potential of the n substrate 111 to the VDD potential and the p bulk 108 for setting the potential of the p well 110 to the VSS potential. By forming the bulk 109, the vicinity of the boundary between the p well 110 and the n substrate 111 is surely set to the VSS potential and the VDD potential, respectively.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a structure of a complementary field effect transistor (hereinafter referred to as CMOS) integrated circuit which prevents latch-up.

[0002]

[Prior art]

 The latch-up phenomenon is a phenomenon in which a large amount of current flows between the power supply for maintaining the potential of the p-well in the CMOS and the power supply for maintaining the potential of the n-substrate, which impairs the operation of the CMOS circuit. is there. This latch-up phenomenon is caused by the thyristor circuit by the parasitic bipolar transistor which is formed due to the structure of CMOS.

The latch-up phenomenon will be described with reference to the drawings. FIG. 2 is a sectional view showing the structure of the CMOS.

As shown in FIG. 2, the n-bulk 205 is a contact region with a power supply for setting the n-substrate 203 to the VDD201 potential, and the p-bulk 206 is for setting the p-well 204, which is the p-region, to the VSS202 potential. This is the contact area with the power supply.

The p gate 207 is a p-type MOS transistor gate formed on the n substrate 203, and the n gate 208 is an n-type MOS transistor gate formed on the p well 204.

The internal resistance Rp 212 represents the internal resistance of the p well 204 determined by the potential distribution inside the p well 204, and the internal resistance Rn 211 represents the internal resistance of the n substrate 203 determined by the potential distribution inside the n substrate 203. Show.

The first transistor 209 is a parasitic transistor in which the source of the p gate 207 is the emitter, the n substrate 203 is the base, and the p well 204 is the collector.

On the other hand, the second transistor 210 is a parasitic transistor in which the source of the n gate 208 is an emitter, the p well 204 is a base, and the n substrate 203 is a collector.

FIG. 3 is a circuit diagram showing an equivalent circuit of the transistor in FIG. When a trigger current Ia212 above a certain amount is generated on the substrate side and a potential difference due to the internal resistance Rp212 occurs between VSS202 and the base of the second transistor 210, the second transistor 210 is turned on and VDD201 and VSS202 are connected. A current Ib213 flows through the internal resistance Rn211.

Further, if the current Ib 213 is sufficient to turn on the first transistor 209, the trigger current Ia 212 continues to flow between VDD 201 and VSS 202.

Due to the above circulation, a large current always flows between VDD 201 and VSS 202, which causes latch-up.

One of the countermeasures against this latch-up phenomenon is to set the formation positions of the p bulk 206 and the n bulk 205 near the boundary between the n substrate 203 and the p well 204, and stabilize the potential distribution to reduce the internal resistance Rp212. There is a method of lowering the resistance value with the internal resistance Rn211.

FIG. 4 is a plan view showing an output terminal portion of a COG integrated circuit in which a conventional integrated circuit chip is directly mounted on a glass substrate.

As shown in FIG. 4, an output terminal 101 is formed in the center, and a first MOS transistor gate 102 that is a p gate, a second MOS transistor gate 103 that is a p gate, and n A third MOS transistor gate 104, which is a gate, and a fourth MOS transistor gate 105, which is an n gate, are formed.

The outputs of the respective MOS transistor gates 102, 103, 104, 105 are shortest distance by the first output line 306, the second output line 307, the third output line 308, and the fourth output line 309. Connected by.

A first n-bulk 310 for contacting the VDD power supply with the n-substrate 111 is formed by forming aluminum on the active region 3 in contact with the VDD power supply and forming a contact hole 1 to thereby form a bulk resistance value. Is lowered.

The second n bulk 311 is connected to the first n bulk 310 via the active region 3 in the second output line 307 region, and aluminum is formed on the active region 3 to form the contact hole 1. This reduces the bulk resistance.

The third n bulk 315 is connected to the first n bulk 310 via the active region 3 of the first output line 306 region, and aluminum is formed on the active region 3 to form the contact hole 1. This reduces the bulk resistance.

Further, the first p-bulk 312 for contacting the p-well 110 with the VSS power source is formed by forming aluminum on the active region 3 in contact with VSS and forming the contact hole 1. Has lowered the resistance value of.

The second p bulk 313 is connected to the first p bulk 312 via the active region 3 of the third output line 308 region, and aluminum is formed on the active region 3 to form the contact hole 1. This reduces the bulk resistance.

The third p bulk 314 is connected to the first p bulk 312 via the active region 3 in the fourth output line 309 region, and aluminum is formed on the active region 3 to form the contact hole 1. This reduces the bulk resistance.

[0022]

[Problems to be solved by the device]

 In the conventional configuration shown in FIG. 4, since low resistance aluminum is formed in the vicinity of the first n bulk 310 having the lowest power supply resistance, the VDD potential is reliably achieved and the internal resistance Rn211 is relatively low. .

On the other hand, the second n bulk 311 and the second output line 307 region are connected to the VDD power supply via the high resistance active region 3, so that the potential of the n substrate 111 is relatively wide. This has a distribution, and the potential difference near the pn junction formed by the p well 110 and the n substrate 111 becomes small, which causes a latch-up phenomenon.

The relationship between the first p bulk 312, the second p bulk 313, and the third p bulk 314 is similar.

It is an object of the present invention to solve these problems and provide an integrated circuit configuration capable of preventing the latch-up phenomenon of the integrated circuit.

[0026]

[Means for Solving the Problems]

 In order to achieve the above object, the integrated circuit of the present invention takes the following means.

The integrated circuit of the present invention is an integrated circuit having an output terminal surrounded by a plurality of MOS transistor gate groups each of which is composed of a first MOS transistor gate group and a second MOS transistor gate group. And an output path to the output terminal is provided with a first path formed by the output of the first MOS transistor gate group and a second path formed by the output of the second MOS transistor gate group, It is characterized in that the first path and the second path are provided in parallel with the boundary line between the n substrate and the p well.

In the integrated circuit of the present invention, the first MOS transistor gate group and the second MOS transistor gate group have the output of the MOS transistor gate formed on the n substrate and the output of the MOS transistor gate formed on the p well. It is characterized by being composed of and.

In the integrated circuit of the present invention, a contact region with a power source is provided in a region surrounded by the first path, the second path, the MOS transistor gate group formed in the p-well or the n-substrate, and the output terminal. Is characterized by.

[0030]

[Action]

 One of the causes of the latch-up phenomenon is that the potential of the boundary line between the p-well 204 and the n-substrate 203 in FIG. 2 is not completely the p-well 204 at the VSS202 potential and the n-substrate 111 at the VDD201 potential. Sometimes.

This means that the difference between the base potential and the collector potential of the first transistor 209 becomes small, and at the same time, the difference between the base potential and the emitter potential of the second transistor 210 becomes small and each transistor turns on. It is equivalent to becoming easier.

By the way, in the vicinity of the second output line 307 in FIG. 4, connecting only in the active region 3 having a relatively high resistance value is effective in the subsequent regions (including the second n bulk 311). Since the potential does not easily reach the VDD potential, the latch-up phenomenon easily occurs.

The same applies to the vicinity of the third output line 308 and the fourth output line 309.

Therefore, the second output line, the third output line, and the fourth output line are routed to form a first route and a second route along the boundary line between the p well and the n substrate. By connecting to the output terminal, aluminum and contact holes are formed in the active regions near the second output line, the third output line, and the fourth output line to lower the resistance and stabilize the potential. .

[0035]

【Example】

 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing an output terminal portion of an integrated circuit according to an embodiment of the present invention.

As shown in FIG. 1, an output terminal 101 is formed in the center and surrounds it, a first MOS transistor gate 102 which is a p gate, a second MOS transistor gate 103 which is a p gate, and n. A third MOS transistor gate 104, which is a gate, and a fourth MOS transistor gate 105, which is an n gate, are formed.

The first path 106 and the second path 107 are formed on the n-substrate 111 and the p-substrate 111 so that the resistance of the n-bulk 108 and the p-bulk 109, which is a contact region between the power source and the substrate, are not obstructed. A path along the boundary with the well 110 to the output terminal 101 formed of aluminum.

The output of the first MOS transistor gate 102, which is a p-gate corresponding to the first MOS transistor gate group, and the output of the fourth MOS transistor gate 105, which is an n-gate, are They are connected by a route 106.

The output of the second MOS transistor gate 103, which is a p-gate corresponding to the second MOS transistor gate group, and the output of the third MOS transistor gate 104, which is an n-gate, are They are connected by a path 107.

The n-bulk 108 formed between the first MOS transistor gate 102 and the second MOS transistor gate 103 and the p-well 110 is formed by forming aluminum on the active region 3 which is in contact with the VDD power supply. By forming the hole 1, the resistance value of the bulk is lowered, and the n substrate 111 region between the first MOS transistor gate 102 and the p well 110 and between the second MOS transistor gate 103 and the p well 110 is formed. Make sure that it is at the VDD potential.

Furthermore, the p-bulk 109 formed between the p-well 110 and the third MOS transistor gate 104 and the fourth MOS transistor gate 105 forms aluminum on the active region 3 in contact with the VSS power supply. Then, by forming the contact hole 1, the resistance value of the bulk is lowered, and between the third MOS transistor gate 104 and the n substrate 111, and between the fourth MOS transistor gate 105 and the n substrate 111. The p well 110 region is surely set to the VSS potential.

In the above description, the n-type substrate and the p-type well are used, but the present invention can be similarly applied to the configurations of the n-type and p-type substrates and the p-type and n-type wells.

[0043]

[Effect of device]

 As is clear from the above description, the integrated circuit according to the present invention increases the difference between the base potential and the collector potential of the conventional first transistor, and further increases the difference between the base potential and the emitter potential of the second transistor. growing. Therefore, it is possible to obtain an integrated circuit that is less likely to cause the latch-up phenomenon.

[Brief description of drawings]

FIG. 1 is a plan view showing an output terminal portion of an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a sectional structure of a CMOS.

FIG. 3 is a circuit diagram showing an equivalent circuit of a CMOS structure.

FIG. 4 is a plan view showing an output terminal portion of a conventional integrated circuit.

[Explanation of symbols]

 101 output terminal 102 first MOS transistor gate 103 second MOS transistor gate 104 third MOS transistor gate 105 fourth MOS transistor gate 106 first path 107 second path 108 n-bulk 109 p-bulk 110 p-well 111 n substrate

Claims (3)

[Scope of utility model registration request] 1. An integrated circuit having an output terminal surrounded by a plurality of MOS transistor gate groups each including a first MOS transistor gate group and a second MOS transistor gate group, the output circuit comprising: Of the first MOS transistor gate group and a second path constituted by the output of the second MOS transistor gate group are provided as the output paths of the first and second paths. Is provided in parallel with the boundary line between the n substrate and the p well. 2. The first MOS transistor gate group and the second MOS transistor gate group according to claim 1, wherein the output of the MOS transistor gate formed on the n substrate and the output of the MOS transistor gate formed on the p well are provided. An integrated circuit comprising: 3. A contact region with a power supply is provided in a region surrounded by the first path, the second path, the MOS transistor gate group formed on the p well or the n substrate, and the output terminal according to claim 1. An integrated circuit characterized by.