KR100399367B1 - Semicondvctor device for protecting an ntegrated circvit prom external transients - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a well region having first and second MOS transistors connected in series between a first terminal and a second terminal, wherein the first MOS transistor and the second MOS transistor have a predetermined depth and concentration. Connected through. The depth and concentration of the well region is deeper and smaller than the active region of the MOS transistors.

Description

Semiconductor device with electrostatic discharge protection {SEMICONDVCTOR DEVICE FOR PROTECTING AN NTEGRATED CIRCVIT PROM EXTERNAL TRANSIENTS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection device for an integrated circuit, and more particularly to a semiconductor device for electrostatic discharge (ESD) protection in an output circuit of an integrated circuit.

In recent integrated circuit technologies, products and processes are developed to cope with high-speed operation and low power consumption, such as products such as SOC (System On Chip). In responding to high speed operation, the characteristics of the active and passive components that make up the circuit are important factors that determine the performance of the integrated circuit product. In particular, in the transistor which is a typical active element, the parasitic resistance and parasitic capacitance present in the structure of the transistor should be reduced as much as possible with the increase in the saturation current between the drain and the source. In the process for reducing the parasitic resistance Rd (drain side parasitic resistance, Rs; source side parasitic resistance) of the MOS transistor shown in FIG. 1A, as shown in FIG. 1A, the gate, source and drain of the transistor Self-aligned silicidation (salicidation) technology is used to form silicon with low resistance on its surface by self-reaction. When the self-aligned silicification method is applied, the transistor characteristics are improved due to the reduction of parasitic resistance, but the effective junction area acts as a discharge area of the transistor when an extraneous signal such as ESD is introduced from the outside. ) Is limited to the lower region of the gate polysilicon layer GP spacer GS. As a result, when electrical transients, such as electrostatic discharge (ESD) or electrical overstress (EOS), flow through the pads, physical damage due to small discharge areas It is generated that such a transistor (having the structure shown in Fig. 1C) becomes impossible to use a product employing a protection element.

Therefore, when the self-aligned silicification method is applied, a protection circuit that can replace a transistor having low ESD characteristics should be used. Such a protection circuit includes a diode or a silicon controlled rectifier (SCR). However, in the integrated circuit device, since the MOS transistor is basically used in the output driving circuit, at a voltage lower than the turn-on voltage (or snap-back voltage) of the horizontal NPN bipolar transistor (LNPN) parasitic to the MOS transistor. A protection circuit capable of flowing a large amount of current is desirable (discharge before the MOS transistor of the output circuit is destroyed by excess instantaneous components). However, since the turn-on voltage of most protection elements is larger than the parasitic LNPN, such protection circuits (with a large current driving capability at low turn-on voltages) have practical application difficulties. Thus, as a method for increasing the turn-on voltage of the parasitic LNPN, the base width of the parasitic LNPN bipolar transistor may be increased, or as shown in FIG. In connection to increase the forward turn-on voltage between the source (emitter of parasitic LNPN) and the P-type substrate (base of LNPN).

In the above-described method of increasing the bay width of the parasitic LNPN, an output circuit is formed of an enMOS transistor in which the gate length (the longer the gate length is increased) is increased so that the turn-on voltage is larger than the protection circuit. However, such a method can make the turn-on voltage of the output circuit larger than the protection circuit, but has a disadvantage in that the circuit area must be enlarged to compensate for the low current driving capability. On the other hand, in the case of adding the resistor Rs to the output circuit 10 as shown in FIG. 2, the activation of the parasitic LNPN can be suppressed. Increasing the circuit area to compensate for the deterioration is inevitable.

Another way to prevent the damage of the EnMOS transistor (e.g., shown in FIG. 2) by increasing the turn-on voltage of the output circuit higher than that of the protection circuit is shown in FIG. 3A, the output circuit 11 ) And the NMOS transistors constituting the protection circuit 12 are connected in series to extend the base width of the parasitic LNPN. There are two ways to form this structure, one shown in FIGS. 3B and 3C and the other shown in FIGS. 3D and 3E.

First, in FIGS. 3B and 3C, the active regions (or N + diffusion regions) of the two NMO transistors N1 and N2 are separated, and the drain and ground voltages of the NMO transistor N1 connected to the pad PAD. A source of the enmo transistor N2 connected to (Vss) is connected through the metal line (M). 3D and 3E show a structure in which the source and the drain of the NMOS transistors N1 and N2 are connected through the active region for efficient use of the circuit area.

However, in the structures shown in FIGS. 3B-3E, the base width between the drain connected to the pad PAD (collector of the parasitic LNPN) and the source connected to the ground voltage Vss (emitter of the parasitic LNPN) is increased. Activation of the parasitic LNPN can be suppressed (the turn-on voltage of the LNPN is increased), but as shown in the equivalent circuit of FIG. 3F, a parasitic bipolar transistor Q3 with an extended base width is formed, and the low current gain of Q3 (β; The collector current increase / base current increase) causes the ESD characteristic to deteriorate.

In addition to these circuit improvements, a process for improving the ESD characteristics of the MOS transistor to which the self-aligned silicification method is applied is shown in FIGS. 4 and 5. In FIG. 4, after the N + source S and the drain region D are formed by the ion implantation process, an insulating film formed on the top surface of the polysilicon gate layer GP and the top surface of the source / drain region as a separate mask process ( Remove part of 41). Then, openings 42 are formed in which only a portion of the surface of the gate layer GP and the source and drain regions are exposed. Then, when local salicidation is performed using the remaining insulating film 41 as a mask, a structure in which silicide films 44 are formed on the gate layer and some surfaces of the source and drain regions is obtained. Since the structure of FIG. 4 is the same as the conventional structure which does not apply the self-aligning silicification method, it is a process technology that can increase the discharge area for an externally transmitted signal such as ESD. However, there is a difficulty in high frequency operation due to an increase in manufacturing cost by using a separate mask and an increase in parasitic resistance components. In addition, since a precise operation of exposing only a part of the surfaces of the gate layer and the source and drain layers is required, it is difficult to proceed in consideration of the trend of high integration such as reduction of circuit size or alignment margin.

In FIG. 5, after forming the source and drain regions, a high energy ion implantation process using a mask process is performed to further extend the diffusion region S 'below the existing source S and the drain diffusion region D. , D '), and then undergo self-alignment silicification to complete the enMOS transistor. In the structure of FIG. 5, the bonding area with the substrate is enlarged by the deeper diffusion regions S 'and D', so that the discharge area can be secured, but additional mask process is required. There is this. In addition, the degree of improvement of the actual ESD characteristics is not so great.

Accordingly, an object of the present invention is to provide a semiconductor device having reliable ESD protection characteristics in an integrated circuit including transistors fabricated by a self-aligned silicide method.

Another object of the present invention is to provide a semiconductor device having reliable ESD protection without using a separate process in an integrated circuit including transistors fabricated by a self-aligned silicide method.

In order to achieve the above object of the present invention, the present invention, in the semiconductor device, having a first and a second MOS transistor connected in series between the first terminal and the second terminal, the first MOS transistor and the second MOS transistor Is connected through a well region having a predetermined depth and concentration. The depth and concentration of the well region is deeper and smaller than the active region of the MOS transistors.

The first and second MOS transistors are composed of NMOS transistors, and their connection relationship has various connection schemes in the embodiment of the present invention. That is, in the case of the NMOS transistors, the power supply voltage and the predetermined internal signal are respectively connected.

In addition, the gates of the first and second MOS transistors are commonly connected to a predetermined internal signal or respectively connected to a separate internal signal.

1A and 1B are equivalent circuit diagrams of enmos and pimos transistors, respectively.

1C is a cross-sectional structure diagram of a MOS transistor.

2 is a circuit diagram of a conventional semiconductor device in which a resistor is added to an output circuit.

3A is a circuit diagram of a conventional semiconductor device in which an NMOS transistor is connected in series.

3B and 3C are plan and cross-sectional structural views of a conventional semiconductor device in which the circuit of FIG. 3A is realized.

3D and 3E are plan and cross-sectional structural views showing another example of the conventional semiconductor device in which the circuit of FIG. 3A is realized.

3F is an equivalent circuit diagram of parasitic bipolar transistors by the semiconductor devices shown in FIGS. 3B-3E.

4A to 4B are process flowcharts showing a process of manufacturing an enMOS transistor using a partial self-silification method.

5A and 5B are process flow diagrams showing a manufacturing process of an NMOS transistor including an ion implantation step.

6 and 7 are plan and cross-sectional structural views of a semiconductor device according to the present invention.

8 is an equivalent circuit diagram of parasitic bipolar transistors according to the structure of FIG. 6 or FIG.

9A to 9C show embodiments regarding their gate connection when the semiconductor device of the present invention is composed of enMOS transistors.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 6 and 7 are plan and cross-sectional schematic diagrams of a device according to the invention, in which the two enMOS transistors in the above-described output circuit (eg 11 in FIG. 3A) are connected between the pad PAD and the ground voltage GND. This is the case where the structure according to the present invention is applied to a circuit structure connected in series.

6 and 7, the structure of the output circuit according to the present invention is symmetrically around the drain region D1 of the NMOS transistor N1 connected to the pad PAD. Each of the fields N1 and N2 has a dual structure. The source region S1 of the NMOS transistor N1 and the drain region D2 of the NMOS transistor N2 are common to each other through the N-type wells 60 and 61. The N type wells 60 and 61 are formed in the substrate 50 between the gates G1 and G2 of the NMOS transistors N1 and N2. The gate of the NMOS transistor N1 and the gate of the NMOS transistor N2 are those formed by the above-described self-silification method, and the output NG from the power supply voltage VDD and the control circuit, respectively. ) The drain region D1 of the NMOS transistor N1 and the source region S2 of the NMOS transistor N2 are connected to the pad PAD and the ground voltage GND through the metal layer M, respectively.

In such a structure, as shown in FIG. 7, a low concentration is formed between the emitter of the parasitic bipolar transistor Q1 and the collector of the parasitic bipolar transistor Q2 formed between the pad PAD and the ground voltage GND. Since the n type wells 60 or 61 are formed, the current gain of the horizontal NPN transistor is nearly zero. Therefore, activation of the horizontal NPNs that degrade the ESD characteristics is almost suppressed and electrostatic discharge is made through the N + diffusion region and the N + / P- junction diode by the P- substrate. That is, referring to FIG. 8, which shows an equivalent circuit of parasitic bipolar transistors in the structure according to FIGS. 6 and 7, the parasitic bipolar transistors Q1 and Q2 are disposed between the pad PAD and the ground voltage GND. Formed, but Q1 and Q2 are not turned on by emitter bias of Q1 or collector bias of Q2. That is, the emitter of Q1 and the collector of Q2 are separated from each other by the N type wells 60 or 61, and the impedance Z therebetween becomes infinite. Further, since the current gain is close to zero by the N type well 60 or 61 formed between the collector and emitter of the bipolar transistor Q3 formed in FIG. 3F, Q3 does not exist on the equivalent circuit. As a result, it can be seen that the low concentration N-type well 60 or 61 deeply formed in the substrate 50 eliminates the horizontal NPN operation, thereby improving the ESD characteristics. The process of forming the N type well 60 or 61 may be performed by adjusting only the ion implantation energy and the concentration by applying the existing N type well formation mask as it is, and thus additionally, as in the case of FIG. 4 or 5 described above. No mask process or ion implantation process is required.

In the structure shown in FIGS. 6 to 7, the gate of the NMOS transistor N1 connected to the pad PAD is connected to the power supply voltage VDD and the gate of the NMOS transistor N2 connected to the ground voltage is connected to the control circuit. Although it was connected to the output NG, as shown in FIGS. 9B to 9C, the gate connection form of the two NMOS transistors was connected in series between the pad PAD and the ground voltage GND. Can be modified differently. For example, as shown in FIG. 9B, two gates are commonly connected to the output NG of the control circuit, or as shown in FIG. 9C, to different outputs NG1 and NG2 applied from the control circuit. Each gate is connected.

In addition, in the above-described embodiment of the present invention, when the gates of the MOS transistors are formed by the self-sintering method, but do not have a gate formed by the self-sintering method because there is an effect of suppressing the activity of the horizontal bipolar transistor by the well. It should be understood that the present invention can be applied to improve the ESD characteristics.

As described above, the present invention connects the diffusion regions of the MOS transistors of the series-connected output circuit through a low concentration well deeper than the diffusion regions that become their source or drain regions, thereby reducing the deterioration of the ESD characteristics by the horizontal parasitic bipolar transistors. It has a suppressing effect. In addition, the present invention has the advantage of providing a semiconductor device having improved ESD characteristics without using an additional mask process.

Claims (8)

A semiconductor device having first and second MOS transistors connected in series between a first terminal and a second terminal, the semiconductor device comprising: A first active region of a first concentration formed on a semiconductor substrate and connected to the first terminal; A second active region of the first concentration formed on the semiconductor substrate and spaced apart from the first active region and connected to the second terminal; And A third active region of a second concentration on the semiconductor substrate spaced apart from the first and second active regions and formed deeper than the first and second active regions; The first and second active regions become drain regions of the first and second transistors, respectively, and the third active region becomes a common source-drain region of the first and second transistors, respectively. And the second concentration is lower than the first concentration. The method of claim 1, And wherein the first terminal is a pad and the second terminal is a ground voltage. The method of claim 1, And wherein the first terminal is a power supply voltage and the second terminal is a pad. delete The method of claim 1, And the gates of the first and second MOS transistors are connected to a power supply voltage and a predetermined internal signal, respectively. The method of claim 1, And the gates of the first and second MOS transistors are connected to predetermined internal signals and reference voltages, respectively. The method of claim 1, And the gates of the first and second MOS transistors are commonly connected to a predetermined internal signal. The method of claim 1, And the gates of the first and second MOS transistors are connected to predetermined first and second internal signals, respectively.