JPH07307875A - Reference signal generating circuit - Google Patents

Abstract

PURPOSE:To obtain a reference signal generating circuit generating a more stable reference clock signal with a simpler configuration circuit. CONSTITUTION:A synchronizing signal detector 11 detects the position of a subcarrier signal and a BPF 10 extracts a subcarrier signal from an image signal. A VCO 13 oscillates a 1st AC signal and a frequency divider 14 divides the frequency of the oscillated signal. A phase comparator 12 detects the phase difference between the subcarrier signal and the 1st AC signal to match the phase of the 1st AC signal with that of the subcarrier signal. The 1st AC signal is frequency-divided by a frequency divider 15 and the synchronization of the phase with a 2nd AC signal is taken in a phase comparator 16. It is not required to generate an AC signal with a uselessly higher frequency through the configuration of 2-stages of PLL circuits and a reference clock signal synchronously with the subcarrier signal is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference signal generation circuit, and more particularly to an NTSC (National Television System Comm).
It relates to a reference signal generation circuit used in an apparatus for quantizing and processing an image signal of the ittee system.

[0002]

2. Description of the Related Art Conventionally, as is well known in television broadcasting, a synchronizing signal (SYNC) is transmitted by an image transmission system in order to synchronize the image reproducing operation on the receiving side with the image capturing operation on the transmitting side. The sync signal is a composite sync signal obtained by synthesizing two kinds of sync signals, that is, a horizontal sync signal and a vertical sync signal. The sync signal is inserted in the blanking signal of the normal image signal with negative polarity and transmitted. Further, in the NTSC color television, since the color subcarrier is suppressed, the color burst signal is sent on the receiving side for the purpose of forming a carrier in phase with the correct color synchronization.

The reference signal generating circuit used for reproducing the television signal described above, for example, generates a 13.5 MHz reference clock from a horizontal synchronizing signal (SYNC) as shown in FIG. A horizontal sync signal detected by the sync signal detector 20 in the reference signal generation circuit and a voltage control oscillator (VCO)
A single-stage PLL that compares the phase with a 13.5 MHz 858 divided signal 23 oscillated by 22 and controls the VCO with an electric signal generated by the phase difference.
(Phase-locked loop) circuit is provided.

Japanese Patent Laid-Open No. 2-228882 is a prior art example related to the technical contents of the present invention. This is to form a horizontal synchronizing signal using the color subcarrier as a reference signal, and the circuit is configured to monitor the phase shift and correct the phase shift only when the phase shift exceeds a predetermined amount.

As another example of the prior art, JP-A-2-26
No. 0285, there is provided a second reference clock in which two stages of PLL circuits each composed of a phase comparator, a loop filter, a VCO and a frequency divider are provided in a cascade connection, and a first reference clock and a frequency are variable. And form.

[0006]

However, in the above-mentioned conventional reference signal generating circuit, the reference clock is generated from the horizontal synchronizing signal of the input image. The horizontal synchronizing signal contains noise of the input image, and the generated signal is apt to cause jitter, and the obtained reference signal has a problem of lack of stability.

Further, referring to the above-cited publications and the like, when the intended reference signal (13.5 MHz) is simply generated by one PLL circuit using the color burst signal as a reference signal, the burst signal (about 3.58 MHz), the reference clock signal (13.5 MHz), and the frequency division ratio of the frequency divider for phase comparison, etc., it becomes necessary to oscillate a signal having a frequency of giga Hz in the VCO. Such a circuit is not practical.

An object of the present invention is to provide a reference signal generation circuit which enables more stable generation of a reference clock with a simpler configuration circuit.

[0009]

In order to achieve the above object, a reference signal generating circuit of the present invention is a reference signal generating circuit used in an apparatus for processing an image signal of NTSC system, which is a subcarrier signal rather than an image signal. And a first oscillating means for oscillating a first AC signal, and a first phase comparing means for detecting a phase difference between the subcarrier signal and the first AC signal. A first PLL circuit, a second oscillating unit that oscillates a second AC signal, and a second phase comparing unit that detects a phase difference between the second AC signal and the first AC signal. And a second PLL circuit configured as described above.
The AC signal of the second subcarrier signal is synchronized with the second
In the PLL circuit, the second AC signal is synchronized with the first AC signal to generate the second AC signal as an output signal synchronized with the subcarrier signal.

In the reference signal generating circuit, the first PLL circuit further detects a synchronizing signal from the image signal and generates a position signal indicating the position of the subcarrier signal in the image signal, and a first synchronizing signal detecting means. A first frequency dividing means for frequency-dividing the AC signal and outputting a first frequency-divided signal;
The phase difference between the subcarrier signal and the first AC signal in the phase comparison means is detected based on the position signal and the frequency-divided signal, and the second PLL circuit further frequency-divides the first AC signal. Second frequency dividing means for outputting a second frequency divided signal;
Of the phase difference between the first AC signal and the second AC signal in the second phase comparison means. The detection may be performed based on the second frequency-divided signal and the third frequency-divided signal.

Furthermore, the first AC signal is approximately 14.3 MHz.
And the second AC signal may be a signal of about 13.5 MHz.

[0012]

Therefore, according to the reference signal generating circuit of the present invention, the subcarrier signal is extracted from the image signal, the first AC signal is oscillated, and the phase difference between the subcarrier signal and the first AC signal is detected to detect the phase difference. The first AC signal is synchronized with the subcarrier signal, oscillates the second AC signal, detects the phase difference between the second AC signal and the first AC signal, and detects the second AC signal as the first AC signal. Synchronized with AC signal. Therefore, the second AC signal becomes a signal synchronized with the subcarrier signal by the two-stage PLL circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a reference signal generating circuit according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, an embodiment of the reference signal generating circuit of the present invention is shown as a circuit block diagram. The reference signal generating circuit of the embodiment is composed of two-stage PLL circuits of a first stage and a second stage.

The first-stage PLL circuit is a bandpass filter (BPF) 10 for extracting a 3.58 MHz subcarrier signal from the input image signal, and also detects a horizontal synchronizing signal from the input image signal to indicate the position of the burst signal. A phase difference signal using the sync signal detector 11 for issuing a burst flag signal, the subcarrier signal extracted by the BPF 10, the burst flag signal output from the sync signal detector 11 and the feedback signal output from the frequency divider 14 as input signals. The VCO 15 that oscillates a 14.3 MHz signal synchronized with the subcarrier signal based on the output signal of the phase comparator 12 that outputs the And the divider 14.

The second-stage PLL circuit outputs the signal having the frequency of 14.3 MHz output from the first-stage PLL circuit to the circuit 35.
Frequency divider 15 for frequency division, output signal of frequency divider 15 and frequency divider 1
A phase comparator 16 that outputs a phase difference signal using the feedback signal output from 8 as an input signal, and 1 that is synchronized with the output signal of the first-stage PLL circuit based on the output signal of the phase comparator 16.
VCO17 that oscillates a 3.5 MHz signal, VCO17
And a frequency divider 18 that divides a signal having a frequency of 13.5 MHz that oscillates by 33. A signal having a frequency of 13.5 MHz oscillated by the VCO 17 is output from the second stage PLL circuit as a reference clock signal.

In the above circuit, the first stage PLL circuit synchronizes with the subcarrier signal of the input image signal.
It produces a 3 MHz signal. The more accurate frequency of the sub-carrier used in the NTSC system is 3.579545 MHz.

In the second-stage PLL circuit, the 14.3 MHz signal generated by the first-stage PLL circuit is divided by 35 to obtain about 4 signals.
The signal of 09 KHz and the oscillation signal of 13.5 MHz are 33
Phase comparison is performed with the signal of about 409 KHz divided by
The signals oscillated by the second-stage and second-stage PLL circuits are synchronized. By synchronizing these two stages of PLL circuits, the 13.5 MHz output signal of the second stage becomes a signal synchronized with the subcarrier signal of the input image signal of the first stage.

According to the above procedure, the two-stage PLL circuit ensures stable 1 which is not affected by the jitter of the horizontal synchronizing signal.
It is possible to generate a 3.5 MHz reference clock signal.

As described above, according to the present invention, when the reference signal is generated, the burst signal which is not influenced by the noise is used as the reference signal, not the horizontal synchronizing signal which is affected by the noise included in the input image, and the reference signal is more stable. Generate a signal. Due to the circuit configuration of the two-stage PLL circuit, it is not necessary to unnecessarily increase the oscillation frequency of the VCO. With a simple circuit configuration, it is possible to generate a highly stable reference signal without causing jitter.

Although the above-described embodiment is a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention.

[0021]

As is apparent from the above description, in the reference signal generating circuit of the present invention, the first AC signal extracted from the subcarrier signal from the image signal and oscillated by the first-stage PLL circuit is the subcarrier signal. Since the second AC signal oscillated by the second-stage PLL circuit and the first AC signal are synchronized with each other, the second AC signal is sub-image signal of the image signal by the two-stage synchronization circuit. The signal is synchronized with the carrier signal. By approximating the frequencies of the first AC signal and the second AC signal and decreasing the frequency division ratio, the synchronous circuit can be configured with an AC oscillation frequency lower than the frequency of the output signal,
The circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of a reference signal generation circuit of the present invention, in which a portion A is a first stage PL and a portion B is a second stage PL.
FIG. 3 is a configuration block diagram of an L circuit.

FIG. 2 is a configuration block diagram of a conventional reference signal generation circuit.

[Explanation of symbols]

10 band pass filter (BPF) 11 sync signal detector 12 phase comparator 13 voltage control oscillator (VCO; 1)
4.3 MHz) 14 divider (dividing ratio 1/4) 15 divider (dividing ratio 1/35) 16 phase comparator 17 voltage control oscillator (VCO; 1
3.5MHz) 18 divider (dividing ratio 1/33)

Claims (3)

[Claims] 1. A reference signal generating circuit used in an apparatus for processing an NTSC image signal, comprising: a filter for extracting a subcarrier signal from the image signal; and a first oscillating means for oscillating a first AC signal. A first PLL circuit configured to include a first phase comparison unit that detects a phase difference between the subcarrier signal and the first AC signal; and a second PLL circuit that oscillates a second AC signal. And a second PLL circuit configured to include a second phase comparison unit that detects a phase difference between the second AC signal and the first AC signal. In the first PLL circuit, the first AC signal is synchronized with the subcarrier signal, and the second PLL signal is
In the circuit, the second AC signal is synchronized with the first AC signal to generate the second AC signal as an output signal in synchronization with the subcarrier signal. circuit. 2. In the reference signal generating circuit, the first PLL circuit further detects a synchronizing signal from the image signal and generates a position signal indicating a position of the subcarrier signal in the image signal, a synchronizing signal detecting means. And a first frequency dividing means for frequency-dividing the first AC signal and outputting a first frequency-divided signal, wherein the sub-carrier signal and the first AC current in the first phase comparing means are included. The phase difference with the signal is detected based on the position signal and the frequency-divided signal, and the second PLL circuit further frequency-divides the first AC signal and outputs a second frequency-divided signal. It has a 2nd frequency-dividing means and a 3rd frequency-dividing means which frequency-divides the said 2nd alternating current signal and outputs a 3rd frequency-dividing signal, Comprising: The said 1st in the said 2nd phase comparison means. The phase difference between the AC signal and the second AC signal is detected by the second component. The reference signal generation circuit according to claim 1, wherein the reference signal generation circuit is performed based on a frequency signal and the third frequency-divided signal. 3. The first AC signal is approximately 14.3 MHz.
And the second AC signal is approximately 13.5 MHz.
3. The reference signal generating circuit according to claim 1, wherein the reference signal generating circuit is a signal of