JPH0730438A - Viterbi decoding method - Google Patents

Abstract

PURPOSE:To sharply reduce operation volume to be required for branch metric calculation in respect to a viterbi decoding method for decoding a receiving sequence encoded by convolusion by means of the arithmetic processing of a processor. CONSTITUTION:In this Viterbi decoding method for decoding a receiving sequence encoded by convolution by means of a processor, a branch metric value corresponding to each state is tabulated and stored in a memory 1, and at the time of executing operation for selecting a remaining pass, the branch metric value is read out front the memory 1 and used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding method for decoding a convolutionally coded received sequence by arithmetic processing by a processor.

In satellite communication or mobile communication, since the transmission path is a wireless section, the error rate is much higher than that in wired transmission. Therefore, as a coding / decoding method, correction coding having excellent error correction capability is performed. / Decoding scheme is used. Among them, the Viterbi decoding method for performing maximum likelihood decoding on a convolutionally encoded reception sequence is often used because it has a particularly excellent error correction capability.

[0003]

2. Description of the Related Art FIG. 4 shows an example of a convolutional encoder that generates a binary convolutional code having a code rate of 1/2 and a generator matrix of G = [1 + D ² , 1 + D + D ² ]. A Viterbi decoding method using this binary convolutional code is shown in FIG.

FIG. 5 shows the state S _ab (a, bε) of the delay element D.
The trellis which represents the transition of 0, 1) with respect to a time axis is shown. The transitions between the states are indicated by the solid and dashed branches corresponding to the information bits 0 and 1 at time t _k , respectively. The 2-bit numerical value attached to each branch represents the output of the convolutional encoder at that time, and the value in parentheses represents the path metric value.

Now, the input information sequence on the transmission side is "1101".
0010 ”, the code sequence of the convolutional encoder output is“ 11 10 00 00 from the above-mentioned generator matrix.
01 11 11 01 ″.

Here, on the transmission path, an error sequence "00 01 00 100 0 due to noise is added to this output code sequence.
Since "1 00 00 10" is added, the receiving side receives "11 11 00 10 00 11" as a reception sequence.
It is assumed that the pattern 11 11 "has been received.

In each state S _ab in FIG. 5, the state S ₀₀ is “00” for the information sequence contained in the delay element D of the convolutional encoder on the transmission side, the state S ₁₀ is “10”, and the state S ₀₁ is the state S _01. "0
1 ”and state S ₁₁ are“ 11 ”, respectively.

The trellis transition diagram will be described. At first (time t ₀ ), the state starts from state S ₀₀ , and if the information sequence input to the convolutional encoder is “0”, the convolutional encoder outputs. transition to generate a code sequence "00" to the state S ₀₀ (branch line), whereas, a transition to a state S ₀₁ generates a "1" into "11" (branch dashed line).

Next, at time t ₁ , if the information sequence is "0" in state S ₀₀ , the convolutional encoder generates "00", transits to state S ₀₀ , and is "1". a transition to a state S ₁₀ generates a bus "11". In state S ₁₀ , if the information sequence is “0”, the convolutional encoder generates “01” and transits to state S ₀₁ , and if “1”, generates “10” and transits to state S ₁₁ . To do. Hereinafter, the same operation is repeated.

Here, the Hamming distance (branch metric) between the reception sequence and each branch at each time t _k is calculated, and the branch metric of the path formed by connecting the branch trains along the trellis is added to obtain the path. Obtain the metric, each state S at each time
_By selecting the surviving path with the smallest path metric at that time among the multiple paths entering _ab , and outputting the input information sequence corresponding to the last surviving path (that is, the path with the smallest path metric). , Estimate the input information sequence most likely to be transmitted on the transmission side, and eliminate errors in the transmission path.

The processing of the conventional Viterbi decoding method for performing the above operation will be described below. In the above binary convolutional code, as shown in FIG. 6, four states S ₀₀ ,
S _10, S _01, information bits "0" for S _11, when "1" is inputted, from the convolutional encoder Each output code shown is output. These values are stored in the table ROM. If you represent the convolutional encoder state memory in trel, as shown in FIG. 7, trel (0), in the case of input information bit "0" to state S ₀₀ in trel (1) The output of the convolutional encoder is stored, and the output of the convolutional encoder when the information bit “0” is input to the state S ₁₀ is stored in trel (2) and trel (3). (6), trel (7) stores the output of the convolutional encoder when the information bit “0” is input for the state S ₁₁ . Similarly trel (8) ~trel (15) in each state _{S 00, S 10, S 01} , S 11 to the information bits "1"
Stores the output of the convolutional encoder when is input.

Namely, as the output of convolutional encoder when the input information bit "0", trel (0) = 0 trel (1) = 0 state convolutional encoder output trel (2) with respect to S ₀₀ = 0 trel (3) = 1 Convolutional encoder output for state S ₁₀ trel (4) = 1 trel (5) = 1 Convolutional encoder output for state S ₀₁ trel (6) = 1 trel (7) = 0 State S ₀₀ Convolutional encoder output for

[0013] As the output of the convolutional encoder at the time of input information bits "1", trel (8) = 1 trel (9) = 1 state convolutional encoder output trel (10) with respect to S ₀₀ = 1 trel (11 ) = 0 Convolutional encoder output for state S ₁₀ trel (12) = 0 trel (13) = 0 Convolutional encoder output for state S ₀₁ trel (14) = 0 trel (15) = 1 Convolutional encoder for state S ₀₀ It becomes the output of the encoder.

If the reception sequence memory for storing the reception sequence is represented by inp, in the case of the example of FIG.
(0) ・ ・ ・ inp (7) ・ ・ ・ contains the reception sequence “11 11 0
"0 10 00 11 11 11 11 ..." is stored. In addition, a metric value memory metric that stores the metric value of each state, a work memory work used for work when calculating a branch metric, and survivor path information. A path memory pathmem for storing is prepared.

FIG. 8 shows an example of a processor-type Viterbi decoding circuit. As shown in the figure, the rewritable RAM and the ROM for storing a fixed value are the data bus # 1 and
The register A and the register B, which are connected to the # 2 and are provided as the operation input registers to the logical operation circuit ALU, and the operation result output registers, are provided as the register C and the register D, respectively. D is also connected to the data buses # 1 and # 2.

FIG. 9 shows a processing procedure of the conventional Viterbi decoding method. In the binary convolutional code, two reception series data are associated with each state S _ab , and the path metric for each state is calculated.

First, the branch metric of the reception sequence inp (i), inp (i + 1) and each trellis branch trel (j), trel (j + 1) is calculated in steps S1 to S12. That is, the reception sequence inp
Inp (i) of (i), inp (i + 1) is stored in register A and tre
l (j) (starting from j = 1 here) is loaded into register B (step S1), and the exclusive OR of the contents of register A and register B is calculated and stored in register C (step S1). S2). Then, the reception sequence inp (i), inp
Inp (i + 1) of (i + 1) is stored in register A, and trel (j +
1) is loaded into the register B (step S3), the exclusive OR of the contents of the registers A and B is calculated and stored in the register D (step S4). Then, seeking input information bit "0" corresponding branch of the branch metrics entering a state S ₀₀ by adding the contents of register C and register D, and stores it in memory work1.

Similarly, the reception sequence inp (i) is stored in the register A.
, Trel (j + 8) is loaded into register B (step S6), the exclusive OR of the contents of register A and register B is calculated and stored in register C (step S7), and then the reception sequence inp (i + 1) to register A and trel (j + 9)
Is loaded into register B (step S8), and register A
And the exclusive OR of the contents of the register B are stored in the register D (step S9). Then, seeking branch of the branch metric corresponding to the input information bits "1" to enter the state S ₀₀ by adding the contents of register C and register D, and stores it in memory work2.

Next, ACS (addition / comparison / selection) processing is performed based on the branch metric obtained as described above.
(Step S11). That is, the obtained branch metric is read from each of the memories work1 and work2, and added to the path metric value metric one time before the path of the branch to calculate the path metric value at the present time. By comparison, the smaller value is selected as the surviving path.

The processing of steps 1 to S11 (branch metric calculation processing) is repeated until j becomes 7 by sequentially adding 2 to j and updating (step S12).
As a result, the branch metric is sequentially calculated for the other states S ₁₀ , S ₀₁ , and S ₁₁ , and the path metric value is calculated based on the branch metric to determine the surviving path.

When the processing of steps 1 to S11 is completed,
Based on the result, the path metric of each branch for the received sequence inp (i), inp (i + 1), that is, the contents of the path metric value memories metric (0) to metric (7) are updated (step S13). In addition, the survivor path information is stored in the path memory
Write to m (step S14).

Next, the value of i is updated by adding 2 to i (step S15), and the above steps S1 to S14 are performed.
By repeating the above, the path metric is calculated and the surviving path is determined for the next reception sequence. This process is sequentially performed by updating i.

[0023]

As can be seen from the flowchart shown in FIG. 9, the branch metric value calculation process (steps S1 to S12) is incorporated in a double loop, and therefore i, j It needs to be repeated many times while updating. Therefore, when this is performed by the processor, a huge amount of calculation is required, and this amount of calculation increases as the number of states of the convolutional encoder and the number of received data increase. As a result, the burden on the processor is increased and the arithmetic processing takes a long time. Therefore, in order to obtain a decoded output in real time with respect to sequentially received data, it is necessary to reduce this calculation amount as much as possible.

The present invention has been made in view of such problems, and an object thereof is to significantly reduce the amount of calculation required for branch metric calculation.

[0025]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, 1 is a memory, and 2 is a portion including a processor that performs a Viterbi decoding process. The Viterbi decoding method of the present invention is a Viterbi decoding method in which a convolutionally encoded reception sequence is decoded by a processor, and a branch metric value corresponding to each state is tabulated and stored in the memory 1 to survive. The branch metric value is read from the memory 1 and used in the calculation for path selection.

The Viterbi decoding method described above decodes the punctured convolutionally encoded reception sequence by tabulating the branch metric values for the punctured convolutionally encoded reception sequence and storing them in the memory 1. You can

[0027]

By replacing the calculation of the branch metric value, which required the calculation amount in the conventional Viterbi decoding method, with the table lookup process by the memory 1 storing the branch metric value, the calculation amount can be greatly reduced. .

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a processing procedure of the Viterbi decoding method as one embodiment of the present invention, and FIG. 3 shows various memories used in the embodiment method. The hardware used in this embodiment is the same processor type decoding circuit as that shown in FIG. As a memory, the conventional convolutional encoder state memory tr
A branch metric value memory path is newly prepared instead of el. A memory k is prepared as a work memory.

In each state S _ab , the received sequence is inp
The combination of (i) and inp (i + 1) is "00", "10", "01"
Therefore, the branch metric value for each of the input information bits "0" and "1" in each state is tabulated in advance and stored in the branch metric value memory path.

That is, in state S ₀₀ , inp (i), inp (i
The branch metric “0” for the combination “+1” is “00”.
The branch metric value "1" for "01" is added to path (0).
The branch metric value “1” for “10” is added to path (1).
The branch metric value “2” for “11” is set to path (2) pa
Store as table value in th (3). Similarly, each state S ₁₀ , S when the input information bit is “0”
The branch metric values in ₀₁ and S ₁₁ are sequentially arranged, and thereafter, the states S ₀₀ and S when the input information bit is “1”
The branch metric values at ₁₀ , S ₀₁ , and S ₁₁ are sequentially arranged. That is,

Inp (i), inp (i + 1) input information bit state branch metric value memory 00 0 S ₀₀ path (0) = 0 01 0 S ₀₀ path (1) = 1 10 0 S ₀₀ path (2) = 1 11 0 S ₀₀ path (3) = 2 00 0 S ₁₀ path (4) = 1 01 0 S ₁₀ path (5) = 0 10 0 S ₁₀ path (6) = 2 11 0 S ₁₀ path (7) = 1 00 0 S ₀₁ path (8) = 2 01 0 S ₀₁ path (9) = 1 10 0 S ₀₁ path (10) = 1 11 0 S ₀₁ path (11) = 0 00 0 S ₁₁ path (12) = 1 01 0 S ₁₁ path (13) = 2 10 0 S ₁₁ path (14) = 0 0 11 0 S ₁₁ path (15) = 1 100 1 S ₀₀ path (16) = 2 01 1 S ₀₀ path (17) = 1 10 1 S ₀₀ path (18) = 1 1 11 1 S ₀₀ path (19) = 0 0 00 1 S ₁₀ path (20) = 1 01 1 S ₁₀ path (21) = 2 10 1 S ₁₀ path (22) = 0 11 1 S ₁₀ path (23) = 1 00 1 S ₀₁ path (24) = 0 0 1 1 S ₀₁ path (25) = 1 1 10 1 S ₀₁ path (26) = 1 1 1 1 S ₀₁ path (27) = 200 1 S ₁₁ path (28) = 1 01 1 S ₁₁ path (29) = 0 10 1 S ₁₁ path (30) = 2 11 1 S ₁₁ path (31) = 1

A Viterbi decoding method according to the present invention using this branch metric value memory will be described below with reference to the flowchart of FIG.

In the method of this embodiment, the address of the branch metric value memory for the reception sequence data is calculated before selecting the optimum path (steps S21 to S2).
3). Although this calculation is newly added, since it is performed outside the double loop, the calculation amount in the entire Viterbi decoding can be reduced by further reducing the calculation (steps S24 to S27) inside the double loop. Is greatly reduced. In the present invention, the processing in the double loop is as follows when the input information bit is "0".
Since the processing is performed only by reading the branch metric value when the input information bit is "1" from the memory, the amount of calculation is greatly reduced.

First, as a process of calculating the address of the branch metric value memory path, inp (i) is loaded into register A and inp (i + 1) is loaded into register B (step S2).
1) The contents of the registers B and A are added and the result is stored in the register C (step S22), the contents of the register C are further transferred to the work memory k, and this k is stored in the branch metric value memory path. Is the address for reading.

That is, using the above k, the branch metric value is read from the branch metric value memory path (j + k) and stored in the work memory work1 (step S2).
4). This branch metric value is a value when the input information bit is "0".

Next, the branch metric value memory path (j + k + 16)
Read the branch metric value from the
Store in work2 (step S25). This branch metric value is a value when the input information bit is "1".

Using the contents of the work memories work1 and work2, ACS (addition / comparison / selection) processing similar to the conventional one is performed to calculate a path metric value and select a surviving path (step S29). After that, 4 is added to j to update (step S27), and steps S24 to S26 are performed.
The process of is repeated. This allows the same reception sequence inp (i), i
For np (i + 1), the branch metric values of the states S ₀₀ , S ₁₀ , S ₀₁ , S ₁₁ are sequentially read and processed.

After that, the metric value memory is updated and the survivor path is written in the same manner as in the conventional method (steps S28 and S29), and the update is performed by adding 2 to i (step S30), and the next reception sequence is performed. The same process is performed for.

Various modifications are possible in carrying out the present invention. For example, the present invention can be applied to a branch metric value memory even for a punctured convolutionally coded reception sequence.
It is possible to respond only by rewriting the value of path. This punctured convolutional coding is disclosed in, for example, Japanese Patent Laid-Open No. 57-1558.
As disclosed in Japanese Patent Laid-Open No. 57-57, it is a system in which a coding rate is increased by erasing a part of code bits in order to improve frequency utilization efficiency.

If the two polynomials have the same degree (as used in the example of the present invention), a table having half the number of states may be prepared, as can be seen from FIG.

[0041]

As described above, according to the present invention, the amount of calculation required for branch metric calculation can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a flowchart showing a Viterbi decoding method as an embodiment of the present invention.

FIG. 3 is a diagram showing various memories used in an embodiment method.

FIG. 4 is a diagram illustrating an example of a convolutional encoder.

FIG. 5 is a transition diagram based on a trellis representation.

FIG. 6 is a diagram showing a state of a convolutional encoder.

FIG. 7 is a diagram showing various memories used in a conventional method.

FIG. 8 shows a processor-type decoder.

FIG. 9 is a flowchart showing a conventional Viterbi decoding method.

[Explanation of symbols]

 # 1, # 2 Data bus RAM Random access memory ROM Read-only memory A, B, C, D register ALU Logical operation circuit inp Received sequence memory path Branch metric value memory metric metric value memory pathem Path memory work memory trel convolution Memory for encoder state

Claims (2)

[Claims] 1. A Viterbi decoding method for decoding a convolutionally encoded received sequence by a processor, wherein a branch metric value corresponding to each state is tabulated and stored in a memory (1).
The Viterbi decoding method in which the branch metric value is read from the memory and used in the calculation for selecting the surviving path. 2. The punctured convolutionally encoded reception sequence is decoded by tabulating the branch metric values for the punctured convolutionally encoded reception sequence and storing them in the memory. Viterbi decoding method described.