JPH07336239A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of the Viterbi decoder by reducing the storage capacity of a memory. CONSTITUTION:A single system RAM is used as a path memory or a pathmetric memory. Two systems of ACS processing functions are provided. When the ACS processing is executed in time division, the 1st ACS processing system stores a pathmetric at a current point of time to an address m0 among addresses m0 and m4 having stored a pathmetric or the like at the preceding point of time and the 2nd ACS processing system stores it to the m4. The processing above is conducted for all addresses for the number of times of (restricted length -1) to terminate the ACS processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder for decoding a reception sequence according to a Viterbi algorithm, and more particularly to a path metric memory or a method of accessing the path memory.

[0002]

Viterbi decoding is known as a maximum likelihood decoding method for a convolutional code. That is, in Viterbi decoding, when a convolutional code is transmitted and received via a communication channel, the value of the likelihood function is maximized with respect to the received code (reception sequence) according to a predetermined Viterbi algorithm. Is a decoding method for determining that a code sequence has been transmitted and outputting this code sequence as a decoded sequence. Viterbi decoding is
This is effective in terms of error correction when performing communication using a poor quality communication path or when high-quality data transmission is required, for example, when transmitting digital data.

Each term of the likelihood function (or an amount proportional thereto)
Is called a branch metric, and the likelihood of the code sequence corresponding to each path on the trellis diagram is evaluated by the sum of the branch metrics. That is, the likelihood of the code sequence corresponding to a certain path can be evaluated by the sum of the branch metrics calculated for each code (each branch on the trellis diagram) forming this code sequence, in other words, the path metric. Maximum-likelihood decoding is to find a path with the smallest path metric. Viterbi decoding is a procedure of selecting a path (survival path) that minimizes the path metric before that when a certain time point is considered.

Viterbi decoding is executed in the following procedure. That is, in the case of Viterbi decoding, first, the branch metric is calculated for all the branches from the state S _i at the previous time point to the state S _j at the current time point. Further, each of the calculated branch metrics is added to the path metric of the surviving path up to the previous time point, that is, the surviving path at the previous time point (add). Furthermore, the result of the addition is the current state S
_For each _j , compare all branches from S _i to S _j (co
mpare). Then, select the branch that gives the minimum value (selec
t), the surviving path at the current time is connected to the surviving path at the previous time. The latest survivor path is output as the maximum likelihood code that is the decoding result.

Of the series of procedures, add, compare and select are collectively referred to as ACS (add-compare-select) processing. In order to execute the ACS processing, a means for storing the path metric (path metric memory) and a means for storing the selected path (path memory) are required. Further, the ACS processing can be executed for each of the current states S _j , that is, in a time-sharing manner.

FIG. 3 shows a conventional read / write mode for a path metric memory. The example in this figure is an example in which the code rate R = 1/2, the constraint length K = 4, and the number of states = 8. The path metric memory in this figure is composed of two RAMs (RAM1 and RAM2). The RAM 1 is composed of addresses for the number of states, that is, mR0 to mR7, and the RAM 2 is also composed of addresses mW0 to mW7 for the number of states. In the example of this figure, the path metric of the surviving path at the previous time is stored in each address mR0 to mR7 of the RAM1. Further, the RAM 2 stores the path metric of the surviving path at the present time obtained by the ACS processing.

When executing Viterbi decoding for the example of this figure, first, the branch metrics are calculated for all the branches from the states 000 to 111 at the previous time point to the states 000 to 111 at the current time point. When the branch metric is calculated, ACS processing is subsequently executed. In that case, RA
The branch metric obtained by the calculation is added to the path metric of the surviving path at the previous time point stored in each address mR0 to mR7 on M1, and the minimum value as a result of the comparison of the added values is the present value. Is stored in the corresponding address of the addresses mW0 to mW7 of the RAM 2 as the path metric of the surviving path of

For example, when focusing on the current state 000, the branch metric from the previous state 000 to the current state 000 is added to the path metric stored in the address mR0 of the RAM 1, while The branch metric from the state 100 at the previous time point to the state 000 at the current time point is added to the path metric stored in the address mR4 of the RAM 1. As a result of these additions, the path having a smaller value is regarded as the surviving path at the present time. The added value which is the surviving path at the present time is stored in the address mW0 of the RAM 2 as the path metric of the path.

When the ACS processing is executed in a time-sharing manner,
With regard to the path metric memory, such processing is executed for each state at the present time. In the example of FIG. 3, the following 8
Steps are performed.

First step: Add the branch metric from 000 to 000 to the path metric on mR0. 10
Add the branch metric from 0 to 000 to the path metric on mR4. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW0.

Second step: Add the branch metric from 000 to 001 to the path metric on mR0. 10
Add the branch metric from 0 to 001 to the path metric on mR4. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW1.

Third step: Add the branch metric from 001 to 010 to the path metric on mR1. 10
Add the branch metric from 1 to 010 to the path metric on mR5. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW2.

Fourth step: Add the branch metric from 001 to 011 to the path metric on mR1. 10
Add the branch metric from 1 to 011 to the path metric on mR5. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW3.

Fifth step: Add the branch metric from 010 to 100 to the path metric on mR2. 11
Add the branch metric from 0 to 100 to the path metric on mR6. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW4.

Sixth step: Add the branch metric from 010 to 101 to the path metric on mR2. 11
Add the branch metric from 0 to 101 to the path metric on mR6. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW5.

Seventh step: Add the branch metric from 011 to 110 to the path metric on mR3. 11
Add the branch metric from 1 to 110 to the path metric on mR7. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW6.

Eighth step: Add the branch metric from 011 to 111 to the path metric on mR3. 11
Add the branch metric from 1 to 111 to the path metric on mR7. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in mW7.

The path memory is also a memory having the same structure as the path metric memory of FIG. 3, and the operation of its contents is also the same as that of the path metric memory. However, the path memory stores not the path metric but the information for specifying the selected path.

[0019]

By executing such ACS processing, error correction by Viterbi decoding can be realized. However, in order to execute this processing in a time-sharing manner, it is necessary to provide two systems of path metric memory and path memory. That is, since the path metric memory or the information such as the path metric is read from the path memory and the ACS processing is performed using the information, the information such as the path metric obtained as a result of the ACS processing is written in the path metric memory or the path memory. Therefore, in order not to destroy the path metric etc. required in the later step in the previous step, the path metric etc. obtained as a result of the execution of each step of the ACS processing is read out (RAM 1 in FIG. 3). It is necessary to write in a different memory (same RAM2).

The present invention has been made to solve the above problems, and improves a path metric memory and an address structure of the path memory and an access method to these to improve the path metric memory and the path. The purpose of the present invention is to reduce the circuit scale of the Viterbi decoder by eliminating the need to provide a plurality of memories.

[0021]

In order to achieve such an object, the present invention provides a means for calculating a branch metric for an input code sequence, a memory for storing survivor path information, and a calculated branch. In a Viterbi decoder comprising: ACS processing means for newly generating survivor path information based on the metric and survivor path information on the memory and writing the survivor path information on the memory; and means for outputting the latest survivor path information as information regarding a decoding sequence, The ACS processing means stores the newly generated survivor path information in a portion of the memory that stores the survivor path information used when newly generating the survivor path information.

Further, according to the present invention, the memory is a path memory for storing information for specifying a surviving path as the surviving path information and / or a path metric memory for storing a path metric of the surviving path as the surviving path information. Characterize.

[0023]

In the present invention, the branch metric is first calculated for the input code sequence. Further, new survivor path information is generated based on the calculated branch metric and survivor path information on the memory, and written on the memory. The latest survivor path information is output as information regarding the composite series. Here, in the present invention,
The ACS processing means newly generated survivor path information,
That is, the surviving path information at the present time is stored in the memory portion that has stored the surviving path information used when the surviving path information at the present time is generated, that is, the surviving path information at the previous time. Therefore, since the new survivor path information is stored in the memory portion that is no longer needed due to the generation of the new survivor path information, two systems, that is, the read source portion and the write destination portion are used as the memory. Since it is not necessary to provide the memory, the capacity of the memory is reduced.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a Viterbi decoder according to an embodiment of the present invention, and FIG. 2 shows a path metric memory and a method of accessing the path memory in this embodiment. In these figures, the coding rate R = 1/2 and the constraint length K = 4 for comparison with FIG. 3 according to the conventional example, but the present invention is not limited to these specifications.

The Viterbi decoder shown in FIG. 1 comprises a branch metric calculation circuit 1, an ACS processing unit 2, a path memory RAM.
3, a path metric RAM 4 and an address generation circuit 5. The branch metric calculation circuit 1 calculates a branch metric based on an input reception sequence (“data input” in the figure). The ACS processing unit 2 executes the ACS processing based on the branch metric calculated by the branch metric calculation circuit 1 and the path metric on the path metric RAM 4, and updates the contents of the path memory RAM 3 and the path metric RAM 4 based on the result. Path memory RAM
Reference numeral 3 stores the path selected by the ACS processing unit, that is, information on the surviving path at the present time, and the path metric RAM 4 stores the path metric of the surviving path at the present time. The path memory RAM3 outputs the latest survivor path as a decoded maximum likelihood series ("data output" in the figure). The address generation circuit 5 has a configuration according to the features of this embodiment, and it is possible to use a RAM of one system configuration as the path memory RAM 3 and the path metric RAM 4.

As shown in FIG. 2, in this embodiment, as the path memory RAM 3 and the path metric RAM 4, a single system RAM composed of addresses m0 to m7 is used. That is, in the conventional example of FIG.
While two RAMs (RAM1 and RAM2) having addresses are used, RA of 8 addresses is used in this embodiment.
It is only necessary to use one M.

When executing Viterbi decoding in this embodiment, first, the branch metric calculation circuit 1 determines branch metrics for all branches from the states 000 to 111 at the previous time to the states 000 to 111 at the present time. Calculated.
When the branch metric is calculated, the ACS processing unit 2 subsequently executes the ACS processing. At that time, the ACS processing unit 2 reads the path metric of the surviving path at the previous time point stored in the addresses m0 to m7, and adds the branch metric obtained by the calculation to this. The ACS processing unit 2 compares the added values and sets the minimum value as a result to the address storing the path metric of each surviving path to be compared as the path metric of the surviving path at the present time. Write. For this reason, the ACS processing unit 2 has two ACS processing systems (not shown), and the address generation circuit 5 performs such read / write operations.
The address is controlled so that writing is performed. The ACS processing unit 2 and the address generation circuit 5 execute the same procedure for the path memory RAM 3. These procedures are repeated for the constraint length-1 times, 4-1 = 3 times in the figure.

This procedure will be described more specifically according to the example of FIG. That is, when the ACS processing is executed in time division, the following 12 steps are executed in time division regarding the path metric RAM 4. The same applies to the path memory RAM3.

First step: The first processing system of the ACS processing unit 2 sets a branch metric from 000 to 000 to m.
Add to the path metric on 0, again 100 to 000
To the path metric on m4. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m0 (the leftmost m in the figure).
Transition from 0 and m4 to m0 to its right 1). The second processing system sets the branch metric from 000 to 001 to m0.
It is added to the upper path metric, and the branch metric from 100 to 001 is added to the path metric on m4. The path having the smaller added value is the surviving path at the present time, and the added value is stored in m4 (the leftmost m in the figure).
Transition from 0 and m4 to its right m4 1).

Second step: The first processing system of the ACS processing unit 2 sets the branch metric from 001 to 010 to m.
Add to the path metric on 1, and also 101 to 010
To the path metric on m5. The path having the smaller added value is the surviving path at the present time, and the added value is stored in m1 (the leftmost m in the figure).
Transition from 1 and m5 to its right m1 2). The second processing system sets the branch metric from 001 to 011 to m1.
The path metric above is added, and the branch metric from 101 to 011 is added to the path metric above m5. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m5 (m on the left side of the figure).
Transition from 1 and m5 to the right m5 2).

Third step: The first processing system of the ACS processing unit 2 sets the branch metric from 010 to 100 to m.
Add to the path metric on 2 and also 110 to 100
The branch metric leading to is added to the path metric on m6. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m2 (the leftmost m in the figure).
Transition from 2 and m6 to the right m2 3). The second processing system sets the branch metric from 010 to 011 to m2.
The path metric above is added, and the branch metric from 101 to 011 is added to the path metric above m6. The path having the smaller added value is the surviving path at the present time, and the added value is stored in m6 (m on the leftmost side in the figure).
Transition from 2 and m6 to the right m6 3).

Fourth step: The first processing system of the ACS processing unit 2 sets the branch metric from 011 to 100 to m.
Add to the path metric on 3 and also 111 to 110
To the path metric on m7. The path having the smaller added value is the surviving path at the present time, and the added value is stored in m3 (the leftmost m in the figure).
3) and transition from m7 to m3 to the right of it 4). The second processing system sets the branch metric from 011 to 111 to m3.
The path metric above is added, and the branch metric from 111 to 111 is added to the path metric above m7. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m7 (the leftmost m in the figure).
3 and m7 to the right m7 4).

Fifth step: The first processing system of the ACS processing unit 2 sets the branch metric from 000 to 000 to m.
Add to the path metric on 0, again 100 to 000
To the path metric on m2. The path having the smaller added value is the surviving path at the present time, and the added value is stored in m0 (2 from the left in the figure).
Transition from the second m0 and m2 to the right m0 1).
The second processing system adds the branch metric from 000 to 001 to the path metric on m0, and adds the branch metric from 100 to 001 to the path metric on m2. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m2 (transition 1 from the second m0 and m2 from the left in the figure to m2 on the right).

Sixth step: The first processing system of the ACS processing unit 2 sets the branch metric from 001 to 010 to m.
Add to the path metric on 4 and again 101 to 010
The branch metric leading to is added to the path metric on m6. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m4 (2 from the left in the figure).
Transition 2) from the fourth m4 and m6 to the right m4).
The second processing system adds the branch metric from 001 to 011 to the path metric on m4, and also adds the branch metric from 101 to 011 to the path metric on m6. The path having the smaller added value is set as the surviving path at the present time and the added value is stored in m6 (transition 2 from the second m4 and m6 from the left in the figure to m6 on the right).

Seventh step: The first processing system of the ACS processing unit 2 sets the branch metric from 010 to 100 to m.
Add to the path metric on 1 and also 110 to 100
The branch metric leading to is added to the path metric on m3. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m1 (2 from the left in the figure).
Transition 3) from the first m1 and m3 to the right m1).
The second processing system adds the branch metric from 010 to 101 to the path metric on m1, and also adds the branch metric from 110 to 101 to the path metric on m3. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m3 (transition 3 from the second m1 and m3 from the left in the figure to m3 on the right).

Eighth step: The first processing system of the ACS processing unit 2 sets the branch metric from 011 to 110 to m.
Add to the path metric on 5, and also 111 to 110
To the path metric on m7. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m5 (2 from the left in the figure).
Transition from the fifth m5 and m7 to the right m5 4). The second processing system adds the branch metric from 011 to 111 to the path metric on m5, and also 111 to 1
The branch metric up to 11 is added to the path metric on m7. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m7 (the second transition m5 from the left in the figure to m7 and the transition 4 from the right m7).

Ninth step: The first processing system of the ACS processing unit 2 sets the branch metric from 000 to 000 to m.
Add to the path metric on 0, again 100 to 000
To the path metric on m1. The path with the smaller added value is the surviving path at the present time, and the added value is stored in m0 (3 from the left in the figure).
Transition 1) from the second m0 and m1 to the right m0). The second processing system adds the branch metric from 000 to 001 to the path metric on m0, and also from 100 to 0.
The branch metric up to 01 is added to the path metric on m1. The path having the smaller added value is set as the surviving path at the present time and the added value is stored in m1 (transition 1 from the third m0 and m1 from the left in the figure to m1 on the right).

Tenth step: First of ACS processing section 2
The processing system of adds the branch metric from 001 to 010 to the path metric on m2, and 101 to 01
The branch metric leading to 0 is added to the path metric on m3. The path having the smaller addition value is set as the surviving path at the present time, and the addition value is stored in m2 (transition 2 from the third m2 and m3 from the left in the figure to m2 on the right).
The second processing system adds the branch metric from 001 to 011 to the path metric on m2, and adds the branch metric from 101 to 011 to the path metric on m3. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m3 (the third m2 from the left in the figure and the transition 2 from m2 to m3 on the right).

Eleventh step: First of ACS processing section 2
The processing system of adds the branch metric from 010 to 100 to the path metric on m4, and also 110 to 10
The branch metric reaching 0 is added to the path metric on m5. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m4 (transition 3 from the third m4 and m5 from the left in the figure to m4 on the right).
The second processing system adds the branch metric from 010 to 101 to the path metric on m4, and also adds the branch metric from 110 to 101 to the path metric on m5. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m5 (transition 3 from the third m4 and m5 from the left in the figure to m5 on the right).

Twelfth step: First of ACS processing section 2
The processing system of adds the branch metric from 011 to 110 to the path metric on m6, and 111 to 11
The branch metric reaching 0 is added to the path metric on m7. The path having the smaller added value is set as the surviving path at the present time, and the added value is stored in m6 (transition 4 from the third m6 and m7 from the left in the figure to m6 on the right).
The second processing system adds the branch metric from 011 to 111 to the path metric on m6, and adds the branch metric from 111 to 111 to the path metric on m7. The path having the smaller added value is set as the surviving path at the present time and the added value is stored in m7 (transition 4 from the third m6 and m7 from the left in the figure to m7 on the right).

As described above, in this embodiment, the ACS
The processing unit 2 is provided with two ACS processing functions, and two ACS processings are performed in parallel at each step of time-division execution. Further, the result of the comparison in each system is stored in the address that stores the path metric of the surviving path related to each comparison target. Therefore, it is possible to prevent the information, which has not been subjected to the ACS processing at the present time, among the information on the surviving paths at the previous time point from being destroyed by writing the ACS processing result. That is, it is not necessary to provide the RAM configuring the path metric RAM 4 in two systems, that is, a read source portion and a write destination portion. For example, in the conventional example of FIG. 3, a capacity of 8 addresses × 2 systems = 16 addresses is required, but in the embodiment of FIG. 2, a capacity of 8 addresses × 1 system = 8 addresses is sufficient. As a result, the memory, which conventionally occupies more than half the circuit scale, can be made smaller.

[0043]

As described above, according to the present invention,
Since the surviving path information at the current time is stored in the part of the memory where the surviving path information at the previous time is stored, the surviving path information at the previous time is read as the memory and the surviving path information at the current time. It is not necessary to provide the two systems of writing destinations, and the storage capacity of the memory can be reduced and the circuit scale of the Viterbi decoder can be reduced. Furthermore, the present invention can be applied to both path memory and path metric memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a Viterbi decoder according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an access mode to a path memory and a path metric memory in this embodiment.

FIG. 3 is a conceptual diagram showing a manner of accessing a path memory and a path metric memory in a conventional example.

[Explanation of symbols]

 1 Branch metric calculation circuit 2 ACS processing unit 3 Path memory RAM 4 Path metric RAM 5 Address generation circuit m0 to m7 addresses

Claims (3)

[Claims] 1. A means for calculating a branch metric for an input code sequence, a memory for storing survivor path information, and a new survivor path information generated based on the calculated branch metric and survivor path information on the memory. In a Viterbi decoder including an ACS processing unit that writes on a memory and a unit that outputs the latest survivor path information as information regarding a decoding sequence, when the ACS processing unit newly generates survivor path information in the memory. A Viterbi decoder characterized in that the newly generated survivor path information is stored in the portion that has stored the used survivor path information. 2. The Viterbi decoder according to claim 1, wherein the memory is a path memory that stores information for identifying a survivor path as survivor path information. 3. The Viterbi decoder according to claim 1, wherein the memory is a path metric memory that stores a path metric of a survivor path as survivor path information.