KR100680024B1 - Viterbi decoder having delay time abbreviation path and control method thereof - Google Patents

Abstract

The present invention relates to a Viterbi decoder having a shorter delay time path and a control method thereof, and in particular, a branch metric calculation unit 120 that receives an input signal output from the input buffer 110 and calculates a branch metric value; An ACS calculator 130 for updating the state metric through the branch metric value of the branch metric calculator 120 and outputting survival path information, and outputting a minimum state number according to an external first path selection signal; And a backtracking operation unit 140 for storing the survival path information according to the external second path selection signal as the backtracking depth and outputting the final decoded signal to the output buffer 150 by backtracking from the minimum state number. The present invention reduces the demodulation delay of the modem reception signal by executing a short path, thereby enabling faster operation when a response is required during the interframe interval time, thereby enabling an excellent frame retransmission. .

Viterbi decoder, ACS operation, traceback operation,

Description

Viterbi decoder with shorter delay time path and control method {VITERBI DECODER HAVING DELAY TIME ABBREVIATION PATH AND CONTROL METHOD THEREOF}             

1 is a functional block diagram showing the configuration of a conventional Viterbi decoder;

2 is a functional block diagram showing the configuration of a Viterbi decoder having a shortened delay time path according to an embodiment of the present invention;

3 is a functional block diagram illustrating a configuration of an ACS calculation unit in a Viterbi decoder having a delay time shortening path according to FIG. 2;

4 is a functional block diagram illustrating a configuration of a traceback calculation unit in a Viterbi decoder having a delay time shortening path according to FIG. 2;

5 is a view showing a convergence characteristic of a backtracking process in a Viterbi decoder having a shortened delay path according to FIG. 2;

6 is an operation flowchart illustrating an operation process of an ACS operation unit in a control method of a Viterbi decoder having a shortened delay time path according to an embodiment of the present invention;

FIG. 7 is an operation flowchart illustrating an operation process of the traceback computing unit in a control method of a Viterbi decoder having a shortened delay time path according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: input buffer 120: branch metric calculation unit

130: ACS operation unit 131: ACS unit

132: minimum metric calculation unit 133: mux

140: backtracking operation unit 141: memory unit

142: memory address control unit 150: output buffer

The present invention relates to a Viterbi decoder having a delay time shortening path and a control method thereof, and more particularly, to a case in which a signal is decoded using a Viterbi decoder, a shortened path is inserted therein, thereby reducing the delay of the signal. The present invention relates to a Viterbi decoder having a shorter delay time path that can minimize power consumption and reduce power consumption by not operating a block that is not in use.

As is well known, for the case of using a convolutional encoder as an error correction code, the receiver usually finds the transmitted signal using a Viterbi decoder.

The conventional Viterbi decoder developed in the prior art, as shown in Figure 1, the input buffer 11, branch metric operation unit 12, Add-Compare-Select (ACS) operation unit 13, the traceback operation unit 14 and the output It consisted of the buffer 15. At this time, the input buffer 11 outputs a soft-determined signal to the branch metric calculator 12 according to the operation of the Viterbi decoder, and the branch metric calculator 12 inputs the soft signal. The branch metric of the signal is calculated and output to the ACS calculator 13.

On the other hand, when the constraint length of the convolutional encoder is K, the ACS calculator 13 updates the state metric by performing branch selection after adding branch metrics to the state metric of 2 ^K-1 . Thereafter, the ACS operator 13 outputs the minimum state number, which is the number of states having a survival metric and a minimum state metric, to the backtracking calculator 14. In addition, the traceback calculation unit 14 performs the traceback as much as the traceback depth starting from the minimum state number, and outputs the signal decoded through the traceback to the output buffer 15. Then, the output buffer 15 rearranges the signals in chronological order as LIFO (Last In First Out).

However, the conventional Viterbi decoder described above has a large internal delay due to the characteristics of the algorithm, and this delay causes a reduction in the overall modem transmission speed. In an environment requiring a current high transmission speed, each state is parallel ACS. Not only does the hardware increase by having a structure, but there is a problem that additional power consumption increases much compared to the case of a low speed modem.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to add a path having a shortened delay inside the Viterbi decoder, so that there is no deterioration in performance, the Viterbi decoder By reducing the delay to the signal output of the Viterbi decoder by reducing the delay of the Viterbi decoder, the data transmission speed is increased, and the unused blocks are stopped. The present invention provides a Viterbi decoder having a shorter delay time path for reducing power consumption and a method of controlling the same.

In order to achieve the above object, a Viterbi decoder having a delay time shortening path of the present invention is a Viterbi decoder used for decoding a convolutional code.

An input buffer for supplying a soft decision signal to the input signal in accordance with the operation of the Viterbi decoder;

A branch metric calculator configured to calculate and output a branch metric value of the soft-determined signal received from the input buffer;

An ACS calculator for updating the status metric through the branch metric value inputted from the branch metric calculator and outputting survival path information, and selectively outputting a minimum state number according to a first path selection signal supplied from the outside;

Receives the survival path information and the minimum state number from the ACS operation unit, stores the survival path information as the traceback depth according to the second path selection signal supplied from the outside, and traces back from the minimum state number to finally decode the signal. A traceback calculation unit for outputting a; And

And an output buffer for storing and outputting the final decoded signal from the traceback calculation unit.

In addition, the control method of the Viterbi decoder having a delay time shortening path includes an input buffer; Branch metric operation unit; An ACS calculation unit including an ACS unit, a minimum metric calculation unit, and a mux; A backtracking calculation unit including a memory unit and a memory address control unit; In the control method of a Viterbi decoder composed of an output buffer,

An eleventh step of determining, by the ACS calculator, whether a first path selection signal is input from the outside;

A twelfth step of stopping, by the ACS calculator, the minimum metric calculator when the first path selection signal is input from the outside in the eleventh step; And

And the thirteenth step of outputting, by the ACS calculation unit, a predetermined minimum state number through the mux.

In addition, the control method of the Viterbi decoder having a delay time shortening path includes: an input buffer; Branch metric operation unit; An ACS calculation unit including an ACS unit, a minimum metric calculation unit, and a mux; A backtracking calculation unit including a memory unit and a memory address control unit; In the control method of a Viterbi decoder composed of an output buffer,

A twenty-first step of determining, by the backtracking calculating unit, whether the memory address control unit receives a second path selection signal from an external source; And

When the second path selection signal is not input from the outside in the twenty-first step, the twenty-second step of generating a memory write / read address using the memory bank of the memory unit is performed.

Hereinafter, a Viterbi decoder having a delay time reduction path and a control method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a functional block diagram of a Viterbi decoder having a delay time shortening path according to an embodiment of the present invention. The Viterbi decoder having a delay time shortening path according to an embodiment of the present invention includes an input buffer 110, It is composed of the branch metric calculation unit 120, ACS operation unit 130, back trace operation unit 140 and the output buffer 150.

At this time, the role and operation of the input buffer 110, branch metric operation unit 120 and output buffer 150 is the same as in Figure 1 will be omitted, and the present invention is different from the conventional decoder of Figure 1 The first path selection signal and the second path selection signal are respectively input to the ACS operation unit 130 and the backtracking operation unit 140. This signal is for selecting a short delay path of each block. The first and second path selection signals are signals that are determined and output by a block capable of calculating a performance of a modem, and are generated in a block in which an error rate is determined . An example of a block capable of determining an error rate is an example of a modem receiver. Currently, most communication systems have their own function of checking whether an error frame has occurred. That is, when the receiving system receives one frame, the receiving system sends a message to the transmitting system whether or not it was received well. If an error occurs, the receiving system requests the transmitting system to retransmit. At this time, if the number of successive frames is more than a predetermined level, it is determined that the channel situation is good at this time. That is, when it is determined that the error rate of the received signal is less than or equal to the preset error rate, the receiving system generates a second path selection signal. When the frame is measured again and no error occurs, the first path selection signal is generated when the error rate is determined to be less than or equal to the preset error rate.

Therefore, the ACS calculator 130 updates the state metric through the branch metric value input from the branch metric calculator 120, outputs survival path information, and minimizes the path according to the first path selection signal supplied from the outside. It selectively outputs the status number. In this case, as shown in FIG. 3, the ACS calculation unit 130 includes an ACS unit 131, a minimum metric calculation unit 132, and a mux 133.

The ACS unit 131 of the ACS operation unit 130 updates the new path metric by adding the branch metric and the path metric inputted from the branch metric operation unit 120 and outputs the new path metric to the minimum metric calculation unit 132. Print out survival path information. On the other hand, the minimum metric calculation unit 132 finds the state metric having the smallest value among all the state metric and outputs the state number. This requires a large number of adders and muxes. Also, the mux 133 outputs a minimum state number or an arbitrary number (for example, "0") in accordance with the first path selection signal. In this case, the Viterbi algorithm is combined into a single path when the backtracking is performed at a depth of more than a predetermined length as shown in FIG. 5. Therefore, when the traceback depth is longer than the convergence period of FIG. 5, a decoded value can be obtained even if an arbitrary state number is set and the operation of the minimum metric calculation unit 132 is stopped. Therefore, it is possible to eliminate the time delay required for the minimum metric detection and to reduce the power consumption.

On the other hand, the backtracking operation unit 140 receives the survival path information and the minimum state number from the ACS operation unit 130, and stores the survival path information as the backtracking depth according to the second path selection signal supplied from the outside and And back traces the minimum state number to output the final decoded signal to the output buffer 150. At this time, the backtracking operation unit 140 is composed of a memory unit 141 and a memory address control unit 142, as shown in FIG.

The memory unit 141 of the backtracking operation unit 140 has a memory bank therein, and serves to store the survival path information received from the ACS operation unit 130 through a memory writing process, and the memory address control unit ( 142 generates a new traceback address by generating a write address for storing survival route information in the memory unit 141 and a read address for a traceback process according to a second route selection signal supplied from the outside. do. At this time, the address of the memory unit 141 indicates each state, and the index is a division indicating the order of data. FIG. 4 illustrates an example in which a K-pointer even algorithm is used when K = 3 among memory-based backtracking methods that are frequently used for backtracking of the Viterbi algorithm. In FIG. 4, memory bank 1 performs a memory write process, while memory banks 2, 4, and 6 perform a memory read process. The survival path information input from the ACS calculator 130 is sequentially stored through a memory writing process while increasing the index. When one memory bank is filled, it is stored in the next memory bank. At this time, there are three pointers used to read the memory. The memory bank 2 reads the decoded value, and the memory banks 4 and 6 show the process of backtracking as much as the traceback depth. Here, the backtracking process is performed to decrease the index of the memory. The start address of the traceback process is output from the mux 133 of the ACS operation unit 130. Inputting the traceback start address into the memory bank as the read address outputs the stored data at the next clock. The traceback is performed by combining the output data with the current read address to get a new read address. As is well known, backtracking beyond the backtracking depth (5 * K ~ 7 * K: K = restraint) yields a decoded value. The reading process of memory bank 2 is a process of obtaining a decoded value.

Like the K-pointer even algorithm described above, other memory-based traceback algorithms require a lot of delay to output. According to the present invention, when there is no performance deterioration, the delay is reduced by using only part of the memory instead of all of the memory. When an external second path selection signal is input to the memory address control unit 142, the memory address control unit 142 does not increase the index of the memory bank to the end of the memory bank during a memory write process. Increment by only the indicated portion) and move to the next memory bank. Similarly, in the memory read process, the back of the memory bank is traced forward from the predetermined part and the back of the memory bank is traced back to the next memory bank. In FIG. 4, the memory bank shows a case in which the traceback depth is 7K, and the case in which the traceback depth is 5K is used when the dotted line is used. In the embodiment of Figure 4 has the effect of reducing the delay of about 28%.

Next, a control method of a Viterbi decoder having a delay time shortening path according to an embodiment of the present invention having the above configuration will be described with reference to the accompanying drawings.

First, the control method of the ACS calculation unit among the control method of the Viterbi decoder having a delay time shortening path according to an embodiment of the present invention will be described with reference to FIG. 6. The ACS calculator 130 determines whether the first path selection signal is input from the outside (S11). At this time, when the first path selection signal is input from the outside in the eleventh step S11 (YES), the ACS calculator 130 stops the operation of the minimum metric calculator 132 (S12). Therefore, the ACS calculator 130 outputs the minimum state number (eg, “0”) set in advance through the mux 133 to the traceback calculator 140 (S13). On the other hand, if the first path selection signal is not input from the outside in the eleventh step S11 (NO), the ACS calculation unit 130 returns the minimum state number calculated by the minimum metric calculation unit 132. The traceback calculator 140 outputs the information to the traceback calculator 140 through step S133.

On the other hand, the control method of the traceback operation unit among the control method of the Viterbi decoder having a delay time reduction path according to an embodiment of the present invention will be described with reference to FIG. First, the memory address controller 142 of the traceback calculator 140 determines whether a second path selection signal is input from the outside (S21). At this time, when the second path selection signal is not input from the outside in the twenty-first step S21 (NO), the memory address controller 142 writes / writes a memory using all of the memory banks of the memory unit 142. Generate a read address (S22). On the other hand, when the second path selection signal is input from the outside in the twenty-first step S21 (YES), the memory address controller 142 uses only the preset memory in the memory bank of the memory unit 141. Generates a memory write / read address (S23).

The method of the present invention as described above may be implemented as a program and stored in a computer-readable recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.).

Although the present invention has been described in more detail with reference to some embodiments, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, according to the Viterbi decoder having a delay time reduction path and a control method thereof according to the present invention, by adding a path for reducing the signal decoding delay inside the Viterbi decoder, there is almost no deterioration in performance. By executing the short path, it reduces the demodulation delay of the modem reception signal so that the data can be transmitted and received quickly. Therefore, if the response is required during the inter frame interval time, the operation can be performed faster. Therefore, there is an excellent effect of increasing the overall data transmission amount.

Claims (9)

In the Viterbi decoder used for decoding convolutional codes, An input buffer for supplying a soft decision signal to the input signal in accordance with the operation of the Viterbi decoder; A branch metric calculator configured to calculate and output a branch metric value of the soft-determined signal received from the input buffer; It updates the state metric through the branch metric value input from the branch metric calculation unit and outputs the survival path information, and determines the error rate of the received signal and outputs a first path selection signal when the error rate is less than or equal to a preset error rate. An ACS calculator configured to selectively output a minimum state number when the first path selection signal is received from an external device ; The second path selection signal is received from an external device that receives the survival path information and the minimum status number from the ACS calculator and determines an error rate of the received signal and outputs a second path selection signal when the error rate is less than or equal to a preset error rate. A traceback calculation unit for storing the input survival path information as much as the traceback depth and receiving the traceback signal from the minimum state number and outputting the final decoded signal; And Viterbi decoder having a delay time reduction path characterized in that the output buffer for storing and outputting the last decoded signal from the traceback calculation unit. The method of claim 1, The ACS operation unit may include: an ACS unit configured to add a branch metric and a path metric inputted from the branch metric calculation unit to update to a new path metric and to output information on a survival path; Wherein when ACS unit the new path metrics generated from the search of a path metric of the lowest value of all the path metrics but outputs the state number, and a minimum metric computing section that the operation stops when the first path selection signal input; And And a mux outputting a minimum state number already set when the first path selection signal is input, and outputting a minimum state number input from the minimum metric calculation unit when the first path selection signal is not input from the outside. Viterbi decoder having a shorter delay time path. The method of claim 2, Viterbi decoder having a shortened time delay path, characterized in that any minimum state number is selectively output through the mux. The method of claim 1, The traceback calculating unit may include: a memory unit having a memory bank therein and storing survival path information received from the ACS calculating unit through a memory writing process; And And a memory address controller configured to generate a write address for storing survival path information in the memory unit and a read address for a traceback process according to the received second path selection signal to generate a new traceback address. Viterbi decoder with low latency path. An input buffer; Branch metric operation unit; An ACS calculation unit including an ACS unit, a minimum metric calculation unit, and a mux; A backtracking calculation unit including a memory unit and a memory address control unit; In the control method of a Viterbi decoder composed of an output buffer, Determining an error rate of a received signal to determine whether the first path selection signal has been received by the ACS calculator from an external device that outputs a first path selection signal when the error rate is less than or equal to a preset error rate ; A twelfth step of stopping the operation of the minimum metric calculator by the ACS operator when the first path selection signal is input in the eleventh step; And And a thirteenth step of outputting a predetermined minimum state number through the mux, by the ACS operator. The method of claim 5, In the first step 11 features include this the operation 14 that if the first path selection signal is received, outputting the additional ACS operation a minimum condition number calculated by the minimum metric computing unit through the MUX Still further A control method of a Viterbi decoder having a shortened delay time path. The method of claim 5, In the thirteenth step, a preset minimum state number selectively outputted through the mux is "0". An input buffer; Branch metric operation unit; An ACS calculation unit including an ACS unit, a minimum metric calculation unit, and a mux; A backtracking calculation unit including a memory unit and a memory address control unit; In the control method of a Viterbi decoder composed of an output buffer, When the second path selection signal is received from an external device that outputs a second path selection signal when the error rate is less than or equal to a preset error rate by determining an error rate of the received signal, the input second path selection signal is the traceback calculating unit. A twenty-first step of determining whether a memory address controller has been inputted; And If in the first step 21 and the second path selection signal is received, the delay time reduction, characterized in that composed of claim 22 further comprising: said memory address control unit generates the memory write / read address to all use of the memory unit the memory banks A control method of a Viterbi decoder having a path. The method of claim 8, If the second path selection signal input in the first step 21, the memory address control section include this the first step 23 to add more to generate the memory write / read address to be used only a predetermined memory in the memory unit the memory banks A control method of a Viterbi decoder having a shortened delay path.

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