JP2000252840A - Error-correcting decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of conflict paths to be obtained and to reduce the calculation quantity of path metrics by calculating differences between path metrics in various states on a selected path and a path metric that a calculated conflict path merges and selecting the minimum value as the logarithmic likelihood ratio of hard-decided bits. SOLUTION: A branch metric calculation part 14 of a survival path calculation part 11 calculates the transition likelihood, closure, and branch metric of a trellis on the basis of an information bit (x), a post-information bit Lu, and a parity bit (y) which are inputted and an ACS part 15 accumulates and sums up them to calculate path metrics. Furthermore, a survival path is selected according to viterbi algorithm and saved in a path memory 12. On the basis of it, an ML path selection and hard decision part 13 calculates an ML path, which is traced back to make a hard decision. Furthermore, a soft decision part 20 calculates the logarithmic likelihood ratio of soft-decided bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoder which receives a transmission signal which has been subjected to recursive systematic convolutional coding and outputs a soft decision.

[0002]

2. Description of the Related Art An error correction decoder for soft-decision-outputting a signal subjected to recursive tissue convolutional coding is used for decoding an inner code of a turbo code or a concatenated code. In general, MAP (Ma
ximum A Posteriori probability) algorithm and
There is an algorithm of SOVA (Soft Output Viterbi Algorithm).

[0003] Among them, the MAP algorithm has a huge amount of calculation and is not suitable for hardware implementation. On the other hand, S
The OVA algorithm requires less computation than the MAP algorithm. However, the SOVA algorithm is complicated, and there is a problem in that if it is to be realized by hardware, the circuit scale becomes large and the power consumption becomes large.

FIG. 6 is a trellis transition diagram for explaining the algorithm of SOVA. In the figure, time k +
In the case of 6, the ML (Most Likelih
ood) Select the path P61, trace back to time k, and make a hard decision. The soft-decision value of the bit hard-decided by the Viterbi algorithm at time k is M between time k and k + 6.
Among the paths that merge with the L path and have values different from the bits hard-decided in the transition from time k-1 to k, the path having the maximum path metric at the time of merging with the ML path must be specified. Must. The difference between the path metric of the path selected in this way and the path metric of the ML path at the merge point is calculated. Assuming that the difference between the path metrics is Δ, seven Δs are obtained in FIG. The one having the smallest value among the seven Δs obtained in this manner is set as the soft-decision value of the bit hard-decided by the Viterbi algorithm.

[0005] A concrete description will be given taking the competitive path P62 as an example. The transition of the state from time k + 3 to k + 4 is uniquely determined because it is the transition to the merge point with the ML path.
Two transitions can be considered for the state transition from time k + 2 to k + 3. Similarly, two transitions can be considered for the transition from time k + 1 to k + 2 and the transition from time k to k + 1.
The transition from time k-1 to time k is uniquely determined because it is a transition having a value different from the bit determined by the Viterbi algorithm.

[0006] As described above, in order to obtain the ML path and merge competing path at time k + 4, 2 ³ pieces for the path of the (eight) must calculate the path metric. That is, in FIG. 6, 1 + 1 + 2 + 4 + 8 + 16 + 32
= Path metric must be calculated for 64 competing paths.

[0007] Also, as one of the methods for calculating the conflict path, the Register Exchange method has been proposed. This method can reduce the number of conflict paths that need to be determined, compared to a method of searching for all possible conflict paths.
However, in order to obtain sufficient performance, the number of contention paths to be obtained needs to be five times the constraint length, and the processing amount for obtaining contention paths is still large.

[0008]

As described above, an error correction decoder which outputs a signal which has been subjected to recursive systematic convolutional coding in a soft-decision manner calculates path metrics of a large number of paths in order to obtain a competitive path. There must be. For this reason,
Attempts to implement with hardware have the problem of increasing the circuit scale and power consumption.

The present invention has been made in view of the above circumstances, and its purpose is to reduce the number of competing paths that need to be obtained, thereby reducing the amount of calculation of the path metric. An object of the present invention is to provide an error correction decoder which has a small circuit size and low power consumption.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an error correction decoding circuit for receiving a signal subjected to recursive systematic convolutional encoding and softly outputting the information bit and the posterior information of a received signal. Transition likelihood calculating means for calculating a trellis transition likelihood from the bits and the error detection bits,
Addition / comparison / selection means for cumulatively adding the transition likelihoods of the trellis calculated by the transition likelihood calculation means to calculate a path metric, and selecting a maximum path metric from a plurality of paths input to each trellis, A path metric of the path selected by the comparison and selection means, and storage means for storing the bits hard-decided by the transition of the selected path, and a maximum value in a state where a signal of a predetermined length is received. Is selected, the selected path is traced back by a predetermined length, and the decoded bit at the point after the traceback is hard-determined stored in the storage means. And a branch metric from all transitions on the trellis giving a sign different from the bit hard-decided by the hard-decision means. Path metric calculation means for calculating a new path metric by adding the path metric stored in the storage means to the calculated branch metric, and a new path metric calculated by the path metric calculation means. The calculation of the transition likelihood by the transition likelihood calculation means and the selection of the maximum path metric by the addition / comparison / selection means are performed again, and the new path metric obtained by this is stored in the storage means. And a branch metric of a transition entering each state on the path selected by the hard decision means, and a path metric corresponding to a transition source state of the branch metric is calculated from the storage means in the calculated branch metric. Read and add this as the path metric of the competing path, and A competing path calculating means for calculating a competing path by a length, a path at a point where the path metric of each state on the path selected by the hard decision means and the competing path calculated by the competing path calculating means are merged. A difference calculating means for calculating a difference between the metrics, and a minimum value selected from the differences between the path metrics calculated by the difference calculating means, and a log likelihood ratio of the bits hard-decided by the hard decision means. And means for performing the above steps.

According to another aspect of the present invention, there is provided an error correction decoding circuit for receiving a signal subjected to recursive systematic convolutional encoding and softly outputting the signal, wherein a trellis transition likelihood is determined from information bits, a posteriori information bits, and error detection bits of the received signal. And a path metric calculated by cumulatively adding the transition likelihoods of the trellis calculated by the transition likelihood calculation means, and calculating the maximum path metric from a plurality of paths input to each trellis. And a path metric of a path selected by the addition / comparison / selection means,
A difference calculating means for calculating and storing a difference from the path metric of the path not selected, and a storing means for storing bits hard-decided by the transition of the path selected by the addition / comparison / selection means; While the signal of the length is received, the path having the maximum path metric is selected, and the selected path is traced back by a predetermined length. And a means for selecting one of the log likelihood ratio and the difference stored in the difference calculation means and making this a soft output with the hard-decision bit stored in the storage means. It is a feature.

In particular, the length of calculating the above-mentioned competing path depends on the characteristics of the transmission path and the quality of service (QoS) required for communication.
ervice).

That is, according to the present invention, at the time of hard decision, a path having a transition having a value different from that of the hard-decided bit is selected as a conflict path, and a modified Viterbi algorithm is selected from these conflict paths. Calculate the surviving conflict path. Then, a path metric at a point where the obtained surviving competitive path and the ML path are merged is calculated, and the smallest one is set as a soft decision value.

Therefore, according to the present invention, it is possible to reduce the number of competing paths to be obtained by half compared with the conventional soft decision decoder, and to calculate the competing paths in accordance with the required error correction capability. By making the length variable, error correction can be performed with a minimum necessary amount of calculation. Therefore, the circuit size of the hardware can be reduced and the power consumption can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit block diagram showing a first embodiment of an error correction decoder according to the present invention. The error correction decoder includes a hard decision unit 10 and a soft decision unit 20.

The hard decision unit 10 includes a surviving path calculation unit 11, a path memory 12, and an ML path selection / hard decision unit 13. Survival path calculator 11
Is the branch metric calculation unit 14 and the ACS (Add Co
mpare Select) unit 15. The branch metric calculator 14 calculates the transition likelihood of the trellis, that is, the branch metric, based on the input information bits x, posterior information bits Lu and parity bits y. ACS
The unit 15 calculates a path metric by cumulatively adding the branch metrics calculated by the branch metric calculation unit 14, and further selects a surviving path according to the Viterbi algorithm. Information on the selected surviving path is stored in the path memory 12. The ML path selection / hard decision unit 13 calculates an ML (Most Likelihood) path based on the surviving paths stored in the path memory 12, and traces back along the ML path to perform a hard decision.

On the other hand, the soft decision unit 20 calculates the log likelihood ratio of the hard-decided bits, and survives a competitive path calculation unit 21, a Δ calculation unit 22, a Δ update unit 23, and a multiplication unit 2.
And 4. The surviving competitive path calculation unit 21
Competing path branch metric calculator 25 and competing path A
CS unit 26.

Competing path branch metric calculator 25
Is used to find a conflict path for the ML path selected by the ML path selection / hard decision section 13 of the hard decision section 10, and calculates a branch metric of the conflict path. The competing path ACS unit 26 calculates a surviving competing path using the branch metric of the competing path calculated by the competing path branch metric calculating unit 25, and provides the calculation result to the Δ calculating unit 22. The Δ calculation unit 22 is different from the ML path in that the surviving competition path obtained by the competition path ACS unit 26 and the ML path obtained by the ML path selection / hard decision unit 13 of the hard decision unit 10 are merged. Of the path metric of the competing path is calculated.

Each time a new difference Δ is calculated by the Δ calculation unit 22, the Δ update unit 23 compares the new difference Δ with the stored difference Δ. And the new difference Δ
Is smaller than the stored difference Δ, the stored content is updated by overwriting the stored difference Δ with a new difference Δ. On the other hand, if the new difference Δ is equal to or larger than the stored difference Δ, the stored difference Δ is left as it is, and the currently calculated new difference Δ is discarded. The update of the difference Δ is performed a predetermined number of times for the bits hard-decided by the hard decision unit 10. That is, the difference Δ is updated by the number of times corresponding to the length of the competition path.

Next, the algorithm of soft decision by the error correction decoder configured as described above will be specifically described with reference to a trellis transition diagram. Now, suppose that the ML path selection / hard decision unit 13 selects the ML path P21 shown in FIG. 2 and makes a hard decision of 0 at time t. At this time, first, the competing path branch metric calculation unit 25 calculates the branch metric of the transition giving a value different from the hard-decided bit. For example, in FIG.
To transitions P22, P23, P24,
The branch metric of P25 is calculated.

When this branch metric is calculated,
This is added to the path metric of each state at time t−1, whereby the path metric of the competing path at time t is obtained. In FIG. 2, when the path metric of the conflicting path at time t is obtained, the conflicting path P22 and the ML path P2 are determined.
1 merges with the state 0 at the time t. Then, a difference Δ0 of the path metric between the competing path P22 and the ML path P21 at the merge point is calculated by the Δ calculation unit 22, and the calculated difference Δ0 is stored in the Δ update unit 23. Thus, the path metric of the competing path at time t is calculated.

Subsequently, referring to FIG. 3, from time t to time t +
1 will be described. The surviving contention path calculation unit 21 first selects one path from two paths flowing into each state according to the Viterbi algorithm for each state at time t + 1. that time,
The Viterbi algorithm is partially changed with respect to contention path selection. In other words, a condition is added to the Viterbi algorithm that the path that has flowed in from the state in which the ML path has passed does not survive and become a candidate for a competitive path. For example, in FIG. 3, the path P3 of the transition from state 0 at time t to state 0 at time t + 1
1 is excluded from the selection candidates for the surviving conflict path at time t + 1 because the ML path passes on state 0 at time t.

From the above algorithm, the paths P32, P3
3, P34 and P35 are selected as surviving competitive paths. At this time, since the path P33 is merged with the ML path in state 2 at time t + 1, the Δ calculation unit 22 calculates the difference Δ1 of the path metric at the merge point. When the path metric difference Δ1 is calculated, the Δ update unit 23 compares the newly obtained difference Δ1 with the stored difference Δ, and stores a new path metric difference Δ1 as a result of the comparison. If the difference is smaller than the difference Δ, the stored difference Δ is updated to the new difference Δ1.

Next, a method of calculating a surviving competitive path and a method of updating the difference Δ will be described with reference to FIG. The surviving and competing path calculation unit 21 calculates the path metric flowing into each state at the time t + 2, and performs comparison and selection. At this time, the path P41 of the transition from the state 2 at the time t + 1 to the state 1 at the time t + 2 passes through the ML path to the state 2 at the time t + 1. The path P42 that transits from the state 3 at the time t + 2 to the state 1 at the time t + 2 is selected as one of the surviving conflict paths.

Then, by selecting the surviving competing path by the above conditions and the Viterbi algorithm, the path P42,
It is assumed that P43, P44, and P45 have been selected. At this time, since the path P42 is merged with the ML path in the state 3 at time t + 2, the difference Δ2 of the path metric at this merge point is calculated by the Δ calculation unit 22. When the path metric difference Δ2 is calculated, the Δ update unit 23 compares the newly obtained difference Δ2 with the stored difference Δ, and stores a new path metric difference Δ2 as a result of the comparison. If the difference Δ is smaller than the difference Δ, the stored difference Δ is updated to the new difference Δ2.

In this way, the surviving competing path is calculated for a determined length, and the difference Δ is updated as needed. The length for calculating the surviving competition path is usually set to about three times the constraint length. Thus, the soft decision value Δ of the bit hard-decided at time t in FIG. 2 is obtained.

As described above, in the first embodiment, at the time of hard decision, a path having a transition having a value different from that of the hard-decided bit is defined as a conflict path, and a change is made from these conflict paths. The surviving competitive path is calculated by the added Viterbi algorithm. Then, a path metric at a point where the obtained surviving competitive path and the ML path are merged is calculated, and the smallest one is set as the soft decision value.

Therefore, the number of competing paths that must be obtained is halved, and the length of calculating the competing paths is made variable according to the required error correction capability, so that error correction can be performed with a minimum necessary amount of calculation. Can do it. For this reason, it is possible to reduce the circuit scale of hardware and reduce power consumption.

(Second Embodiment) In the first embodiment, the length for calculating the surviving contention path is set to about three times the constraint length. However, the transmission path quality is good and information errors occur so much. Otherwise, a sufficient error correction capability can be obtained even if the length for calculating the surviving conflict path is set to one.

Therefore, when the transmission path quality is good, a soft decision error corrector is constructed as shown in FIG. 5 to derive a soft decision value. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals.

That is, in the soft decision unit 20 ', there is no need to update the difference Δ with respect to the hard-decided bits.
The update unit 23 is omitted. Also, an algorithm for performing a soft decision can be realized by using the difference Δ0 obtained in FIG. 2 as a decision value as it is. With this configuration, when the transmission path quality is good, the amount of calculation for soft decision can be further reduced.

Also, the length of calculating the contention path is determined by the quality of service (QoS) required for the state of the transmission path and communication.
By making the variable according to e), it is possible to perform optimal error correction with a minimum amount of calculation.

[0033]

As described in detail above, according to the present invention, at the time of hard decision, a path having a transition having a value different from that of the hard-decided bit is selected as a competing path. The surviving competitive path is calculated by the modified Viterbi algorithm. Then, a path metric at a point where the obtained surviving competitive path and the ML path are merged is calculated, and the smallest one is set as the soft decision value.

Therefore, according to the present invention, it is possible to reduce the number of competing paths to be obtained by half compared with the conventional soft decision decoder, and to calculate the competing path in accordance with the required error correction capability. By varying the error, it is possible to perform error correction with a minimum necessary amount of calculation, thereby providing an error correction decoder with a reduced hardware circuit size and reduced power consumption. .

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of an error correction decoder according to the present invention.

FIG. 2 is a trellis transition diagram for explaining a procedure and contents of a soft decision algorithm in the decoder shown in FIG. 1;

FIG. 3 is a trellis transition diagram for explaining a procedure and contents of a soft decision algorithm in the decoder shown in FIG. 1;

FIG. 4 is a trellis transition diagram for explaining a procedure and contents of a soft decision algorithm in the decoder shown in FIG. 1;

FIG. 5 is a circuit block diagram showing a second embodiment of the error correction decoder according to the present invention.

FIG. 6 is a trellis transition diagram for explaining an SOVA algorithm.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Hard decision part 11 ... Remaining path calculation part 12 ... Path memory 13 ... ML path selection / hard decision part 14 ... Branch metric calculation part 15 ... ACS part 20, 20 '... Soft decision part 21 ... Remaining competition path calculation part 22 ... Δ calculation section 23 .DELTA. Update section 24... Multiplication section 25... Competitive path branch metric calculation section 26... ACS section x... Information bit Lu... Post information bit y... Parity bit P21. P33, P41, P42, P43 ... Pass

Claims (3)

[Claims] An error correction decoding circuit for receiving a signal subjected to recursive tissue convolutional encoding and softly outputting the signal, calculates a transition likelihood of a trellis from information bits, a posteriori information bits, and error detection bits of the received signal. A transition likelihood calculating means, and a path metric is calculated by cumulatively adding the transition likelihoods of the trellis calculated by the transition likelihood calculating means, and adding the maximum path metric from a plurality of paths input to each trellis. Comparing and selecting means; a path metric of the path selected by the adding and comparing means; and storing means for storing the bits hard-decided by the transition of the selected path, and a signal of a predetermined length. In the received state, select the path with the largest path metric, trace back the selected path by a predetermined length, and Hard decision means for setting decoded bits at a point after the traceback to hard decision bits stored in the storage means; and all transitions on the trellis giving codes different from the bits hard decided by the hard decision means. A path metric calculating means for calculating a new path metric by adding the path metric stored in the storing means to the calculated branch metric; and a new path metric calculated by the path metric calculating means. Based on the path metric, the calculation of the transition likelihood by the transition likelihood calculation means and the selection of the maximum path metric by the addition / comparison / selection means are performed again, and the new path metric obtained by this is stored in the storage means. A storage unit; and a transition block that enters each state on the path selected by the hard decision unit. A launch metric is calculated, and a path metric corresponding to the state of the transition source of the branch metric is read out from the storage means and added to the calculated branch metric to obtain a path metric of a competing path. A competing path calculating unit that calculates only the competing path, a path metric of each state on the path selected by the hard decision unit, and a path metric of a point where the competing path calculated by the competing path calculating unit is merged. A difference calculating means for calculating the difference; and a means for selecting a minimum value from among the differences of the path metrics calculated by the difference calculating means, and using this as a log likelihood ratio of the bit hard-decided by the hard decision means. An error correction decoder comprising: 2. An error correction decoding circuit for receiving a signal subjected to recursive tissue convolutional encoding and softly outputting the signal, calculates a transition likelihood of a trellis from information bits, a posteriori information bits, and error detection bits of the received signal. A transition likelihood calculating means, and a path metric is calculated by cumulatively adding the transition likelihoods of the trellis calculated by the transition likelihood calculating means, and adding the maximum path metric from a plurality of paths input to each trellis. Comparison and selection means; difference calculation means for calculating and storing the difference between the path metric of the path selected by the addition and comparison means and the path metric of the non-selected path; and Storage means for storing bits hard-decided by path transitions, and a maximum path metric when a signal of a predetermined length is received The path having the selected path is traced back by a predetermined length, and the decoded bit at the point after the traceback is set as a hard-decision bit stored in the storage unit, and its logarithm is calculated. Means for selecting one of the likelihood ratio and the difference stored in the difference calculation means and for making the soft output a soft output. 3. The length of calculating the competing path is determined by the characteristics of the transmission path and the QoS (Quality of Service) required for communication.
3. A variable according to ce).
An error correction decoder as described.