JPH07302882A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which has a PNP transistor and an NPN transistor which are arranged to improve latch-up resistance. CONSTITUTION:A semiconductor device 10, which has a PNP transistor including a p-type emitter layer connected to a constant voltage power source Vcc and an NPN transistor including an n<+>-type emitter layer 20 earthed and provided next to the PNP transistor, is constituted so that the n<+>-type base layer 16 of the PNP transistor may be arranged between the p-type emitter layer 17 and the NPN transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PNP type transistor including a p type emitter layer connected to a constant voltage power source Vcc, and an NPN type grounded n ⁺ type emitter layer adjacent to the PNP transistor. The present invention relates to a semiconductor device having a type transistor.

[0002]

2. Description of the Related Art Conventionally, such a semiconductor device is constructed, for example, as shown in FIGS. That is,
In FIG. 3, the semiconductor device 1 includes an n ⁺ type buried layer 3, 3 ′ on the surface of the p type silicon substrate 2 by thermal diffusion or the like.
Is formed, and the n-type layer 4 is formed over the entire surface of the substrate by epitaxial growth or the like, and then the p ⁺ -type layer 2a is formed around the n-type layer 4 to separate the n-type layer 4 from each other. To do.

Subsequently, in the region corresponding to the n ⁺ type buried layer 3 on the surface of the n type layer 4, an annular p type collector layer 5 and an n type collector layer 5 are formed.
^{The +} type base layer 6 is formed and the p type collector layer 5 is formed.
A p-type emitter layer 7 is formed on the inside of the.

Further, the n ⁺ type collector layer 8 and the p type base layer 9 are formed in a region corresponding to the n ⁺ type buried layer 3'on the surface of the n type layer 4, and the p type base layer is formed. An n ⁺ type emitter layer 9 a is formed on the surface of 9.

The semiconductor device 1 having the above-described structure has n
^In the region corresponding to the ⁺ -type buried layer 3, the p-type collector layer 5 acts as a collector, the n ⁺ -type base layer 6 acts as a base, and the p-type emitter layer 7 acts as an emitter. In the region corresponding to the n ⁺ -type buried layer 3 ′, the n ⁺ -type collector layer 8 serves as a collector, the p-type base layer 9 serves as a base, and the n ⁺ -type emitter layer 9 a is provided in the region where the transistor is formed. An NPN transistor is formed by acting as an emitter. The p-type emitter layer 7 is connected to the constant voltage power supply Vcc, and the n ⁺ -type emitter layer 9a is connected to the ground Gnd.

[0006]

However, in the semiconductor device 1 having such a configuration, when the latch-up withstanding test is performed and latch-up is generated, P
Since the p-type emitter layer 7 of the NP transistor and the n ⁺ -type emitter layer 9a of the NPN transistor are arranged relatively close to each other, the current from the constant voltage power supply Vcc causes the p-type emitter layer 7 to flow. From the n ⁺ type emitter layer 9a
Will flow to the ground. As a result, it may operate as a thyristor, and there is a problem that the latch-up resistance cannot be increased so much.

In view of the above points, the present invention has an object to provide a semiconductor device having a PNP transistor and an NPN transistor, which has improved latch-up resistance.

[0008]

According to the present invention, the above object is to provide an n-type layer surrounded by an isolation of a p ⁺ -type layer, and an annular p-type collector layer formed in the n-type layer. , N ⁺ -type base layer and a p-type emitter layer formed inside the annular p-type collector layer and connected to a constant voltage power source Vcc, and a p ^{+ -type} transistor adjacent to the PNP transistor. An n-type layer surrounded by an isolation formed of a type layer, and n ⁺ formed in the n-type layer
Having -type collector layer, a p-type base layer, an NPN transistor consisting of the n ⁺ -type emitter layer and which is formed and the ground connection to the p-type base layer, in the semiconductor device, the PNP transistor n ⁺ -type base A semiconductor device, characterized in that a layer is arranged between the annular p-type collector layer and the NPN transistor.

[0009]

According to the above structure, the p-type emitter layer of the PNP transistor and the n ⁺ -type emitter layer of the NPN transistor are relatively separated from each other due to the n ⁺ -type base layer of the PNP transistor. Will be done. Therefore, the emitter diffusion reduces the hFE of the parasitic PNP transistor including the p-type collector layer, the n-type layer of the PNP transistor, and the p ⁺ -type layer which is the isolation. As a result, the operation as a thyristor is excluded, and the latch-up withstand capability can be improved.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. 1 and 2 show P according to the present invention.
1 shows an example of a semiconductor device having an NP transistor and an NPN transistor. 1 and 2, in the semiconductor device 10, the n ⁺ -type buried layers 12 and 12 ′ are formed on the surface of the p-type silicon substrate 11 by thermal diffusion or the like, and the entire surface of the substrate 11 is covered. After forming the n-type layer 13 by epitaxial growth or the like, the n-type layer 13 is formed.
The n ⁺ type layer 13 is separated by forming the p ⁺ type layer 14 around the.

Subsequently, in the region corresponding to the n ⁺ type buried layer 12 on the surface of the n type layer 13, an annular p type collector layer 15 is formed.
Is formed, and inside the p-type collector layer 15, p
The type emitter layer 17 is formed. Then, n ⁺ type base layer 1
6 is formed.

Further, the n ⁺ type collector layer 18 and the p type base layer 19 are formed in a region corresponding to the n ⁺ type buried layer 12 'on the surface of the n type layer 13, and the p type base layer is formed. 1
An n ⁺ type emitter layer 20 is formed on the surface of 9.

The above structure is similar to that of the conventional semiconductor device 1 shown in FIGS. 3 and 4, but in the semiconductor device 10 according to the embodiment of the present invention, the n ⁺ type base layer of the PNP transistor described above is used. 16 is a p-type collector layer 15
And an NPN transistor.

The semiconductor device 10 according to the present invention is configured as described above, and in the region corresponding to the n ⁺ -type buried layer 12, the p-type collector layer 15 serves as the collector and the n-type collector layer 15 serves as the collector.
^{By the +} type base layer 16 acting as a base and the p type emitter layer 17 acting as an emitter,
In the region corresponding to the n ⁺ type buried layer 12 ', the PNP type transistor is formed, and the n ⁺ type collector layer 18 serves as a collector, the p type base layer 19 serves as a base, and the n ⁺ type emitter layer is provided. 20 as an emitter,
An NPN type transistor is formed by acting on each.

In the case of the latch-up withstanding test, the p-type emitter layer 17 is connected to the constant voltage power supply Vcc and the n ⁺ -type emitter layer 20 is connected to the ground Gnd.

In this case, the p-type emitter layer 17 and n
^{The +} type emitter layers 20 are separated from each other by the n ⁺ type base layer 16 of the PNP transistor existing therebetween. Therefore, when a latch-up withstanding test is performed to cause latch-up, a parasitic PN composed of the p-type base layer 16, the n-type layer 13, and the p ⁺ -type layer 14 is formed.
The hFE of the P transistor becomes small. This would allow it to be eliminated acting as a parasitic thyristor. Thus, the latch-up tolerance can be improved.

[0017]

As described above, according to the present invention, P
The p-type emitter layer of the NP transistor and the n ⁺ -type emitter layer of the NPN transistor are relatively separated from each other due to the n ⁺ -type base layer of the PNP transistor therebetween. Therefore, due to the emitter diffusion, the hFE of the parasitic PNP transistor including the p-type collector layer, the n-type layer of the PNP transistor, and the p ⁺ -type layer which is the isolation is reduced. This eliminates the operation as a thyristor,
Latch-up tolerance can be improved. Thus, according to the present invention, an extremely excellent PNP transistor and N having improved latch-up resistance are provided.
A semiconductor device having a PN transistor can be provided.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device having a PNP transistor and an NPN transistor according to the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device of FIG.

FIG. 3 is a plan view showing an example of a semiconductor device having a conventional PNP transistor and an NPN transistor.

4 is a cross-sectional view of the semiconductor device of FIG.

[Explanation of symbols]

Reference Signs List 10 semiconductor device 11 p-type silicon substrate 12, 12 'n ⁺ type buried layer 13 n type layer 14 p ⁺ type layer 15 p type collector layer 16 n ⁺ type base layer 17 p type emitter layer 18 n ⁺ type collector layer 19 p type base layer 20 n ⁺ type emitter layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (1)

[Claims] 1. A p ⁺ and n-type layer which is surrounded by isolation consisting -type layer, an annular p-type collector layer formed on the n-type layer, and the n ⁺ -type base layer, the ring-shaped p-type collector layer A PNP-type transistor formed inside the substrate and comprising a p-type emitter layer connected to a constant voltage power supply Vcc, and the PN transistor.
Adjacent to the P-transistor, an n-type layer surrounded by isolation made of a p ⁺ -type layer, an n ⁺ -type collector layer and a p-type base layer formed in the n-type layer, and the p-type base layer A semiconductor device having an NPN-type transistor formed of an n ⁺ -type emitter layer formed inside and grounded, wherein the n ⁺ -type base layer of the PNP transistor is the annular p-type.
A semiconductor device, wherein the semiconductor device is arranged between the type collector layer and the NPN transistor.