JPH0729996A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To guarantee operations at a low voltage to sufficiently cope with a power source electric potential of 3.0V+ or -10% which is a market requirement. CONSTITUTION:A threshold value voltage in a bit line load circuit 11, a column gate 13, a write gate 14, a data transfer gate 12 of a memory cell, and a data bus load circuit 17 is set lower than that of other NMOSs. Incidentally, in order to reduce Vth, after an N channel doping step of forming a normal NMOS channel is completed, a mask of an NMOS channel part for reducing Vth is made to form it by performing a channel doping step again.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to an S memory device.
The present invention relates to guaranteeing an operation of a RAM (Static Random Access Memory) at a low voltage.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional embodiment. B in FIG.
L and XBL are a pair of bit lines, 21 is an NMOS 1
In the pair of bit line load circuits, the source is connected to the power supply potential, the drain is connected to one end of the bit line, and the gate is connected to the bit line load control signal LD. DB, XDB
Is a pair of data buses, and 23 is a pair of column gates having an NMOS structure, the source of which is the other end of the bit line, the drain is one end of the data bus, and the gate is the column selection signal C.
It is connected to G respectively. Reference numeral 15 is a data storage circuit, which is a pair of high resistance load elements 151 and 152 and a pair of NMOS.
The high resistance load element is composed of the elements 153 and 154. One end of the high resistance load element is at the power supply potential, and the other end is the drain M of the NMOS element.
The source of the NMOS element is grounded, the gate of 153 is MC, and the gate of 154 is XMC.
It is connected to the. 22 is a pair of NMOS data transfer gates, the source of which is the bit line and the drain of which is the drain MC, XM of the NMOS element of the data storage circuit.
The gate is connected to C and the gate is connected to the word line selection signal WL. WB and XWB are a pair of data write buses,
Reference numeral 24 denotes a pair of write gates having an NMOS structure, the source being one end of the data write bus, the drain being the other end of the data bus, and the gate being the data write control signal W.
It is connected to G respectively. An input / output circuit 16 is connected to the other end of the data write bus. 27 is N
In a pair of MOS data bus load circuits, the source and gate are connected to the power supply potential, and the drain is connected to one end of the data bus. A plurality of bit line pairs are connected to a pair of data buses via a pair of column gates. A plurality of data storage circuits are connected to a pair of bit lines via a pair of data transfer gates.

The operation of writing data to the data storage circuit and the data potential to be propagated in the semiconductor memory device having the above-mentioned structure will be described with reference to FIG.

In the NMOS element, when the potential is transmitted from the source to the drain, the potential corresponding to the threshold voltage VthN decreases. That is, when the power supply potential VDD is applied to the source side, the potential becomes VDD-VthN on the drain side. In the following description, the bit line load circuit 21 and the column gate 2
3, the threshold voltage of the write gate 24 is VthN, the threshold voltage of the data transfer gate 22, the NMOS elements 153 and 154 is VthM, and the back gate effect is ignored.

VDD and 0V are applied from the input / output circuit 16 to the data write bus pair WB and XWB, respectively. The potentials of the data buses DB and XDB are the data bus load circuit 27.
Is always on, and therefore is kept at VDD-VthN. When the data write control signal WG reaches the VDD potential (hereinafter abbreviated as “H”), the write gate 24 is turned on and the potentials of the data write buses WB and XWB are transferred to the data buses DB and XDB. At this time, the potential of the data bus becomes VDD-VthN and 0V, respectively. While the column gate selection signal CG is at the ground potential (hereinafter abbreviated as “L”), the bit line load control signal LD becomes “H”, the bit line load circuit 21 is turned on, and the potentials of the bit lines BL and XBL are both VDD. -It becomes VthN. Next, the bit line load control signal LD becomes "L", the bit line load circuit 21 is turned off, the column gate selection signal CG is "H", the column gate 23 is turned on, and the potentials of the data buses DB and XDB and the bit line BL, The potential of XBL is equalized. At this time, the potentials of the bit lines become VDD-VthN and 0V, respectively. Next, when the word line selection signal WL is "H", the data transfer gate 22 is turned on and the potentials of the bit lines BL and XBL are transferred to the drains MC and XMC of the NMOS elements 153 and 154 of the data storage circuit. At this time, the potentials of MC and XMC become VDD-VthN-VthM and 0V.

[0006]

In order to hold this potential in the data storage circuit, the NMOS element 153,
The threshold voltage VthM of 154 must have the following relationship.

VthM <VDD-VthN-VthM That is, the operation lower limit power supply potential capable of holding data in this data storage circuit is VthN + 2 × VthM or more. If VthN = 0.90V and VthM = 1.00V, the operation lower limit power supply potential becomes 2.90V or higher. Further, in reality, the influence of the back gate effect is also added, so that it becomes even higher. Power supply potential of 3.0V ± as market needs
While the operation at 10% is required, this operation lower limit power supply potential cannot be applied.

The present invention aims to improve the above points and provide a semiconductor memory device capable of guaranteeing operation at a low voltage.

[0009]

A semiconductor memory device of the present invention includes a pair of bits composed of a pair of bit lines and an N channel MOS type FET (hereinafter abbreviated as NMOS) connected to the bit lines. A line load circuit, a pair of column gates composed of an NMOS connected between the bit line and a pair of data buses, and an NMOS connected between the bit line and a data storage circuit 1 composed of a pair of data transfer gates, a pair of write gates composed of an NMOS connected between the data bus and a pair of data write buses, and 1 composed of an NMOS connected to the data bus
In a semiconductor memory device including a pair of data bus load circuits, the bit line load circuit, the column gate, the data transfer gate, the write gate, and the NMOS threshold voltage of the data bus load circuit are set to other NMOSs. It is characterized in that it is lower than the threshold voltage of.

[0010]

Embodiments of the present invention will be described with reference to FIGS. In FIG. 1, description of the symbols common to FIG. 2 is omitted. Reference numeral 11 in FIG. 1 denotes a pair of bit line load circuits "having a threshold voltage lower than that of other NMOS" (hereinafter abbreviated as "lowered Vth") 11 in the NMOS configuration, and 21 in FIG. Will be replaced. 12 is a low Vt of NMOS configuration
A pair of data transfer gates that are converted into h replaces 22 in FIG. Reference numeral 13 denotes a pair of column gates having a low Vth and having an NMOS structure, which replaces 23 in FIG. Reference numeral 14 denotes a pair of write gates having a low Vth and having an NMOS structure.
Will be replaced. 17 is an NMOS structure having a low Vth 1
The pair of data bus load circuits replaces 27 in FIG. 1
The threshold voltages of 1, 12, 13, 14, 17 are set lower by ΔVth than the corresponding threshold voltages of 21, 22, 23, 24, 27 in FIG. That is 11, 13,
The threshold voltage of 14 and 17 is VthN-ΔVth, 12
Has a threshold voltage of VthM-ΔVth. Low V
N to form a normal NMOS channel
After the channel doping step, a mask for the channel portion of the NMOS for lowering Vth is created, and the channel doping step is performed again to form the mask.

The operation of writing data in the data storage circuit and the data potential to be propagated in the semiconductor memory device having the above configuration will be described with reference to FIG.

The NMOS device having a reduced Vth has a threshold voltage (Vth) when a potential is transmitted from the source to the drain.
The potential for N-ΔVth) decreases. That is, when the power supply potential VDD is applied to the source side, VDD is applied to the drain side.
The potential becomes −VthN + ΔVth. In the following description, the threshold potentials of the bit line load circuit 11, the column gate 13, and the write gate 14 are VthN-ΔVth, and the threshold potential of the data transfer gate 12 is VthM-ΔVth, N.
The threshold voltage of the MOS elements 153 and 154 is set to VthM, and the back gate effect and the like are ignored.

VDD and 0V are applied from the input / output circuit 16 to the data write bus pair WB and XWB, respectively. The potentials of the data buses DB and XDB are the data bus load circuit 17
Is always on, VDD-VthN + ΔVt
It is kept at h. The data write control signal WG is "
When it becomes "H", the write gate 14 is turned on and the potentials of the data write buses WB and XWB are set to the data buses DB and X.
It is transmitted to the DB. At this time, the potential of the data bus becomes VDD-VthN + ΔVth and 0V, respectively. While the column gate selection signal CG is "L", the bit line load control signal L
D becomes "H", the bit line load circuit 11 is turned on, and the potentials of the bit lines BL and XBL are both VDD-VthN +.
It becomes ΔVth. Next, the bit line load control signal LD is "
The bit line load circuit 11 is turned off, the column gate selection signal CG is turned "H", the column gate 13 is turned on, and the potentials of the data buses DB and XDB and the bit lines BL and XB are turned on.
The potential of L is equalized. At this time, the potentials of the bit lines become VDD-VthN + ΔVth and 0V, respectively. Next, when the word line selection signal WL is "H", the data transfer gate 1
2 is turned on, and the potentials of the bit lines BL and XBL become the drains MC of the NMOS elements 153 and 154 of the data storage circuit.
It is transmitted to XMC. At this time, the potential of MC and XMC is VD
D-VthN-VthM + 2 × ΔVth, which is 0V.

[0014]

As compared with the conventional example, the potential held in the node MC of the data storage circuit is written higher by 2 × ΔVth. That is, the operation lower limit power supply potential that can hold data in this data storage circuit is VthN + 2 × Vt.
hM-2 × ΔVth, which is 2 × ΔVth more than the conventional example.
Operation can be guaranteed up to a low power supply potential. Here, it is assumed that Vth = 0.90V, VthM = 1.00V, and ΔVt.
When h = 0.30V, the operation lower limit potential becomes 2.30V or higher. As a result, the power supply potential of the market needs 3.0V ±
It is possible to supply a semiconductor memory device that can sufficiently guarantee 10%.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional embodiment.

FIG. 3 is a waveform diagram for explaining the operation of FIG.

FIG. 4 is a waveform diagram for explaining the operation of FIG.

[Explanation of symbols]

 11 Bit line load circuit with low Vth 12 Data transfer gate with low Vth 13 Column gate with low Vth 14 Write gate with low Vth 15 Data storage circuit 151, 152 High resistance load element 153, 154 NMOS element 16 Input / output Circuit 17 Low Vth data bus load circuit 21 Bit line load circuit 22 Data transfer gate 23 Column gate 24 Write gate 27 Data bus load circuit MC, XMC Data storage circuit terminal BL, XBL Bit line DB, XDB Data bus WB, XWB Data write bus LD Bit line load control signal WL Word line selection signal CG Column gate selection signal WG Data write control signal

Claims (1)

[Claims] 1. A pair of bit lines and an N-channel MOS type FET (hereinafter abbreviated as NMOS) connected to the bit lines.
A pair of bit line load circuits, a pair of column gates composed of NMOS connected between the bit lines and the pair of data buses, and a pair of bit line load circuits between the bit lines and the data storage circuit. Connected to the data bus is a pair of data transfer gates made up of NMOSs, a pair of write gates made up of NMOSs connected between the data bus and a pair of data write buses. In a semiconductor memory device including a pair of data bus load circuits configured by NMOSs, the bit line load circuit, the column gate, the data transfer gate, the write gate, and the NMOS of the data bus load circuit. Threshold voltage for other NMOS
A semiconductor memory device characterized by being made lower than the threshold voltage of.