JP2525728B2 - Semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using complementary MOS transistors.

[0002]

2. Description of the Related Art FIG. 1 shows an example of a potential equalization / precharge circuit for a bit line pair of a conventional semiconductor memory device, and FIG. 2 shows a potential change of the bit line pair when this circuit operates.

Reference numeral 1 denotes a memory cell, which has T11, T12,
T13 is an N-channel MOS (hereinafter referred to as NMOS) transistor, P is a precharge signal line, and W
Is a word line, B is a bit line, and bar B is a bit line complementary to B. The gate electrodes of T11, T12, and T13 are commonly connected to P, and the memory cell is
Connected to B and bar B and W, T12 and T13
Drain electrode of T1I and T12 connected to the power supply
The source electrode of T13 is connected to B, and the source electrode of T13 and T
Eleven drain electrodes are connected to bar B.

[0004]

The operation of the conventional circuit will be described. The precharge signal line P is set to a high level potential in the state where the memory cell is in the non-selected state by the word line signal and the information in the memory cell is not output to B and bar B. In this state, the NMOS transistors T12 and T13 are turned on, and the potential levels of B and B are converged to the potentials that have dropped from the power supply voltage by the threshold voltages of T12 and T13. At the same time, T11 of the NMOS transistor is also in the ON state, and the source and the drain are in a conductive state, and B and B have the same potential by this T11. In the circuit as described above, since T11 which makes B and bar B the same potential is composed of an NMOS transistor, as B and bar B approach the convergence potential of precharge, the on resistance of T11 increases and the same potential. It is hard to become. As a result, it becomes difficult for B and bar B to have the same potential as the precharge potential level approaches the convergence level, and there is a disadvantage that much time is spent until reaching the precharge convergence potential level. .

Further, in the case where T11 is a P-channel type MOS (hereinafter referred to as PMOS) transistor which constitutes a precharge circuit, B and bar B are connected to B and bar when T11 is turned on at the start of precharge. Since either B is at a low level potential, the on resistance of T11 of the PMOS transistor is high and it is difficult for the PMOS transistor T11 to have the same potential. As a result, when precharge is started from a state where a sufficient potential difference is present between B and bar B, it is difficult for the potentials of both B and bar B to become equal until the potential levels of both are sufficiently increased.
The drawback is that much time is spent before reaching the precharge convergent potential level.

The present invention solves the above drawbacks, and an object of the present invention is to provide complementary signal line pairs when the signal line pairs of complementary signal line pairs are made to have the same potential in a semiconductor memory device. The purpose is to reduce the time required to bring them to the same potential.

[0007]

SUMMARY OF THE INVENTION According to the present invention, memory cells arranged in a matrix, word lines for selecting the memory cells, and complementary information to which information of the memory cells selected by the word lines is propagated. In a semiconductor memory device including a pair of signal lines having a similar relationship, a charge means is connected to each of the signal lines, and a one conductivity type transistor and a reverse conductivity type transistor are connected between the signal line pairs, In order to make the pair have the same potential, the one conductivity type transistor and the opposite conductivity type transistor are electrically connected.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor memory device of the present invention, word lines arranged in a matrix extending in a row direction and signal line pairs connected to the memory cells and extending in a column direction in a complementary relationship. In the semiconductor memory device, the drain electrode of the first NMOS transistor, the source electrode of the second NMOS transistor, and the source electrode of the first PMOS transistor are connected to the first signal line of the signal line pair, The source electrode of the first NMOS transistor, the drain electrode of the second NMOS transistor, and the drain electrode of the first PMOS transistor are connected to the second signal line of the signal line pair, and the second and third NMOS transistors are connected. The drain electrode of the transistor is connected to a power source, and the first and second
A timing signal line is connected to the gate electrode of the third NMOS transistor, and a gate electrode of the first PMOS transistor is connected to a timing signal line complementary to the timing signal line.

The present invention will be described in detail below based on examples. FIG. 3 shows a potential equalization / precharge circuit for a bit line pair according to an embodiment of the present invention, and FIG. 4 shows a potential change of the bit line pair when the precharge circuit operates. T2
1, T22, T23 are NMOS transistors,
24 is a P-channel type MOS transistor, T21
And a complementary MOS transistor of T24 form a transmission gate, the drain electrodes of T22 and T23 are connected to a power source, and the drain electrode of T21 and T22
And the source electrodes of T24 are connected to B, and the source electrodes of T21 and T22 and the drain electrode of T24 are bar B.
It is connected to the. P is a precharge signal line, and bar P is a precharge signal line having a syntactic relationship with P. The signal line of P is commonly connected to the gate electrodes of T21, T22, and T23, and the bar of P is connected to the gate electrode of T24. The signal line of is connected.

The operation of the circuit according to the embodiment of the present invention will be described.
When the memory cell is in the non-selected state by the word line signal,
When the precharge signal line P is set to a high level potential in a state where the information in the memory cell is not output to B and B, T22 and T23 are turned on, and B and B are set to T22 and T23 from the power supply voltage. It converges to the potential dropped by the value voltage. At the same time, T21 is turned on and T
24 is also turned on by the signal line of bar P. In the circuit as described above, since the circuit for setting B and bar B to the same potential is the transmission gate composed of NMOS and PMOS transistors, when either B or bar B at the precharge start is at the low level potential. ,
When the NMOS transistor of the transmission gate has a low on-resistance and works to make the bit line pair have the same potential, the precharge progresses and the potential level of the bit line pair rises.
The on-resistance of the MOS transistor is lowered, which works to bring the bit line pair to the same potential, and the potential level of the precharge is quickly brought to the same potential level.

Although the embodiment of the present invention has been described using the bit line pair, the present invention is not limited to this, and can be similarly applied to the precharge circuit of the data line pair and the sense amplifier circuit input / output line pair. it can.

[0012]

As described above, according to the present invention, in order to make the pair of signal lines in a complementary relationship pulled up by the charging means have the same potential by the transmission gate composed of the complementary MOS transistor, The potential level of the signal line pair can be set to the same potential faster than in the same potentializing circuit using only NMOS or PMOS transistors, and the time required for equalizing the potential can be shortened.

In the semiconductor memory device, high-speed operation is required, and it is important to shorten the access time which is a data read time. Reducing the time for equalizing the potential has the effect that the access time can be shortened as it is.

[Brief description of drawings]

FIG. 1 is a diagram showing a conventional britage circuit of a pair of bit lines.

FIG. 2 is a diagram showing a potential change of a bit line pair by a conventional british circuit.

FIG. 3 is a diagram showing a bridging circuit for a bit line pair according to an embodiment of the present invention.

FIG. 4 is a diagram showing a potential change of a bit line pair by the precharge circuit of the present invention.

[Explanation of symbols]

TI1, T12, T13, T21, T22, T23 ...
.... N channel type MOS transistor, T24 ... P channel type MOS transistor 1 ... memory cell, W ... word line, B, bar B ... bit line, P, Bar P ... Precharge signal line

Claims (1)

(57) [Claims] 1. Memory cells arranged in a matrix,
In a semiconductor memory device comprising a word line for selecting the memory cell and a signal line pair having a complementary relationship for transmitting information of the memory cell selected by the word line,
In order to connect the charging means to each of the signal lines, and to connect a transistor of one conductivity type and a transistor of opposite conductivity type between the pair of signal lines to make the pair of signal lines have the same potential,
A semiconductor memory device characterized in that the one conductivity type transistor and the opposite conductivity type transistor are electrically connected.