JP2738793B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static RAM.
And a semiconductor memory device exclusively for reading and writing.

[0002]

2. Description of the Related Art FIG . 2 is a circuit diagram showing a configuration of a conventional semiconductor memory device. In FIG. 2 , reference numeral 10 denotes a precharge terminal, reference numerals 20 and 30 denote precharge transistors formed of p-channel MOS transistors, reference numeral 40 denotes a row decoder, reference numeral 50 denotes a word line, reference numeral 60 denotes a memory cell, and reference numerals 70 and 80 comprise n-channel MOS transistors. Switching transistor, 90 is a flip-flop circuit, 100,
110 is a bit line.

The operation of the conventional semiconductor memory device configured as described above will be described. First, before reading data from the memory cell 60, a low voltage is applied to the precharge terminal 10 to turn on the precharge transistors 20, 30, so that the two bit lines 100, 110 are set to a high potential. Is set. Next, the word line 50 of the memory cell 60 from which data is read is set to a high potential, that is, an active state by the row decoder 40, and the switching transistors 70 and 80 in the memory cell 60 are turned on.
The flip-flop circuit 90 is connected to the bit lines 100 and 110, and the data stored in the flip-flop circuit 90 is read out to the bit lines 100 and 110.

[0004]

However, in the conventional semiconductor memory device configured as described above, immediately after the power is turned on, the data of all the memory cells 60 is indefinite. Therefore, there is a problem that data must be written in all the memory cells 60.

An object of the present invention is to provide a semiconductor memory device which does not require data writing by software immediately after power-on in view of the above problems.

[0006]

In a semiconductor memory device according to the present invention, a precharge terminal and a reset terminal are connected to an input terminal.
Connected NOR circuit and the gate via the first inverting circuit
Connect to the precharge terminal, connect the source to the power supply,
A precharge transistor with a rain connected to the first bit line
Connect the transistor and the gate to the output terminal of the NOR circuit.
Source to power supply and drain to second bit line
Precharge / reset dual-use transistor
To the reset terminal, ground the source, and
Transistor connected to the first bit line
And one input to the precharge terminal via the first inverting circuit
A row decoder connected to one end and a reset terminal are connected to a second counter.
Connected to one input terminal via a
Connect the output terminal to the other input terminal and the output terminal to the word line.
And a continuous NAND circuit.

[0007]

According to the structure of the present invention, immediately after the power is turned on, the reset is performed.
Set terminal to high potential and precharge terminal to low potential
By doing so, the precharge transistor is turned off,
Precharge / reset transistor and reset
And the first bit line is turned on.
The low potential and the second bit line have a high potential. Also Roude
Set reset terminal to high potential regardless of coder output
As a result, the output of the NAND circuit becomes high potential,
Is selected (becomes high potential). Therefore, the first
Bit line has a low potential, the second bit line has a high potential,
Since all word lines are selected , data can be written to all memory cells.

[0008]

DETAILED DESCRIPTION FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device of the real施例of the present invention. In FIG. 1, 1 is a precharge terminal, 2 is a precharge transistor composed of a p-channel MOS transistor, and 3a is a p-channel transistor.
Precharge / Reset of MOS transistor
Use transistor, a reset terminal, the reset transistor 5 is made of a p-channel MOS transistor 4,
7 is a row decoder for selecting an address, 8 is a word line,
9 is a memory cell, 13 is a first bit line, 14 is a second bit line, 21 is a NAND circuit, 22 is a NOR circuit, 2
3 is an inverter which is a first inverting circuit, and 24 is a second inverter.
It is an inverter that is a conversion circuit .

[0009] As shown in FIG. 1, by connecting a plurality of memory cells 9 between the first and second bit lines 13 and 14, are connected to word line 8 for each memory cell 9. A precharge transformer is provided between the power supply and the first bit line 13.
Register 2 and interposed and a power source, a drain first
Is connected to the bit line 13. Power supply and second bit
Transistor for both precharge and reset between lines
The source is a power source and the drain is a second
Connected to bit line 14.

The precharge terminal 1 is connected to the NOR circuit 22
It is connected to one input terminal and to the gate of the precharge transistor 2 via an inverter 23 . The reset terminal 4 is connected to the other input of the NOR circuit 22.
Connected to the gate of the reset transistor 5, and further connected to the NAND through an inverter 24.
It is connected to one input terminal of the circuit 21 . NOR circuit 2
Pre-charge / reset dual-use output terminal 2
It is connected to the gate of 3a.

The resetting transistor 5 has a drain connected to the first bit line 13 and a source grounded. The NAND circuit 21 has the other input terminal connected to the output terminal of the row decoder 7 and the output terminal connected to the word line 8 . Hereinafter, the semiconductor memory device thus configured
The operation of the device will be described.

After the power is turned on, a reset signal is input to the reset terminal 4 to set the reset terminal 4 to a high potential and the precharge terminal 1 to a low potential. By setting the precharge terminal 1 to a low potential, the precharge transistor 2 is turned off. Also, reset terminal 4
Is high potential, the output of the NAND circuit 21 becomes high potential regardless of the output of the row decoder 7, and all the word lines 8 are selected. Further, by setting the reset terminal 4 to a high potential, the reset transistor 5 is turned on, and the precharge / reset dual-purpose transistor 3a is turned on. As a result, the first bit line 13 has a low potential and the second bit line 14 has a high potential.

As described above, the reset signal is supplied to the reset terminal 4
, All word lines 8 are set to a high potential, that is, an active state, the first bit line 13 is set to a low potential, and the second bit line 14 is set to a high potential.
Data can be written to all memory cells 9 .

By setting the reset terminal 4 at a low potential, a desired word line 8 can be selected by the row decoder 7, and the precharge transistor 2 and the precharge Both of the reset / shared transistors 3a can be turned on / off. As described above , according to this embodiment, immediately after the power is turned on, the reset signal is input to reset the reset terminal 4.
High potential and pre-charge terminal 1 low
The precharge transistor 2 is in the off state,
Charge / Reset Transistor 3a and Reset
Transistor 5 is turned on, and the first bit line 1
3 has a low potential and the second bit line 14 has a high potential. Ma
Further, regardless of the output of the row decoder 7, the reset terminal 4
To a high potential, the output of all NAND circuits 21
The force becomes high potential, and all word lines 8 are selected (high
Potential). Therefore, the first bit line 13 is
And the second bit line 14 becomes high potential, and all the words
Since the line 8 is selected, data can be written to all the memory cells 9 .

As a result, the data of all the memory cells 9 can be determined by hardware immediately after the power is turned on, and it is not necessary to write the data to all the memory cells 9 by software as in the related art. According to this embodiment, the precharge / reset dual-purpose transistor 3a having the output of the NOR circuit 22 as a gate input is connected to the precharge / reset transistor 3a .
Transistor and reset transistor
Therefore, the number of transistors connected to the second bit line 14 can be reduced.

[0016]

Effects of the Invention] According to the semiconductor memory device of the present invention, electrostatic
Immediately after turning on the power, set the reset terminal to high potential and
By setting the charge terminal to low potential, the precharge
The star is off, and the precharge / reset
The reset and reset transistors are turned on,
The first bit line has a low potential and the second bit line has a high potential.
You. Furthermore, regardless of the output of the row decoder, reset
By setting the terminal to high potential, the output of the NAND circuit becomes high potential.
And all the word lines are selected, so that data can be written to all the memory cells.

As a result, the data of all the memory cells can be determined by hardware immediately after the power is turned on, and it becomes unnecessary to write the data to all the memory cells by software immediately after the power is turned on, unlike the related art. . NO
Precharge / Reset using the output of R circuit as gate input
The dual-purpose transistors are precharge transistors and
It also serves as a reset transistor.
Can reduce the number of transistors connected to each bit line.
it can.

[Brief description of the drawings]

1 is a circuit diagram showing a configuration of a semiconductor memory device of the real施例of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional semiconductor memory device.
You.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 precharge terminal 2 precharge transistor 3 a precharge / reset transistor 4 reset terminal 5 reset transistor 7 row decoder 8 word line 9 memory cell 13 first bit line 14 second bit line 21 NAND circuit 22 NOR circuit 23 Inverter (first inversion circuit) 24 Inverter (second inversion circuit)

Claims (1)

(57) [Claims] 1. A semiconductor memory device in which a plurality of memory cells are connected to first and second bit lines, and a word line is connected to each memory cell, wherein a precharge terminal and a reset terminal are connected to an input terminal. Connected to
A NOR circuit, and a gate connected to the precharge terminal via a first inverting circuit.
, The source is connected to the power supply, and the drain is connected to the first
A precharging transistor connected to the bit line of the NOR circuit , a gate connected to the output terminal of the NOR circuit, and a source connected to the
Source and the drain was connected to the second bit line
A precharge / reset combined transistor, a gate connected to the reset terminal, a source grounded,
A reset transistor having a drain connected to the first bit line;
A transistor and the precharge terminal are connected via the first inverting circuit.
A row decoder connected to an input terminal and the reset terminal connected to one input terminal via a second inverting circuit;
And the output terminal of the row decoder is connected to the other input terminal.
And a NAND circuit having an output terminal connected to the word line.
A semiconductor memory device provided with a path .