JPH09251793A - Semiconductor storage device and data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an access time of a semiconductor storage device. SOLUTION: In a semiconductor storage device having a delay circuit (UD1) for generating a timing signal, an inverter V50 is constituted with a first transistor P11 coupled to a high potential side power source Vdd, a second transistor N13 coupled to a lower potential side power source, a depletion type transistor N12 arranged between the first transistor and the second transistor. Surplus timing margin is reduced and a memory access time is shortened by coordinating voltage dependency of a delay circuit with voltage dependency of a word line driving system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
Further, the present invention relates to a read-only ROM (read only memory) used as a program memory or the like, and relates to a technique effectively applied to, for example, a data processing device.

[0002]

2. Description of the Related Art In a mask ROM, data is written in a wafer process. This data writing method,
That is, the mask ROM programming method includes a diffusion layer programming method in which a logical value "1" or "0" of data is defined depending on the presence or absence of a diffusion layer of a memory cell transistor (presence or absence of a memory transistor), and a memory cell by channel ion implantation There is an ion implantation programming method in which data is programmed by changing the threshold voltage of the transistor. Mask R
There are a NOR type, a NAND type, and the like regarding the memory arrangement of the OM. The NOR type ROM is sometimes called a lateral ROM, and has a configuration in which word lines and bit lines are arranged in the X and Y directions, and memory cells are arranged in a matrix at intersections of the word lines and the bit lines. The word line to be selected is set to the selection level of the memory cell, and the word line to be deselected by the address signal is set to the non-selection level of the memory cell, so that the selection terminal is coupled to the word line. Storage information is read depending on whether or not a current flows through the bit line through the memory cell. NAND type R
The OM is also called a vertical ROM, and one end of a series connection circuit of a plurality of memory cells is coupled to a bit line, and a word line to be selected by an address signal is set to a non-selection level of the memory cell, The word line that should not be selected by the signal is set to the selection level of the memory cell,
The stored information is read depending on whether or not a direct current path is formed in the series connection circuit.

As an example of the document describing the mask ROM, "Ultra High Speed MOS Device", pages 316 to 3 issued by Baifukan Co., Ltd. on February 10, 1986.
There are 18 pages.

[0004]

In a semiconductor memory device such as a mask ROM, a wiring material having a relatively high resistance is used for a word line. Therefore, the signal delay at the far end of the word line is larger than that at the near end thereof. This is mainly due to the wiring load of the word line, and it is difficult to drive the word line at high speed even if the driving capability of the transistor that drives the wiring is increased. This means that voltage dependency is low in driving the word line of the mask ROM.

In the mask ROM, the transition of the address signal is detected, and the detection signal is delayed by the delay circuit to generate the operation control signal of the data read system such as the sense amplifier. Since the voltage dependency in the word line driving is different from each other, the signal delay time in the delay circuit is set to be sufficiently long in order to guarantee stable operation within the allowable range of fluctuation of the power supply voltage. . In other words, even if the power supply voltage becomes high and the delay time of the delay circuit becomes short, equalization of the common data line and the amplification timing of the memory cell data in the sense amplifier are not undesirably shifted. It is necessary to set a sufficient margin for the operation timing of. However, this also hinders the reduction of the memory access time. By shortening the word line sufficiently to reduce the signal delay between the near end and far end of the word line, the operation timing of the data read system can be accelerated, and the access time can be shortened accordingly. However, then, to secure the same storage capacity, the number of word lines increases,
Correspondingly, the scale of the decoder for decoding the row address signal increases, the semiconductor chip size increases,
This is not preferable because it causes an increase in manufacturing cost.

An object of the present invention is to shorten the access time of a semiconductor memory device. Another object is to provide a data processing device equipped with such a semiconductor memory device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, when the semiconductor memory device is formed with the delay circuit for generating the operation timing signal of the data read system (15), the first transistor (P11) coupled to the high potential side power source, An inverter (V50) including a second transistor (N13) coupled to the low-potential-side power supply and a depletion type transistor (N13) interposed between the first transistor and the second transistor, It is applied to the above delay circuit. The depletion type transistor acts to reduce the voltage dependence of the logic threshold of the inverter. This brings the voltage dependence of the delay circuit close to the voltage dependence of the word line drive, and makes it possible to optimize the delay time in the delay circuit by reducing the unnecessary margin.

At this time, the delay circuit includes a time constant circuit (C, R) formed by coupling a capacitor (C) and a resistor (R), and the inverter (V50) for inverting the output signal of the time constant circuit. And can be configured. In addition, the semiconductor memory device (3
4) and a central processing unit (31) accessible to it, a data processing unit can be formed.

[0011]

FIG. 5 shows an embodiment of a data processing device according to the present invention.

This data processing device includes a CPU (central processing unit) 31 and an SDRAM (synchronous dynamic random access memory) via a bus BUS.
32, SRAM (static random access
Memory) 33, ROM (Read Only Memory) 3
4, the peripheral device control unit 35, the display system 36, and the like are connected to each other so that signals can be exchanged therebetween, and are configured as a computer system that performs predetermined data processing according to a predetermined program. The CPU 31 is a logical core of the present system, and mainly includes address designation, information reading and writing, data operation, instruction sequence, acceptance of interrupt, activation of information exchange between a storage device and an input / output device, and the like. And has an arithmetic control unit, a bus control unit, a memory access control unit, and the like. SDRAM 32, S
The RAM 33 and the ROM 34 are positioned as internal storage devices. The SRAM 33 is used as a main memory, and the ROM 34 is used as a read-only program memory. SDRAM32 and SRAM33,
Programs and data required for calculation and control by the CPU 30 are loaded. The peripheral device control unit 35 controls the operation of the external storage device 38 and the input of information from the keyboard 39 and the like. Further, by the display system 36,
Information display control on the CRT display 40 is performed.

FIG. 6 shows an example of the structure of the ROM 34, and FIG. 8 shows the operation timing in the read mode.

The ROM 34 shown in FIG. 6 is not particularly limited, but may be manufactured by a known semiconductor integrated circuit manufacturing technique.
It is formed on one semiconductor substrate such as single crystal silicon.

The ROM 34 is a mask ROM, and data is written in the wafer process. Although not particularly limited, the mask ROM programming method is an ion implantation programming method in which the threshold voltage of the memory cell transistor is changed by channel ion implantation to program data.

The ROM 34 shown in FIG. 6 is not particularly limited, but a memory array cell 11 formed by arranging a plurality of memory cells, and an X connected to the memory cell array 11.
Address decoder 13 (XD) and Y switch (YS)
16, and a timing generation circuit (T) for generating various internal control signals based on a signal given from the outside.
G) 10, X for decoding an X address signal from the outside
Address decoder 12, Y address decoder (YD) 17 for decoding Y address signal from the outside, Y
A Y switch (YS) 16 for selectively coupling the bit line of the memory cell array 34 to the common data line based on the output signal of the address decoder 17, and a sense amplifier (SA) for amplifying the signal of this common data line. 15,
It is formed by a combination of various functional blocks such as a data output buffer (OB) 14 for externally outputting the amplified signal and an address transition circuit (ATD) 19 for detecting an address change.

The timing generation circuit 10 includes a chip enable signal CE * (* means low active or signal inversion) and an output enable signal O from the outside.
E * and the address transition detection signal ATDS from the address transition circuit 19 are input, and based on that, internal control signals CE0, CE1, OE, EQ *, SAC, SL *, D
OC is generated. The detailed configuration thereof will be described later.

As shown in FIG. 7, memory cell array 11 includes a plurality of word lines, a plurality of bit lines arranged so as to intersect therewith, and a large number of memory cells MC. In this embodiment, the memory cell forming the memory cell array has n channels which selectively retain the storage data of the logical value "1" or the logical value "0" by selectively implanting impurities into the channel. Type MOS transistor. Although not particularly limited, the memory cell array 11 is a NAND (nand) type,
The memory cells arranged in the same column are arranged in series every predetermined number between the corresponding bit line and the ground potential (low-potential-side power supply Vss) of the circuit.

The plurality of word lines WL forming the memory cell array 34 include an X address decoder 1 for decoding the internal X address signals X0 to Xi having an i + 1 bit structure.
3 and are selectively set to the selected state based on the decode output signal of the X address decoder 13. The X address buffer 12 is arranged in the preceding stage of the X address decoder 13, and the address signals AX0 to AXi are applied to the X address buffer 12 via the address input terminals, whereby the internal address signals X0 to Xi are transferred to the X address decoder. 13 is output. The internal control signal CE1 output from the timing generation circuit 10 is input to the memory cell array 11. The internal control signal CE1 is asserted to a high level at a predetermined timing when a chip enable signal CE * given from an external terminal to bring the ROM 34 into a selected state is asserted to a low level.

As shown in FIG. 8, when the chip enable signal CE *, which is the activation control signal, is asserted to the low level, the ROM 34 is brought into the selected state. The output enable signal OE * is set to the low level prior to the change of the chip enable signal CE * to the low level. Further, the X address signal AX is applied to the address input terminal.
0 to AXi are supplied in a combination designating the row address XA, and Y address signals AY0 to AYj are supplied to the address input terminals AY0 to AYj in a combination designating the column address YA. Y address signals AY0 to AY
j is changed to a combination designating the column address YB when a predetermined time further elapses. The X address buffer (XB) 12 outputs the X address signals AX0 to AXi supplied via the address input terminals AX0 to AXi when the ROM 34 is in the selected state, to the internal control signal CE.
In accordance with 1, the internal address signals X0 to Xi are formed based on these X address signals and transmitted to the X address decoder 13. X address decoder 1
Reference numeral 3 decodes the internal address signals X0 to Xi to drive the corresponding one word line of the memory cell array 11 to the selection level. The internal address signals X0 to Xi formed by the X address buffer 12 are also transmitted to the address transition detection circuit 19.

The bit lines forming the memory cell array 11 are coupled to the Y switch 16, and 16 bits are selectively connected to the common data lines CD0 to CDF via the Y switch 16.
(The number of signal lines exceeding 10 is displayed in hexadecimal. The same applies to the following). The Y switch 16 is supplied with a bit line selection signal of a predetermined bit from the Y address decoder (YD) 17, and the Y switch 16 is supplied with a bit line selection signal of a predetermined bit from the Y address decoder 17. The address buffer (YB) 18 supplies j + 1-bit internal address signals Y0 to Yj. Further, the Y address buffer 18 is supplied with the Y address signals AY0 to AYj via the address input terminal and the internal control signal CE1 from the timing generation circuit (TG) 10.

When the ROM 34 is in the selected state, the Y address buffer 18 takes in the Y address signals AY0 to AYj supplied through the address input terminals in accordance with the internal control signal CE1, and internally based on these Y address signals. The address signals Y0 to Yj are formed and supplied to the Y address decoder 17. In addition, the Y address decoder 1
Reference numeral 7 decodes the internal address signals Y0 to Yj and selectively sets the corresponding bit line selection signal to the high level.
The internal address signals Y0 to Yj are also supplied to the address transition detection circuit 19.

Y switch 16 includes a plurality of switch MOS transistors provided corresponding to each bit of memory cell array 11, as shown representatively in FIG.
One of these switch MOS transistors is coupled to the corresponding bit line BL of the memory cell array 11,
For the other ones, the common data lines CD0 to CD every 16th
Commonly connected to F. Further, the gates of the respective switch MOS transistors are sequentially connected in common to each other by 16 pieces, and the corresponding bit line selection signals are set to the high level, whereby 16 pieces are selectively turned on, and the corresponding 16 pieces of the memory cell array 11 are formed. Bit lines and common data lines CD0-CD
F and F are selectively connected. Although not particularly limited, the memory cell array 11 includes 16 dummy bit lines to which predetermined dummy cells are coupled, and these dummy bit lines are selectively connected via the Y switch 16 to the dummy common data lines DD0 to DD0. It is connected to the DDF.

The address transition detection circuit 19 is supplied with the internal address signals X0 to Xi from the X address buffer 12 and the Y address buffer 18, and the internal control signal CE0 from the timing generation circuit 10.
The internal control signal CE0 is set to the selection level in response to the low level change of the chip enable signal CE *, as shown in FIG.

The address transition detection circuit 19 has an internal control signal CE0, that is, a chip enable signal CE *, and internal address signals X0 to Xi, that is, an X address signal AX0.
.About.AXi and internal address signals Y0 to Yj are monitored for level changes, and when the logical level of any of the bits is inverted, the output signal, that is, the address transition detection signal ATDS is temporarily set to the high level for a predetermined time. .
Therefore, in the case of FIG. 8, the address transition detection signal ATDS
Is temporarily set to a high level in response to a low level change of the chip enable signal CE *, that is, a high level change of the internal control signal CE0.
When Y0 to AYj are changed to the combination designating the column address YB, they are temporarily set to the high level.
The address transition detection signal ATDS output from the address transition detection circuit 19 is supplied to the timing generation circuit 10.

A common data line C to which 16 designated bit lines of the memory cell array 11 are selectively connected.
D0 to CDF are coupled to one input terminal of the corresponding unit circuit of the sense amplifier 15. In addition, 16 dummy bits of the memory cell array 11 are coupled to the dummy common data lines DD0 to DDF which are selectively connected and the corresponding other input terminals of the sense amplifier 15.
The sense amplifier 15 is supplied with the inverted internal control signals EQ * and SL * and the internal control signal SAC from the timing generation circuit 10. The inverted internal control signal EQ * is set to the low level for a predetermined time in response to the rising edge of the address transition detection signal ATDS output from the address transition detection circuit 19, as shown in FIG. In addition, the internal control signal SA
C is temporarily set to high level after the inverted internal control signal EQ * is returned to high level. Further, the internal control signal SL * is set to low level at the same time when the inverted internal control signal SAC is set to high level, and the internal control signal SAC is set to low level.
Is returned to high level before is returned to low level.

The sense amplifier 15 has a common data line CD0.
To CDF and 16 unit circuits provided corresponding to the dummy common data lines DD0 to DDF, each of these unit circuits is a so-called current mirror type differential amplifier circuit and non-inverting of each differential amplifier circuit. And an equalizing MOS transistor provided between the inverting input terminals and an output latch for receiving an output signal of each differential amplifier circuit. Of these, each equalizing MOS transistor is selectively turned on in response to the low level of the inverted internal control signal EQ *, and equalizes the non-inverting and inverting input nodes of the corresponding differential amplifier circuit to a predetermined level. In addition, each differential amplifier circuit is selectively operated in response to the high level of the internal control signal SAC, and the corresponding common data line CD0 is selected from the 16 selected memory cells of the memory cell array 11.
˜CDF, the read signal output is amplified while being compared with the refinement signal transmitted via the corresponding dummy common data lines DD0 to DDF. Furthermore, each output latch takes in the output signal of the corresponding differential amplifier circuit when the inverted internal control signal SL * is at the low level, and holds it while the inverted internal control signal SL * is at the high level. .

The output signals of the output latches of the unit circuits of the sense amplifier 15 are supplied to the corresponding unit data output buffers UOB0 to UOBF of the data output buffer 14 as internal output signals SO0 to SOF, respectively. The internal control signals OE and DOC are also commonly supplied from the timing generation circuit 10 to each unit circuit of the data output buffer 14. The internal control signal OE is selectively set to high level by setting the chip enable signal CE * and the output enable signal OE * to low level as shown in FIG. In addition, the internal control signal DOC
Is returned to the low level when the inverted internal control signal SL * is returned to the high level and then returned to the high level in response to the rise of the address transition detection signal ATDS, or when the ROM 34 is in the non-selected state. .

The data output buffer 14 has data D0 to D0.
16 unit circuits are provided corresponding to the data output terminals for outputting the DF to the outside. Internal control signals OE and DOC are commonly supplied from the timing generation circuit 10 to these unit circuits, and the sense amplifier 15
To the output signals of the corresponding unit circuits, that is, the internal output signals SO0 to SOF, respectively. The output terminal of each unit circuit of the data output buffer 14 is coupled to the corresponding data output terminal.

Each unit circuit of the data output buffer 14 is
When both the internal control signals OE and DOC are set to the high level, the internal output signals SO0 to SO0 that are selectively brought into the transmission state and output from the corresponding unit circuit of the sense amplifier 15 are output.
The SOF is externally output via the corresponding data output terminal. The high level of the output signal at the output terminal of each unit circuit of the data output buffer 14 is the power supply level on the high potential side of the circuit, and the low level is the power supply level on the low potential side of the circuit (ground potential). Internal control signal OE or D
When any of the OCs is at the low level, the data output terminal is in the so-called high impedance state.

FIG. 7 shows an example of the structure of the memory cell array 11 in relation to its peripheral circuits.

As shown in FIG. 7, the memory cell array 1
1 is a NAND type and includes a plurality of memory cells M
Each C is formed of an n-channel type MOS transistor, one end of its series connection circuit is coupled to the bit line BL, and the word line WL to be selected by the address signal is set to the non-selection level of the memory cell and The word line WL to be unselected is set to the selection level of the memory cell, so that the stored information is read depending on whether or not a direct current path is formed in the series connection circuit. An ion implantation programming method is adopted in which the threshold voltage of the memory cell transistor is changed by channel ion implantation to program data. As the material of the word line WL, a high resistance material equivalent to that used for forming the gate electrode of the MOS transistor is applied, and compared with the case where the word line WL is made of aluminum or the like, the X address decoder 13 Signal delay occurs at the near end and the far end of the word line viewed from above. This signal delay is caused by the wiring load such as the wiring capacitance component and the gate capacitance of the memory cell, in addition to the resistance of the wiring of the word line. For this reason,
In the X address decoder 13, since the wiring load of the word line WL is larger than the ON resistance of the transistor that drives the word line WL, the signal delay in the word line has a characteristic that it does not depend so much on the fluctuation of the power supply voltage. Become.

FIG. 9 shows a configuration example of the timing generation circuit 10.

In FIG. 9, the timing generation path 10 is
It includes p-channel type MOS transistors P1 and P2 and n-channel type MOS transistors N1 and N2 forming an input NOR gate. Of these, the commonly coupled gates of the MOS transistors P1 and N1 are coupled to an external terminal via an electrostatic protection circuit (not shown), and
The commonly coupled gates of transistors P2 and N2 are coupled to the circuit ground potential. As a result, the input gates formed by the MOS transistors P1 and P2 and N1 and N2 are constantly in the transmission state, and the chip enable signal CE * input as the activation control signal through the external terminal
Is inverted and transmitted to its output terminal.

MOS transistors P1 and P2 and N
The output signal of the input gate composed of 1 and N2 is supplied to one input terminal of the NAND gate NA1 via the inverter V1 and the other of the NAND gate NA1 via the four inverters V2 to V5 arranged in series. It is supplied to the input terminal. As a result, the output signal of the NAND gate N1 is set to the high level by setting the chip enable signal CE * to the low level, and after the chip enable signal CE * is returned to the high level, the inverters V2 to V2.
When the delay time of 5 elapses, it is returned to the low level. The output signal of the NAND gate N1 is supplied to the internal control signal C via two inverters V6 and V7 which are arranged in series.
E0, which is an internal control signal CE1 via two inverters V6 and V8 which are also in serial form. Then, the internal control signal CE1 is inverted by the inverter V9 to become the inverted internal control signal CE1 *.

Further, the timing generation circuit 10 is a p-channel type MOS that forms another input NOR gate.
Transistors P3 and P4 and n-channel MOS
It includes transistors N3 and N4. Of these, the commonly connected gates of the MOS transistors P3 and N3 are coupled to an external terminal via an electrostatic protection circuit (not shown),
The inverted internal control signal CE1 * is supplied to the commonly connected gates of the MOS transistors P4 and N4. As a result, the input gate formed of the MOS transistors P3 and P4 and N3 and N4 is selectively transmitted by setting the inversion control signal DE1 * to the low level, that is, by setting the chip enable signal CE * to the low level. The output enable signal OE *, which is brought into the state and inputted as the activation control signal through the external terminal, is inverted and transmitted to the output terminal. The output signal of the input gate is supplied to the data output buffer 14 as the internal control signal OE through the five inverters V10 to V15 arranged in series (see FIG. 6).

The timing generation circuit 10 further includes a delay circuit DL1 including six unit delay circuits UD1 to UD6 arranged in series. Of these, the unit delay circuit UD1
The address transition detection circuit 19 is connected to the non-inverting input terminal of
The address transition detection signal ATDS, which is the output signal of, is supplied to the inverted input terminal of the inverter V16 of the address transition detection signal ATDS. The non-inverting and inverting input terminals of the unit delay circuit UD2 are supplied with the non-inverting and inverting output signals of the unit delay circuit UD1 provided in the preceding stage, respectively. Unit delay circuit U
The non-inverting and inverting input terminals of D3 to UD6 are supplied with the non-inverting and inverting output signals of the unit delay circuits UD2 to UD5 provided in the preceding stage, respectively. The non-inverted output signal of the unit delay circuit UD6 is supplied to one input terminal of the NOR gate NOR1, and its inverted output signal is supplied to the inverter V17.
After being inverted by, it is supplied to the other input terminal of the NOR gate NO1. Output signal SD of NOR gate NO1
Becomes the inverted internal control signal EQ * through two inverters and V18 and V19.

Further, the output signal of the NOR gate NO1 is supplied to the unit delay circuits UD7 and UD11 non-inverting input terminals which form the delay circuits DL2 and DL3 by converting the inverters V20 and V25 into the inverter V21.
, And V26, and further supplied to the inverting input terminals of the unit delay circuits UD7 and UD11. The delay circuit DL2 includes four unit delay circuits UD7 to UD10 in a serial form, and the delay circuit DL3 includes three range delay circuits UD11 to UD13 in a serial form.

The unit delay circuit U at the final stage of the delay circuit DL2
The non-inverted output signal of D10 is supplied to one input terminal of the NOR gate NO2, and its inverted output signal is supplied to the other input terminal of the NOR gate NO2 via the inverter V22. The output signal of the NOR gate NO2 is supplied to the third input terminal of the NOR gate NO3. The inverted internal control signal C is applied to the first input terminal of the NOR gate NO3.
E1 * is supplied, and the output signal of the inverter V20 is supplied to the second input terminal thereof. The output signal of the NOR gate NO3 is output from the two inverters V23 in the serial form.
, And V24, it is supplied to the sense amplifier 15 as an internal control signal SAC (see FIG. 6).

As a result, the output signal of the NOR gate NO2 is set to the low level in response to the high level change of the output signal of the inverter V20, that is, the low level change of the output signal SD of the NOR gate NO1 and the output signal of the inverter V20 becomes low. The level, that is, the output signal SD of the NOR gate NO1 is returned to the high level, and is returned to the high level when a predetermined delay time as the delay circuit DL2 has elapsed. As a result, as for the output signal of the NOR gate NO3, that is, the internal control signal SAC, the output signal of the inverter V20 is at the low level, that is, the output signal SD of the NOR gate NO1 is returned to the high level, and then the output signal of the NOR gate NO2 is at the high level. To the high level, that is, for a time corresponding to the delay time of the delay circuit DL2, it is temporarily set to the high level.

On the other hand, the inverted output signal of the unit delay circuit UD13 at the final stage of the delay circuit DL3 is supplied to one input terminal of the NOR gate NO4, and the inverted output signal is input to the other input of the NOR gate NO4 via the inverter V27. Supplied to the terminal. The output signal of the NOR gate NO4 is supplied to one input terminal of the NOR gate NO5. The output signal of the inverter V25 is supplied to the other input terminal of the NOR gate NO5. The output signal of the NOR gate NO5 becomes the inverted internal control signal SL * via the inverter V28. Further, the output signal of the NOR gate NO4 becomes the internal control signal DOC through the four inverters V29 to V32 in the serial form.

As a result, the output signal of the NOR gate NO4 is set to the air level in response to the high level change of the output signal of the inverter V25, that is, the low level change of the NOR gate NO1 output signal SD, and the output signal of the inverter V25 is set to the low level, That is, the output signal SD of the NOR gate NO1 is returned to the high level, and is returned to the high level when a predetermined delay time as the delay circuit DL3 has elapsed. However, as for the inverted internal signal SL *, the output signal of the inverter V25 is low level, that is, the NOR gate NO.
From the time the output signal SD of 1 is returned to the high level until the output signal of the NOR gate NO4 is returned to the high level
In other words, it is temporarily set to the high level for a time corresponding to the delay time of the delay circuit DL3. Needless to say,
The internal control signal DOC is the address transition detection signal ATDS
Of the inverter V2 after the internal control signal SL * is returned to the high level.
When the time corresponding to the delay time of 9 to V32 has elapsed, the low level is restored. As a result, the time relationship between the address transition detection signal ATDS and the inverted internal control signals EQ *, SL * and the internal control signals SAC and DOC corresponds to that shown in FIG.

Next, the unit delay circuit forming the delay circuit will be described.

The plurality of unit delay circuits UD1 to UD13
Can have the same configuration as each other,
Here, the unit delay circuit UD1 will be described in detail.

FIG. 1 representatively shows the configuration of the unit delay circuit UD1.

As shown in FIG. 1, p-channel type M
The OS transistor P10 and the n-channel type MOS transistor N11 are connected in series via a resistor R, and p
The gate electrode of the channel-type MOS transistor P10 and the gate electrode of the n-channel-type MOS transistor N11 are commonly connected to form a signal input terminal to the unit delay circuit UD1. A capacitor C is provided between the coupling point of the p-channel MOS transistor P10 and the resistor R and the low-potential-side power supply Vss line, and a time constant circuit for signal delay is formed. The capacitor C is formed of a material equivalent to the load capacitance of the word line WL, although not particularly limited. The p-channel MO
The S transistor P10 is coupled to the high potential side power supply Vdd. When the gate electrodes of the MOS transistors P10 and N11 are at low level, the p-channel type MOS transistor P10 is turned on, so that the charge is stored in the capacitor C. When the gate electrodes of the MOS transistors P10 and N11 are set to the high level, the n-channel MOS transistor N11 is turned on, and the accumulated charge of the capacitor C is discharged to the low potential side power source Vss side via the resistor R. . At this time, depending on the time constant of CR, the node P2
The potential of is gradually decreased. By changing the value of the resistor R or the value of the capacitor C, the delay time here can be changed. Further, an inverter V50 is arranged in the subsequent stage of such a time constant circuit. This inverter V50
Is a p-channel type M coupled to the high potential side power source Vdd
An OS transistor P11, an n-channel MOS transistor N13 coupled to the low-potential-side power supply Vss, and p
It includes an n-channel MOS transistor N12 interposed between a channel MOS transistor P11 and an n-channel MOS transistor N13. The n-channel MOS transistor N12 is of depletion type, and the gate electrode is coupled to the source electrode so that the drain-source current (Ids) depends on the logic threshold value of the inverter V50. .
Therefore, even if the power supply voltage fluctuates, the fluctuation of the logic threshold value of the inverter V50 can be suppressed small.

Here, the difference between the case where the depletion type n-channel type MOS transistor N12 is provided and the case where it is omitted will be described.

FIG. 2 shows the configuration of the unit delay circuit in the case where the n-channel type MOS transistor N12 is omitted. In FIG. 2, the inverter V52 is a normal inverter formed by connecting a p-channel type MOS transistor P11 and an n-channel type MOS transistor N13. It should be noted that components having the same functions as those shown in FIG. 1 are designated by the same reference numerals.

FIG. 4 shows the voltage dependence characteristics when the circuit configuration shown in FIG. 2 is adopted. Memory cell array 11
However, in the case of the NAND type structure as shown in FIG.
Since the material of the word line is made of the same high resistance material as that used for forming the gate electrode of the MOS transistor, the X address decoder 13 is more effective than the case where the word line WL is made of aluminum or the like. Signal delay occurs at the near end and far end of the word line as seen. This signal delay is caused by the wiring load such as the wiring capacitance component and the gate capacitance of the memory cell, in addition to the resistance of the wiring of the word line WL. Therefore, since the wiring load of the word line is larger than the ON resistance of the transistor that drives the word line WL, the signal delay in the word line does not depend so much on the fluctuation of the power supply voltage. The characteristic line H1 in FIG. 4 shows the voltage dependence of the signal delay in driving the word line WL in this case. Although the signal delay time in the word line WL is shortened due to the rise in the power supply voltage, it is gentle around that time.

As described above, the signal delay in driving the word line WL does not depend so much on the fluctuation of the power supply voltage, whereas in the unit delay circuit shown in FIG. Since the power supply voltage fluctuates relatively, the delay circuit including the inverter V52 has a relatively large voltage dependence of the delay time. That is, when the power supply voltage increases, the logic threshold value of the inverter V52 also increases, and the node P3 changes to the high level even though the potential level of the node P2 has not been lowered so much. The delay time is significantly shortened with increasing. A characteristic line H2 in FIG. 4 is a voltage dependence characteristic of the delay circuit when the configuration of FIG. 2 is adopted. A region P1 on the right side of the intersection of the characteristic lines H1 and H2 is a non-operating region, and this region P1
However, since the delay time in the delay circuit is too short, the sense amplifier 15 and the like operate faster than the memory cell data is determined by word line driving. In order to avoid such timing mismatch, the delay time in the delay circuit is set to a large value in advance as shown by the characteristic line H3 in FIG. 2, and at least within the range where the operation of the ROM 34 is guaranteed, the power supply voltage is high. Even when the value becomes high, it is necessary to avoid the dead region P1 in timing. This means that considering the case where the power supply voltage is relatively low, the access time of the ROM 34 becomes long due to the operation margin that is too large.

On the other hand, in this embodiment, as shown in FIG. 1, a p-channel type MOS transistor P1 is used.
1 and an n-channel type MOS transistor N13 are provided with a depletion type n-channel type MOS transistor N12, and the gate electrode and the source electrode of this n-channel type MOS transistor N12 are coupled to each other, thereby forming an n-channel type MOS transistor. Since N12 is operated in the saturation region, the drain current controlled by the threshold voltage of the MOS transistor N12 flows in terms of circuit. Therefore, the logic threshold value of the inverter V50 does not change much even if the power supply voltage is changed. In other words, depletion type MO
By providing the S transistor N12, the inverter V5
The voltage dependence of the logic threshold value of 0 can be reduced. As a result, the voltage dependence of the delay time in the delay circuit is
In FIG. 3, it becomes as shown by the characteristic line H5, and it follows the change of the characteristic line H1 (voltage dependence of signal delay in the word line drive system). As such, the delay circuit UD1
Since it is possible to approximate the voltage dependence at the word line to the voltage dependence at the word line, it is necessary to set a large delay amount of the delay circuit in order to avoid the dead region P1 as in the case shown in FIG. Disappears. Therefore, the time constant circuit (C,
In the constant setting of R), by setting an appropriate operation margin, a useless operation margin when the power supply voltage is relatively low is eliminated, and as a result, the access time of the ROM 34 can be shortened.

According to the above embodiment, the following operational effects can be obtained.

(1) A depletion type n-channel MOS transistor N12 is provided between a p-channel MOS transistor P11 and an n-channel MOS transistor N13, and a gate electrode and a source electrode of this n-channel MOS transistor N12 are provided. By operating the n-channel MOS transistor N12 in the saturation region, the dependency of the logic threshold value of the inverter V50 on the power supply voltage can be reduced, and the delay time of the delay circuits DL1 to DL3 can be reduced. The voltage dependence is in line with the voltage dependence of the signal delay in the word line, as shown in FIG. So delay circuit D
Since the voltage dependence in L1 to DL3 can be made close to the voltage dependence in the word line, the delay amount of the delay circuit is increased in order to avoid the dead region P1 as in the case shown in FIG. There is no need to set it up,
A useless operation margin when the power supply voltage is relatively low is eliminated, and the access time of the ROM 34 can be shortened.

(2) Unit delay circuits UD1 to UD of the delay circuit based on a time constant circuit consisting of a resistor R and a capacitor C
Since 13 is configured, a delay circuit having a desired delay time can be realized with relatively few circuit elements. Also, a capacitor C forming a time constant circuit
Can be formed of the same material as the load capacitance of the word line forming the memory cell array 11, so that the relative process variation of the delay time of each delay circuit is sufficiently suppressed. As a result, in the above embodiment, since the timing margin of the internal control signal can be correspondingly reduced, the cost of the mask ROM can be reduced while
It can promote reduction of access time.

(3) Since the access time can be shortened as described above, such a mask ROM is used.
However, when applied to the ROM 34 of the data processing device shown in FIG. 5, the program written in the memory cell can be read at high speed, and therefore the processing speed of the data processing device should be increased. You can

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the gate electrode and the source electrode of the depletion type n-channel type MOS transistor N12 are short-circuited, but the gate electrode has a reference voltage generated by a low voltage power supply circuit (not shown). To the n-channel MOS transistor N12, the power supply voltage dependence of the logic threshold value of the inverter V50 can be reduced and the voltage dependence of the delay circuit can be reduced. The effect can be obtained. In the above embodiment,
Although the time constant circuit is formed by the capacitor C and the resistor R, the time constant circuit is not limited thereto. For example, CMOS
A time constant circuit may be formed by multi-stage coupling of transistors.

In the above description, the case where the invention made by the present inventor is mainly applied to the ROM included in the data processing apparatus which is the background field of application has been described, but the present invention is not limited thereto. Instead, it can be applied to various semiconductor memory devices. It can also be applied to a semiconductor integrated circuit built in a single-chip microcomputer or the like.

The present invention can be applied on condition that it includes a delay circuit that delays at least an input signal.

[0060]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the first coupled to the high potential side power source
Forming an inverter of a delay circuit including a transistor, a second transistor coupled to a low-potential-side power supply, and a depletion type transistor interposed between the first transistor and the second transistor, By matching the voltage dependence of the delay time in the delay circuit with the voltage dependence of the signal delay of the word line drive system, it is possible to reduce unnecessary timing margins, and thereby the access time of the semiconductor memory device. Can be shortened. Further, a data processing device including such a semiconductor memory device can be applied. In that case, since the access time of the semiconductor memory device is shortened, the processing time of the data processing device can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a configuration example of a unit delay circuit included in a ROM which is an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram of a configuration to be compared and contrasted with the unit delay circuit.

3 is a voltage dependence characteristic diagram when the circuit shown in FIG. 1 is adopted.

4 is a voltage dependence characteristic diagram when the circuit shown in FIG. 2 is adopted.

FIG. 5 is a block diagram of an overall configuration example of a data processing device including a semiconductor memory device according to the present invention.

FIG. 6 is a block diagram of a configuration example of the ROM.

FIG. 7 is a circuit diagram of a configuration example of a memory cell array included in the ROM.

FIG. 8 is an operation timing chart of the ROM.

FIG. 9 is a circuit diagram of a configuration example of a timing generation circuit included in the ROM.

[Explanation of symbols]

10 Timing Generating Circuit 11 Memory Cell Array 12 X Address Buffer 13 X Address Decoder 14 Output Buffer 15 Sense Amplifier 16 Y Switch 17 Y Address Decoder 18 Y Address Buffer 19 Address Transition Detection Circuit 31 CPU 32 SDRAM 33 SRAM 34 ROM 35 Peripheral Device Control Unit 36 display system 38 external storage device 39 keyboard 40 CRT display UD1 to UD13 unit delay circuit DL1 to DL3 delay circuit P11 n-channel type MOS transistor N12 depletion type n-channel type MOS
Transistor N13 n-channel MOS transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Nakamura 5-20-1 Joumizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Shinichi Fukasawa 5 Kamimizuhoncho, Kodaira-shi, Tokyo No. 20-1 Stock Company Hitachi Ltd. Semiconductor Division

Claims (5)

[Claims] 1. A semiconductor including a memory cell array in which a plurality of memory cells are arranged, and a delay circuit for delaying an input signal, wherein a control signal for a data read operation from the memory cell array is formed by the delay circuit. In the memory device, the delay circuit is interposed between a first transistor coupled to a high potential side power source, a second transistor coupled to a low potential side power source, and the first transistor and the second transistor. And an inverter including a depletion type transistor. 2. A memory cell array in which a plurality of memory cells are arranged, a data read system for reading stored data in the memory cell array, an address transition detection circuit for detecting a transition of an input address, and In a semiconductor memory device including a delay circuit for generating an operation control signal of the data read system based on a detection signal of an address transition detection circuit, the delay circuit includes a first transistor coupled to a high potential side power supply. A semiconductor memory comprising a second transistor coupled to a low-potential-side power source and an inverter including a depletion type transistor interposed between the first transistor and the second transistor. apparatus. 3. A memory cell array in which a plurality of memory cells are arranged, a data read system for reading stored data in the memory cell array, an address transition detection circuit for detecting transition of an input address, and the address. In a semiconductor memory device including a delay circuit for generating an operation control signal of the data read system based on a detection signal of a transition detection circuit, the delay circuit includes a time constant circuit formed by coupling a capacitor and a resistor, An inverter for inverting an output signal of the time constant circuit, wherein the inverter includes a first transistor coupled to a high potential side power source, a second transistor coupled to a low potential side power source, and the first transistor. And a depletion type transistor interposed between the second transistor and the second transistor. Semiconductor memory device. 4. The semiconductor memory device according to claim 1, wherein the depletion type transistor is operated in a saturation region by short-circuiting a gate electrode and a source electrode. 5. A data processing device comprising the semiconductor memory device according to claim 1 and a central processing unit capable of accessing the semiconductor memory device.