JPH0289290A - Static type integration circuit memory - Google Patents

Abstract

PURPOSE:To initialize the states of every memory cells within the short period of time immediately after power source apply by building-in a circuit to automatically initialize the value of every memory elements into the memory when the power source is supplied. CONSTITUTION:The circuit to initialize for every memory elements is built-in the memory itself when the power source is applied. This circuit consists of the time constant circuit of a resistance R and a capacity C and the circuit able to simultaneously write initialization information, all '0' for instance, into every memory element within the short period of time immediately after the power source apply to the memory with the use of this time constant. Thus, the state of every memory cell can be initialized within the short period of time immediately after the power source apply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an initial setting circuit for an integrated circuit memory I, particularly when a static type integrated circuit memory is turned on.

[Prior art and its problems] An integrated circuit memory has a memory element that contains "0" or "0".
2'f!' in dynamic memory and static memory. There is gN. In the following text, the term "memory" refers to a static integrated circuit memory that does not require any special operation in terms of storage retention. Furthermore, the term "memory element" refers to a unit cell that stores information in a memory.

Regarding the memory mounted on the printed board, the value of the memory element immediately after power is turned on is rOJ or "1", which is completely randomly stored, and its reproducibility is not guaranteed each time the power is turned on. Therefore, when inspecting a single printed circuit board equipped with the memory or a system equipped with the printed circuit board, the first thing to do is to test the memory for the first time.
It is necessary to set fI. For this purpose, for example, "0" is written into this memory as an initial state.

To do this, write data "0" must be sent to all memory addresses. After that, in order to check whether initialization has been done correctly, a read command is sent to the previous address of the same memory, and its normality is checked. However, with this method, as the size of the memory increases, the time it takes to write the initial settings also increases, and if the data read from the memory differs from the expected value, the memory write circuit needs to The problem is that it is difficult to determine whether there is a problem, a problem with the readout circuit, or a defect in the memory element itself.

[Differences between the Invention and the Prior Art] The present invention differs from the conventional memory described above in that the present invention incorporates a circuit inside the memory that automatically initializes the values of all memory elements when the power is turned on.

[Means for Solving the Problems] The memory of the present invention incorporates a circuit that performs initial settings for all memory elements of the memory itself when power is turned on. This circuit consists of a time constant circuit of resistance and capacitance.
Utilizing this time constant, a circuit is constructed that can simultaneously write initial setting information, for example, all "0", to all memory elements within a short period of time immediately after power is turned on to the memory.

[Example] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the first circuit of the present invention, which is different from the conventional memory element circuit.
FIG. 2 is a circuit diagram showing an example. In particular, a circuit that characterizes this embodiment is shown by a chain line in the figure. A1-A
n is an address signal which, after being developed by the decoder 1, selectively drives one of the specific word lines W1 to Wn. When Wl is selected, transistors T1 and T2 are made conductive via the driver DIO on this word line, and the signal stored in memory cell 2 is transferred to digit line DIO.
It is read out to I and DI. This value is read out to the RD terminal by the sense amplifier 3. On the other hand, in the write operation, in addition to the address signals A1 to An, write information is sent to the digit line D2. DI and D through driver D20゜D20 from n
I- and written to memory cell 2. Reference numeral 4 indicates a precharge circuit, which is driven by a driver D30.

In this embodiment, a circuit for forcibly initializing memory cells is incorporated into the address line and digit line, and all memory cells are initialized in a very short time after power is turned on. The note N1 at the midpoint between the resistance R and the capacitance C according to this embodiment is the gate circuit GIO to G inserted between the address lines.
transistor T3.in, which is also inserted on the digit line side. T4. T5. It is also connected to T6 directly or via inverter G20. Immediately after the power is turned on, there is no charge in C, so the potential of node N1 is 0■
It is. Therefore, the inputs of the gates 010 to G1n also become OV, and the address lines W1 to \Vn become low level, so the outputs of DIO to Din are inverted and all become high and connected to the memory cell 2. TI and T2, which are connected, become conductive. On the other hand, since their inputs are at low level, T3 and T4 are non-conductive and D20. ■The output of l1 is DI, D
I can't convey it to l. Roughly, the input gate of T5 has G2.
0 supplies a high level which is an inversion of the potential 0■ of N1, so conduction occurs and earth air appears on Dl.

Similarly, since T6 is of P-channel type, it is also conductive and the power supply voltage appears on DI. Since TI and T2 are also conductive, the potential of this DI and n is supplied to the memory cell 2, and the cell is forcibly initialized.

Next, after a period of time determined by the time constants of R and C has passed, the potential of node N1 rises to the power supply voltage, and 610 to GIn and UT3. While opening the gate of T4, T5. T6 is turned off to prevent the ground voltage and power supply voltage from going out to DI and DI, and then preparation is made for normal memory operation as described above. The circuit according to this embodiment is commonly connected to all address lines and digit lines, and all memory cells are initialized simply by turning on the power.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In the embodiment shown in FIG. 1, as the degree of integration of the memory increases and the number of cells increases, the number of wirings leading to the address decoder and digit line increases with control using a single C and R, and the resistance and capacitance of these wirings increases. This makes it difficult to set the values of C and R in the time constant circuit. Therefore, if an initial setting circuit is prepared for the digit line as in the embodiment shown in FIG. 2, this difficulty can be overcome.

[Effects of the Invention] As explained above, the present invention incorporates a time constant circuit for initialization into the memory, and it is possible to initialize the states of all memory cells within a short time immediately after power is turned on. be. Therefore, the testing time can be shortened when testing printed circuit boards and systems incorporating this memory, and even if a fault occurs, it is possible to easily isolate the location of the fault.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 is a block diagram of the second embodiment. 1 φ ・ ・ ・ 2 ・ ・ ・ φ ・ 3 ・ ・ ・ ・ 4 ・ ・ ・ ・ ・ A1~An ・ Wl, Wn GIO, GIN1 ・ ・ ・ ・ ・Address decoder, ・Memory cell, ・Sense Amplifier, ・Precharge circuit, ・Address line, ・Word line, ・Gate element, ・Node, DIO, Din, D20°, D30... Driver DI. ■T. D2゜D-digit line, TI, T2. T3゜T4. T5. T6・・・・・・Transistor, RD・
... Read terminal, R...
・・・・・・ ・・・Resistance, C・・・・・・
·······capacity. Patent issued 1 @ Nippon Electric Co., Ltd.

Claims (1)

[Claims] In a static integrated circuit memory in which each storage element has a self-holding function, a time constant circuit is formed by connecting a resistor and a capacitor in series, and the potential at the connection point of the resistor and capacitor of the time constant circuit immediately after power is turned on. 1. A static integrated circuit memory characterized in that address lines and write lines are simultaneously controlled using changes to write the same data to all storage elements within the memory.