JPH0729977A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make an effective positioning of an integrated circuit on an LSI chip possible by relaxing the positioning regulations of a large-scale function block. CONSTITUTION:A first power supply wiring 31 to apply a first potential is so formed as to surround a large-scale function block 11 and a second power supply wiring 32 to apply a second potential is so formed as to surround the first power supply wiring 31. Then, a third power supply wiring 33 to apply the first potential is so formed as to surround the second power supply wiring 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device which relaxes restrictions on the layout of large-scale functional blocks and enables efficient layout on an LSI chip.

[0002]

2. Description of the Related Art ASIC (Application Specific Integ
The rated circuit) design method is generally classified into a standard cell method and a gate array method. The standard cell method has a higher degree of freedom in design than the gate array method, such as the size of the transistor can be freely decided. Especially, when a large-scale functional block such as RAM is mounted, high performance and high integration are achieved. LSI can be realized. On the other hand, the development period is long, and it is necessary to fabricate a mask for all process steps. Therefore, the development cost is higher than that of the gate array method. In the gate array method, since the arrangement of transistors is designed in advance, the LSI designer only has to make a mask for the wiring process, and the development period is short and the development cost is low compared to the standard cell method. On the other hand, since a large-scale functional block such as a RAM is also designed by using a transistor designed in advance, it is not possible to obtain the high performance and the high degree of integration like the standard cell method.

Therefore, as a method having the advantages of the above two methods, what has recently attracted attention is that a high-performance and highly integrated RAM designed by the standard cell method is preliminarily used in a transistor array of a gate array. It is a method of replacing with a part (Hereafter, here, ECA
(Embedded Cell Array) method). The ECA method has an advantage that an LSI designer can develop a high-performance and highly-integrated LSI equivalent to the standard cell method in a short development period similar to that of the gate array method.

By the way, in recent ASICs, in order to design a mask pattern of an LSI in a short period of time, it is general that wiring between cells is automatically placed and wired by a CAD tool. FIG. 10 is a configuration diagram showing a transistor array and power supply wiring of a conventional gate array. In the figure, 1 is a transistor, 2 is a transistor array, and 3 and 4 are power supply wirings.

Next, the operation will be described. In the case of the gate array method, as shown in FIG. 10, a plurality of transistors 1 are arranged in a row, a cell is formed by using this transistor row 2, and a power wiring is automatically wired between the cells by an automatic placement and routing tool. . In this case, it is common to arrange the power supply wirings 3 and 4 in the horizontal direction above and below the transistor row 2.
(Hereinafter, this power supply wiring is referred to as follow wiring.) Also, even in the case of the standard cell method, the height of each cell is generally the same in order to effectively use the automatic placement and routing tool. . In this case, it is more efficient to arrange the power supply wirings 3 and 4 for supplying power to each cell in the horizontal direction above and below the cell, as in the case of the gate array method.

On the other hand, in the case of the ECA method, as described above, a large-scale functional block such as a high-performance and highly-integrated RAM designed by the standard cell method is replaced with a part of the transistor array of the gate array. In this way, when cells of uniform height and large-scale functional blocks that are taller than that are mixed, the automatic placement and routing tool can be effectively used to perform follow wiring and power wiring for large-scale functional blocks. As a method of connecting without contradiction, a method of surrounding the large-scale functional block with power supply wiring has been proposed. (Hereinafter, the power supply wiring surrounding the large-scale functional block is simply referred to as a power supply ring.) FIG. 11 shows a conventional large-scale functional block with a power supply ring disclosed in Japanese Patent Laid-Open No. 2-86145. It is a plan view showing an example mounted on the
Is a large-scale functional block, 12 is an inner power supply ring (inner ring), 13 is an outer power supply ring (outer ring), 14 is a stripe wiring for applying a power supply potential (VDD), 15
Is a stripe wiring for applying a ground potential (VSS), 1
6 is an LSI. In the LSI 16, a power supply current from the outside is supplied to the plurality of follower wirings 3 and 4 by stripe wirings 14 and 15 vertically arranged on the LSI 16. These stripe wirings are also automatically wired by the automatic placement and routing tool.

FIG. 12 is an enlarged view of the main part of the LSI 16.
In the figure, 17 is a through hole, 18 is a VDD pin,
Reference numeral 19 is a VSS pin, and 20 is a signal pin. Usually, the follow wirings 3 and 4 are composed of a first layer metal wiring, and the stripe wirings 14 and 15 are composed of a second layer metal wiring.
The power supply rings 12 and 13 are composed of an outer ring 13 that supplies a power supply potential (VDD) and an inner ring 12 that supplies a ground potential (VSS). In the figure, the outer power ring (outer ring) 13 is VDD, and the inner power ring (inner ring) 12 is VSS. These two power ring 1
In general, 2 and 13 have a horizontal wiring portion formed of a first-layer metal wiring and a vertical wiring portion formed of a second-layer metal wiring. The wiring width of the power supply rings 12 and 13 must be wide enough to supply the power supply current required by the large-scale functional block 11. Therefore, as the power supply current required by the large-scale functional block 11 increases, the widths of the power supply rings 12 and 13 become wider, and the horizontal wiring (first-layer metal wiring) of the power supply rings 12 and 13 and the vertical direction thereof. Through hole 1 for connecting wiring (second layer metal wiring)
7 areas will also be widened.

The two power supply rings 12 and 13 are usually composed of a first-layer metal wiring for the horizontal component and a second-layer metal wiring for the vertical component. Therefore, at least power supply wiring from the outer power supply ring (outer ring) 13 to the large-scale functional block 11 (hereinafter, power supply wiring from the power supply ring to the large-scale functional block is simply referred to as ring connection wiring).
In order to avoid the inner power ring (inner ring) 12,
The wiring layer must be different from the wiring layer of the power ring 12. That is, when the power supply wiring is configured by two wiring layers, the horizontal ring connection wiring connecting the vertical component (second layer metal wiring) of the outer ring 13 and the large-scale functional block 11 is the first layer metal. Outer ring 1 made up of wiring
Horizontal component of 3 (first layer metal wiring) and large-scale functional block 1
The vertical ring connection wiring for connecting with 1 is composed of the second layer metal wiring.

[0009]

By the way, when the large-scale functional block 11 with the power ring is arranged on the LSI 16, the stripe wiring 14 of VDD and the power ring 12 of VSS, the stripe wiring 15 of VSS and VDD are provided.
It is necessary to arrange so as not to short-circuit with the power supply ring 13. In FIG. 13, VDD stripe wiring 1
4 need only be connected to the outer ring (VDD) 13 and do not need to be wired inside the large-scale functional block 11 any more, so that it does not overlap the inner ring (VSS) 12. However, since the VSS stripe wiring 15 must be connected to the inner ring (VSS) 12, it must not overlap with the same wiring layer (that is, the vertical wiring layer / through hole region) of the outer ring (VDD) 13. It will be a matter. Therefore, the larger the area of the through hole 17 of the outer ring 13, the greater the restrictions on the arrangement. In the example of FIG. 13,
Even if the large-scale functional block 11 with power ring is moved to the right or left, the outer ring (VDD) 13
And the VSS stripe wiring 15 are short-circuited.

Since the conventional semiconductor integrated circuit device is configured as described above, when arranging a large-scale functional block with a dual power supply ring on an LSI, the wider the wiring width of the power supply ring, the more Since the layout restriction for preventing short-circuiting between VDD and VSS becomes strict (may not be possible in some cases), it is very difficult to efficiently arrange a large-scale functional block on an LSI chip. There was a problem such as

Further, the conventional follow wiring, stripe wiring, power supply ring and ring connection wiring are wiring for supplying a power supply potential (hereinafter abbreviated as VDD) and ground potential (hereinafter, V).
As for the wirings for giving SS), the horizontal wirings are all composed of the first-layer metal wirings, and the vertical wirings are all composed of the second-layer metal wirings. The VDD wiring is the follow wiring 3, 4
And the VSS stripe wiring 15 and the VSS wiring of the ring connection wiring must not be short-circuited with the follow wirings 3 and 4 and the VDD stripe wiring 14. 11
There is a limitation when arranging the above on the LSI chip. Therefore, it is impossible to efficiently arrange the large-scale functional block 11 on the LSI chip. Further, as shown in FIG. 13, when the wiring width of the ring connection wiring in the horizontal direction is larger than the wiring distance of the follow wiring, it is impossible to arrange as it is. However, there has been a problem that manual work such as cutting the follow wiring is generated on the way, which causes deterioration of design efficiency.

The present invention has been made in order to solve the above-mentioned problems, and by arranging the power supply ring with at least three ring-shaped wirings, the restriction on the arrangement of large-scale functional blocks is eased, and the LSI chip Enables efficient layout on the upper side, and relaxes the layout restrictions of large-scale functional blocks by configuring the vertical component (or horizontal component) of the two power supply rings VDD and VSS with different wiring layers. However, it is an object of the present invention to provide a semiconductor integrated circuit device that enables efficient placement on an LSI chip.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device for applying a first potential to a large-scale functional block so as to surround the large-scale functional block. Power supply wiring is formed, and a second power supply wiring for applying a second potential to the large-scale functional block is formed so as to surround the periphery of the first power supply wiring, and the second power supply wiring is formed. A third power supply line for applying the same potential as the first potential to the large-scale functional block is formed so as to surround the periphery of the.

In the semiconductor integrated circuit device according to the second aspect of the present invention, the first power supply wiring and the third power supply wiring are connected to each other.

In the semiconductor integrated circuit device according to the third aspect of the present invention, the first power supply wiring for applying the first potential to the large-scale functional block is provided so as to surround the large-scale functional block. A second power supply for forming a large potential between the large-scale functional block and the first power supply wiring so as to surround the periphery of the large-scale functional block and to apply a second potential to the large-scale functional block. A wiring is formed, and one wiring portion of the first power supply wiring facing each other and the second power supply wiring are formed by the same wiring layer.

According to a fourth aspect of the semiconductor integrated circuit device of the present invention, the first power supply wiring for applying the first potential and the second power supply for applying the second potential to the logic circuit element are provided. Wirings are formed in parallel with each other by the first wiring layer, and a third power supply wiring for applying the first potential to the large-scale functional block is formed so as to surround the large-scale functional block. A fourth power supply wiring for applying a second potential to the large-scale functional block is formed between the large-scale functional block and the third power-supply wiring so as to surround the periphery of the large-scale functional block. However, a wiring portion of the fourth power supply wiring in a direction different from the first and second power supply wirings, that is, in a direction orthogonal to the first and second power supply wirings is formed by the first wiring layer, and the first and second wirings of the third power supply wiring are formed. Wiring in a direction different from the second power supply wiring, that is, in a direction orthogonal to the second power supply wiring Min and is formed by the second wiring layer different from the first wiring layer.

According to a fifth aspect of the semiconductor integrated circuit device of the present invention, a first power supply wiring for applying a first potential and a second power supply for applying a second potential to the logic circuit element. Wirings are formed in parallel with each other by the first wiring layer, and a third power supply wiring for applying the first potential to the large-scale functional block is formed so as to surround the large-scale functional block. A fourth power supply wiring for applying a second potential to the large-scale functional block is formed between the large-scale functional block and the third power-supply wiring so as to surround the periphery of the large-scale functional block. However, a wiring portion of the fourth power wiring in the same direction as the first and second power wirings, that is, a direction parallel to each other is formed by a second wiring layer different from the first wiring layer. The same direction as the first and second power supply wirings of the power supply wiring 3 Wire portion in the direction parallel to are those formed by the first wiring layer.

Further, in a semiconductor integrated circuit device according to a sixth aspect of the present invention, a wiring portion of the fourth power supply wiring in a direction different from the first and second power supply wirings, that is, in a direction orthogonal to the first and second power supply wirings is the first
And a wiring portion of the third power supply wiring in a direction different from the first and second power supply wirings, that is, a direction orthogonal to the first and second power supply wirings, is formed by the second wiring layer.

Further, in the semiconductor integrated circuit device according to the invention of claim 7, the wiring portion of the fourth power supply wiring in a direction (orthogonal direction) different from the first and second power supply wirings is formed into a large-scale functional block. A fifth power supply line in the same direction as the first and second power supply lines for applying the second potential (direction parallel to each other) is formed by the first wiring layer.

Further, the semiconductor integrated circuit device according to the invention of claim 8 has a large-scaled function than the wiring portion of the fourth power supply wiring in the same direction (parallel to each other) as the first and second power supply wirings. The fifth power supply wiring in a direction (direction orthogonal to) of the first and second power supply wirings for applying the second potential to the block is formed by the first wiring layer.

Further, in the semiconductor integrated circuit device according to the invention of claim 9, the wiring portion of the third power supply wiring in a direction different from the first and second power supply wirings (direction orthogonal to each other) is formed into a large-scale functional block. A fifth power supply wiring in the same direction (parallel to each other) as the first and second power supply wirings for applying the first potential is formed by the second wiring layer.

The semiconductor integrated circuit device according to the invention of claim 10 has a larger scale function than the wiring portion of the fourth power supply wiring in the same direction (parallel to each other) as the first and second power supply wirings. A fifth power supply wiring in a direction (direction orthogonal to) of the first and second power supply wirings for applying the second potential to the block is formed by the second wiring layer.

Further, in the semiconductor integrated circuit device according to the invention of claim 11, the wiring portion of the fourth power supply wiring in a direction (orthogonal direction) different from the first and second power supply wirings is formed into a large-scale functional block. A fifth power supply line in the same direction (parallel to each other) as the first and second power supply lines for applying the second potential is formed by the second wiring layer.

In the semiconductor integrated circuit device according to the twelfth aspect of the present invention, the third power supply wiring has a larger scale function than the wiring portion in the same direction as the first and second power supply wirings (directions parallel to each other). A fifth power supply wiring in a direction (direction orthogonal to) the first and second power supply wirings for applying the first potential to the block is formed by the first wiring layer.

Further, in the semiconductor integrated circuit device according to the thirteenth aspect of the present invention, a wiring portion of the fourth power supply wiring in a direction different from the first and second power supply wirings (direction orthogonal to each other) is formed into a large-scale functional block. The fifth power supply wiring in the same direction (parallel to each other) as the first and second power supply wirings for applying the second potential is formed by the first wiring layer.

In the semiconductor integrated circuit device according to the fourteenth aspect of the present invention, the fourth power supply wiring has a larger scale function than the wiring portions in the same direction as the first and second power supply wirings (directions parallel to each other). A fifth power supply wiring in a direction (direction orthogonal to) of the first and second power supply wirings for applying the second potential to the block is formed by the second wiring layer.

In the semiconductor integrated circuit device according to the fifteenth aspect of the present invention, a wiring portion of the third power supply wiring in a direction (direction orthogonal to) different from the first and second power supply wirings is formed into a large-scale functional block. A fifth power supply line in the same direction (parallel to each other) as the first and second power supply lines for applying the first potential is formed by the second wiring layer.

The semiconductor integrated circuit device according to the sixteenth aspect of the present invention has a large-scaled function than the wiring portion of the third power supply wiring in the same direction (parallel to each other) as the first and second power supply wirings. A fifth power supply wiring in a direction (direction orthogonal to) the first and second power supply wirings for applying the first potential to the block is formed by the first wiring layer.

[0029]

According to the semiconductor integrated circuit device of the present invention, a first power supply wiring for applying a first potential to the large-scale functional block is formed so as to surround the large-scale functional block. A second power supply line that applies a second potential to the large-scale functional block is formed so as to surround the first power supply line, and the large scale is provided so as to surround the second power supply line. By forming the third power supply line for applying the first potential in the functional block, the power supply current supplied by applying the first potential mainly flows in the first power supply line. It is possible to narrow the width of the power supply wiring of 3. Therefore, when arranging a large-scale functional block with power wiring on an LSI, there are layout restrictions for preventing VDD of the power wiring and VSS of the stripe wiring from being short-circuited and VDD of the power wiring and VSS of the stripe wiring. This is alleviated as compared with the conventional one, and it becomes possible to construct an LSI chip area-efficiently.

According to a second aspect of the semiconductor integrated circuit device of the present invention, the first power supply wiring and the third power supply wiring are connected to each other, whereby the first and third power supply wirings are mutually connected. There is no fluctuation in the electric potential during the period, and it stabilizes.

According to a third aspect of the semiconductor integrated circuit device of the present invention, a first potential is applied to the large-scale functional block so as to surround the large-scale functional block.
A second power supply wiring is formed, and a second potential is applied to the large-scale functional block so as to surround the large-scale functional block between the large-scale functional block and the first power-supply wiring. Through-holes for connecting the wiring layers by forming the power wiring of the first power wiring and forming one wiring portion of the first power wiring facing each other and the second power wiring by the same wiring layer. The number of ICs can be greatly reduced, and they can be placed on the LSI chip without being restricted by the position and width of the power supply pins of the large-scale functional block.
It is possible to efficiently use the I chip.

According to a fourth aspect of the semiconductor integrated circuit device of the present invention, a first power supply wiring for applying a first potential and a second power supply wiring for applying a second potential to the logic circuit element are provided as first and second power supply wirings. Third parallel wiring layers are formed in parallel with each other, and a third power supply wiring for applying a first potential to the large-scale functional block is formed so as to surround the large-scale functional block. And a third power supply wiring, a fourth power supply wiring for applying a second potential to the large-scale functional block is formed so as to surround the large-scale functional block, and the fourth power supply is formed. A wiring portion of the wiring in a direction different from the first and second power wirings is formed by the first wiring layer, and a wiring portion of the third power wiring in a direction different from the first and second power wirings. Is formed by a second wiring layer different from the first wiring layer And a result, the second power supply wiring,
It is not necessary to form a through hole for connection between wiring layers at the intersection with the fourth power supply wiring. Therefore, the large-scale functional block with power wiring can be arranged on the LSI chip without being restricted by the position and width of the power pin of the large-scale functional block, and the LSI chip can be used efficiently. Will be possible.

According to a fifth aspect of the semiconductor integrated circuit device of the present invention, a first power supply wiring for applying a first potential and a second power supply wiring for applying a second potential to the logic circuit element are provided as first and second power supply wirings. Third parallel wiring layers are formed in parallel with each other, and a third power supply wiring for applying a first potential to the large-scale functional block is formed so as to surround the large-scale functional block. And a third power supply wiring, a fourth power supply wiring for applying a second potential to the large-scale functional block is formed so as to surround the large-scale functional block, and the fourth power supply is formed. A wiring portion of the wiring in the same direction as the first and second power wirings is formed by a second wiring layer different from the first wiring layer, and the first and second wirings of the third power wiring are formed.
The wiring portion in the same direction as that of the power supply wiring is formed by the first wiring layer.
It is not necessary to form a through hole for connecting wiring layers at the intersection with the power supply wiring. Therefore, the large-scale functional block with power wiring can be arranged on the LSI chip without being restricted by the position and width of the power pin of the large-scale functional block, and the LSI chip can be used efficiently. Will be possible.

In the semiconductor integrated circuit device according to a sixth aspect of the present invention, the wiring portion of the fourth power wiring in a direction different from that of the first and second power wirings is formed by the first wiring layer, By forming a wiring portion of the third power supply wiring in a direction different from that of the first and second power supply wirings by the second wiring layer, the second power supply wiring and the fourth power supply wiring can be formed.
It is not necessary to form a through hole for connecting wiring layers at the intersection with the power supply wiring.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit device, the large-scale functional block is provided with the second portion in the wiring portion of the fourth power wiring in a direction different from that of the first and second power wirings. The first and second applying a potential of
The fifth power supply wiring in the same direction as the power supply wiring is formed by the first wiring layer, so that the fourth power supply wiring and the fifth power supply wiring which is the connection wiring are formed in the same wiring layer. Therefore, it is not necessary to form through holes for connecting wiring layers at these intersections.

Further, in the semiconductor integrated circuit device according to the invention of claim 8, from the wiring portion of the fourth power supply wiring in the same direction as the first and second power supply wirings, the second large scale functional block is provided. Forming a fifth power supply wiring in a direction different from that of the first and second power supply wirings to which the potential is applied by the first wiring layer, thereby forming the fourth power supply wiring and the connection wiring. It is possible to configure the power supply wirings 5 in the same wiring layer, and it is not necessary to form through holes for connecting wiring layers at their intersections.

Further, in the semiconductor integrated circuit device according to the invention of a ninth aspect, the large-scale functional block is provided with the first portion in the wiring portion of the third power wiring in a direction different from that of the first and second power wirings. The first and second applying a potential of
By forming the fifth power supply wiring in the same direction as the power supply wiring of No. 2 by the second wiring layer, the third power supply wiring and the fifth power supply wiring which is the connection wiring are formed of the same wiring layer. Therefore, it is not necessary to form through holes for connecting wiring layers at these intersections.

According to a tenth aspect of the invention, in a semiconductor integrated circuit device, the first and second power supply wirings are provided.
The first and second portions for applying the second potential to the large-scale functional block from a wiring portion in the same direction as the power wiring of
The fifth power supply wiring in a direction different from the power supply wiring of
Since the fourth power supply wiring and the fifth power supply wiring, which is a connection wiring, can be formed in the same wiring layer by forming the wiring layer of the above wiring layer, the through wiring for wiring interlayer connection is formed at the intersection of these. There is no need to form holes.

In the semiconductor integrated circuit device according to the invention of claim 11, the first and second power supply wirings are provided.
The second power supply wiring in the same direction as the first and second power supply wirings for applying the second potential to the large-scale functional block from the wiring portion in the direction different from the power supply wiring. Since the fourth power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer, the through-holes for connecting the wiring layers are formed at the intersections thereof. There is no need to do it.

According to a twelfth aspect of the present invention, there is provided a semiconductor integrated circuit device, wherein the first and second power supply wirings are provided.
The first power wiring in a direction different from the first and second power wirings for applying the first potential to the large-scale functional block from the wiring portion in the same direction as the power wiring of the first wiring layer. Since the third power supply wiring and the fifth power supply wiring, which is a connection wiring, can be formed in the same wiring layer, the through holes for wiring interlayer connection are formed at the intersections thereof. There is no need to do it.

According to a thirteenth aspect of the present invention, there is provided a semiconductor integrated circuit device in which the first and second power supply wirings are provided.
The fifth power supply wiring in the same direction as the first and second power supply wirings for applying the second potential to the large-scale functional block from the wiring portion in the direction different from the power supply wiring of the first wiring layer. Since the fourth power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer, the through-holes for connecting the wiring layers are formed at the intersections thereof. There is no need to do it.

According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit device, the first and second power supply wirings are provided.
A second power supply wiring in a direction different from the first and second power supply wirings for applying a second potential to the large-scale functional block from a wiring portion in the same direction as the second power supply wiring. With this structure, the fourth power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer, and through holes for connecting wiring layers are formed in these wirings. There is no need.

According to a fifteenth aspect of the present invention, in the semiconductor integrated circuit device, the first and second power supply wirings are provided.
From the wiring portion in a direction different from that of the power source wiring, the fifth power source wiring in the same direction as the first and second power source wirings for applying the first potential to the large-scale functional block is connected to the second wiring layer. The third power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer, and through holes for wiring interlayer connection are formed at the intersections thereof. There is no need to do it.

According to a sixteenth aspect of the present invention, in the semiconductor integrated circuit device, the first and second power supply wirings are provided.
The first power wiring in a direction different from the first and second power wirings for applying the first potential to the large-scale functional block from the wiring portion in the same direction as the power wiring of the first wiring layer. The third power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer, and through holes for wiring interlayer connection are formed at the intersections thereof. There is no need to do it.

[0045]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 11 is a large-scale functional block, 31
Is an inner ring (first power wiring), 32 is an inner ring (second power wiring)
Power wiring), 33 is an outer ring (third power wiring), 3
Reference numeral 4 is an inter-ring connection wiring that connects the inner ring 31 and the outer ring 33, 35 is a through hole, 36 is a VDD pin, and 37
Is a VSS pin, 38 is a signal pin, 39 is a VDD ring connection wiring (VDD wiring), and 40 is a VSS ring connection wiring (VSS wiring).

Next, the operation will be described. VDD pin 3
6. The VSS pin 37 is provided on each of the left and right sides of the large-scale functional block 11, and the signal pin 38 is provided on each of the upper and lower sides. The inner ring 31 and the outer ring 33 are used as VDD rings, and the middle ring 32 is used as VSS rings.
In the three rings 31 to 33, the vertical wiring is the second-layer metal wiring, and the horizontal wiring is the first-layer metal wiring.
Each is formed. In addition, the ring connection wiring 39,
40 is formed by the first layer metal wiring, and the inter-ring connection wiring 34 is formed by the second layer metal wiring.

FIG. 2 is a block diagram showing an example in which this large-scale functional block with a power ring is mounted on an ECA type LSI. In the figure, 2 is a transistor array and 3 is a VD.
D follow wiring, 4 VSS follow wiring, 14 VDD stripe wiring, 15 VSS wiring, and 17 through holes. The follower wirings 3 and 4 are formed by the first-layer metal wiring, and the stripe wirings 14 and 15 are formed by the second-layer metal wiring. The follow wiring 3 and the stripe wiring 14 of VDD are connected to the outer ring 3 of VDD by the through hole 17.
Connected to 3. The follow wiring 4 and the stripe wiring 15 of the VSS are connected to the VSS through the through hole 17.
Connected to the inner ring 32.

First, the wiring of VDD will be described. Power supply current is supplied to the transistor rows 2 on the left and right of the large-scale functional block 11 through the outer ring 33. Therefore, the width of the outer ring 33 only needs to be wide enough to supply the power supply current required for the operation of these transistor rows 2. Specifically, the stripe wirings 14 and 15
It is enough to have the same width as. This is because the widths and intervals of the stripe wirings 14 and 15 are designed so as to supply the power supply current to the region where the large-scale functional block 11 does not exist and only the transistor row 2 exists. is there. The large-scale functional block includes a route of VDD stripe wiring 14 → horizontal wiring of outer ring 33 → inter-ring connection wiring 34 → horizontal wiring of inner ring 31 → vertical wiring of inner ring 31 → ring connection wiring 39. Supply the power supply current. When the inter-ring connection wiring 34 is laid out so as to correspond to each of the VDD stripe wirings 14, the lateral wiring of the outer ring 33 and the inter-ring connection wiring 34 are similar to the stripe wiring 14. It only needs to have a wiring width. If the wiring interval between the plurality of stripe wirings 14 is known in advance, the inter-ring connecting wiring 34 can be wired before the large-scale functional block 11 is placed on the LSI as shown in FIG. is there. That is, the wiring interval between the ring connection wirings 39 may be made approximately the same as the wiring interval between the stripe wirings 14.

At this time, the distance between the through hole 17 connecting the vertical wiring and the horizontal wiring of the outer ring 33 and the inter-ring connecting wiring 34 provided in the vicinity thereof is also the wiring distance between the stripe wirings 14. With the same degree, the degree of freedom of arrangement of the large-scale functional block 11 on the LSI is no different from that in the case where the inter-ring connection wiring 34 does not exist. The inner ring 31 is laid out with a width sufficient to supply a power supply current required for the large-scale functional block 11 within a range not exceeding the total width of the VDD stripe wirings 14 connected to the outer ring 33. In addition, in FIG. 1 and FIG. 2, the VDD ring connection wiring 39 is connected only to the inner ring 31, but if it is desired to allow a part of the power supply current required for the large-scale functional block 11 to flow to the outer ring 33. , VDD may be extended to the outer ring 33 and the through hole 17 may be arranged at the intersection with the outer ring 33.

Next, the VSS wiring will be described. Both the transistor array 2 on the left and right of the large scale functional block 11 and the large scale functional block 11 are connected to the middle ring 32. The width of the middle ring 32 is equal to that of the large-scale functional block 11.
Since it does not affect the degree of freedom of arrangement on the LSI, the width required for the operation of both the transistor array 2 and the large-scale functional block 11 can be freely set.

As described above, according to the semiconductor integrated circuit device of this embodiment, the LS of the large-scale functional block is larger than that of the power ring system which is conventionally applied to the large-scale functional block.
The degree of freedom of arrangement on the I can be increased, and an LSI having an area efficiency higher than the conventional one can be realized.

Example 2. FIG. 3 is a diagram showing another embodiment of the present invention. This semiconductor integrated circuit device is different from the first embodiment in that the VDD pins 36 are provided on the upper and lower sides instead of the left and right sides. In this case, the path through which the VDD power supply current is supplied to the large-scale functional block 11 is V
The DD stripe wiring 14 → the lateral wiring of the outer ring 33 → the inter-ring connecting wiring 34 → the lateral wiring of the inner ring 31 → the ring connecting wiring 39. In this device, since the vertical wiring of the inner ring 31 is not included in the path, the inner ring 31
The wiring width of the vertical wiring can be made narrower than that of the first embodiment, and an LSI having a higher degree of integration than that of the first embodiment can be realized. The degree of freedom of arrangement of the large-scale functional block 11 is the same as that of the device of the first embodiment.

The semiconductor integrated circuit device according to the first and second embodiments is not limited to the above-described first and second embodiments, and various modifications can be made. For example, the relationship between VDD and VSS may be reversed. In addition, in the first and second embodiments, VDD
Is the "power supply potential" and VSS is the "ground potential".
The absolute values of those potentials can be set arbitrarily. Also,
In the first and second embodiments, the horizontal wiring is basically realized by the first-layer metal wiring and the vertical wiring is realized by the second-layer metal wiring, but the present invention does not limit the realized wiring layer. Absent. Furthermore, in the first and second embodiments, the large-scale functional block 11 is surrounded by the triple power supply rings 31 to 33.
The same effect can be brought about by constructing the power supply ring of four layers (or more than that).
In the above-mentioned Embodiments 1 and 2, the ECA type LSI has been described as an example, but the gate array and the standard cell type L
The same can be applied to SI.

Example 3. Hereinafter, another embodiment of the present invention will be described with reference to the drawings. In FIG. 4, 51 is a large-scale functional block, 52 is an inner ring (fourth power supply wiring), 53 is an outer ring (third power supply wiring), 54 and 55 are ring connection wirings, 56 is a through hole, and 57 is a VDD is a VDD pin, 58 is a VSS pin, and 59 is a signal pin.

In this semiconductor integrated circuit, VDD pin 5 is used.
7. The VSS pin 58 is provided on each of the left and right sides of the large-scale functional block 51, and the signal pin 59 is provided on each of the upper and lower sides. The inner ring 52 is used as a VSS ring and the outer ring 53 is used as a VDD ring. Inner ring 52
Both the vertical wiring and the horizontal wiring are formed by the first layer metal wiring, and the outer ring 53 is formed by the vertical wiring by the second layer metal wiring and the horizontal wiring by the first layer metal wiring. . The ring connection wiring 54 connecting the inner ring 52 and the VSS pin 58 is the first layer metal wiring, and the ring connection wiring 5 connecting the outer ring 53 and the VDD pin 57 is formed.
Reference numeral 5 is formed by the second layer metal wiring. The through hole 56 connecting the metal wiring layers is formed by the outer ring 5.
It suffices if it is only at the intersection of the vertical wiring and the horizontal wiring of 3.

FIG. 5 is a block diagram showing an example in which the large-scale functional block with the power supply ring is mounted on an ECA type LSI, and the follow wirings 3 and 4 are the first layer metal wiring and the stripe wiring 14, Reference numeral 15 is formed by the second layer metal wiring.

First, the follow wirings 3 and 4 and the power supply ring 5
The connection with 2, 53 will be described. The follow wiring VDD (first layer metal wiring) 3 and the VDD outer ring (second layer metal wiring) 53 are connected by arranging a through hole 56 at the intersection of the two. The through hole 56 can be arranged without being restricted by the VSS wiring or the like, regardless of where on the vertical wiring of the outer ring 53 the VDD follow wiring 3 comes. Further, when this position corresponds to the intersection of the vertical wiring and the horizontal wiring of the outer ring 53, the through hole 56 already exists,
It is not necessary to form a through hole again. Also, V
Since the SS follow-up wiring (first-layer metal wiring) 4 and the VSS inner ring (first-layer metal wiring) 52 use the same wiring layer, it is necessary to form the through hole 56 for connecting the two. Absent. Therefore, even if the VDD ring connection wiring (second-layer metal wiring) 55 exists at the connection point between them, VDD and VSS will not be short-circuited.

Next, the connection between the stripe wirings 14 and 15 and the power supply rings 52 and 53 will be described. VDD,
Stripes wiring (second layer metal wiring) 1 for both VSS
The horizontal wirings (first-layer metal wirings) of the power supply rings 52, 53 and the wirings 4, 15 are connected by arranging through holes 56 at the intersections of the two. Since the VDD pin 57 and the VSS pin 58 do not exist on the upper and lower sides of the large-scale functional block 51, the ring connection wiring is not wired between the horizontal wiring of the power supply ring and the large-scale module. Therefore,
Even if both the horizontal components of the inner ring 52 and the outer ring 53 are formed by the first-layer metal wiring, the wirings of VDD and VSS do not become inconsistent. Also, large-scale functional block 5
The signal pins 59 existing on the upper and lower sides of 1 can be easily connected to other logic circuits by wiring outside the power ring using the second layer metal wiring.

As described above, according to the semiconductor integrated circuit device of the third embodiment, the degree of freedom of arrangement on the large-scale functional block LSI can be increased as compared with the conventional one.
Therefore, it is possible to realize an LSI having a higher area efficiency than the conventional one. In addition, it is possible to reduce manual work when automatic placement and wiring is performed using a CAD tool, and there is an effect that design efficiency is improved.

Example 4. FIG. 6 is a diagram showing another embodiment of the present invention. This semiconductor integrated circuit device differs from that of the third embodiment in that V is provided on each of the upper and lower sides of the large-scale functional block 51.
A DD pin 57 and a VSS pin 58 are provided, and a signal pin 59 is provided on each of the left and right sides. here,
Inner ring 52 is VSS ring, outer ring 53 is VDD
Used as a ring. The inner ring 52 is composed of the second-layer metal wiring in both the vertical wiring and the horizontal wiring, and the outer ring 53 is composed of the vertical wiring in the second-layer metal wiring and the horizontal wiring in the first-layer metal wiring. ing. Also, the inner ring 52
The ring connection wiring connecting the VSS pin 58 and the VSS pin 58 is a second layer metal wiring, and the ring connection wiring connecting the outer ring 53 and the VDD pin 57 is a first layer metal wiring. The through hole 56 connecting the metal wiring layers is formed with the outer ring 53.
It only needs to be at the intersection of the vertical wiring and the horizontal wiring.

FIG. 7 is a block diagram showing an example in which the large-scale functional block with a power ring is mounted on a standard cell type LSI. First, the stripe wiring 14, 1
The connection between the power supply ring 5 and the power supply rings 52 and 53 will be described.
VDD stripe wiring (second layer metal wiring) 14 and V
The outer ring (first layer metal wiring) 53 of the DD is connected by disposing a through hole 56 at the intersection of the two. No matter which position on the lateral wiring of the outer ring 53 the VDD stripe wiring 14 comes in, this through hole 56
Can be arranged without being restricted by VSS wiring or the like. When this position corresponds to the intersection of the vertical wiring and the horizontal wiring of the outer ring 53, the through hole 56 already exists, and therefore it is not necessary to arrange the through hole again. Further, since the VSS stripe wiring (second-layer metal wiring) 15 and the VSS inner ring (second-layer metal wiring) 52 use the same wiring layer, through holes are arranged to connect them. No need. Therefore, even if the VDD ring connection wiring (first-layer metal wiring) 55 exists at the connection point of both, VDD and VS
S will never short.

Next, the follow wirings 3 and 4 and the power supply ring 5
The connection with 2, 53 will be described. For both VDD and VSS, the follow wirings (first layer metal wirings) 3 and 4 and the vertical wirings (second layer metal wirings) of the power supply rings 52 and 53 are connected by arranging through holes 56 at the intersections of the two. . Since the VDD pin 57 and the VSS pin 58 do not exist on the left and right sides of the large-scale functional block 51, the ring connection wiring is not wired between the vertical wiring of the power ring and the large-scale module. Therefore, even if both the vertical components of the inner ring 52 and the outer ring 53 are formed by the second-layer metal wiring, there is no contradiction in the wirings of VDD and VSS. Further, the signal pins 59 existing on the left and right sides of the large-scale functional block 51 can be easily connected to other logic circuits by wiring them to the outside of the power supply rings 52 and 53 using the first layer metal wiring. .

As described above, the semiconductor integrated circuit of the fourth embodiment also has the same effect as that of the third embodiment, and an LSI having a high area efficiency can be realized.

Example 5. FIG. 8 is a diagram showing another embodiment of the present invention. This semiconductor integrated circuit device is the third embodiment.
4 is that the VDD pin 57, the VSS pin 58, and the signal pin 59 are provided on each of the upper and lower sides and the left and right sides of the large-scale functional block 51. In this semiconductor integrated circuit device, the vertical wiring of the inner ring 52 and the outer ring 5 are
The horizontal wiring of No. 3 is composed of the first layer metal wiring, and the horizontal wiring of the inner ring 52 and the vertical wiring of the outer ring 53 are the second wiring.
It is composed of layer metal wiring.

In this case, as shown in FIG. 9, the relationship between the large-scale functional block 51 with the power ring and the follow wirings 3 and 4 is the same as that of the third embodiment, and the stripe wirings 14 and 1 are the same.
Since the relationship with the fifth embodiment is the same as that of the fourth embodiment, the large-scale functional block 51, like the large-scale functional blocks of the third and fourth embodiments, is restricted by the position / width of the power supply pin of the large-scale functional block. It can be placed on the LSI chip without receiving it, and the LSI chip can be used efficiently. When the signal pins 59 are present on the upper and lower sides, the wiring between the inner ring 52 and the outer ring 53 is performed by the first layer metal wiring, and from there, the wiring is performed by the second layer metal wiring to the outside of the outer ring 53. The signal pin 59 can be connected to another logic circuit. Similarly, when the signal pins 59 are present on the left and right sides, the wiring between the inner ring 52 and the outer ring 53 is performed by the second-layer metal wiring, and then the wiring is performed by the first-layer metal wiring to the outside of the outer ring 53. As a matter of fact, this signal pin 59 can be connected to another logic circuit. When the number of metal wiring layers that can be used for wiring is three or more, the signal pins 59 on the upper and lower sides and the signal pins 5 on the right and left sides are provided.
9 can be similarly formed by using the third-layer metal wiring (or the metal wiring in the upper layer).

In the third embodiment, it is assumed that only the signal pins 59 exist on the upper and lower sides, but VS on the upper and lower sides.
The S pin 58 may be present. In this case, VS
Regardless of the position of the S pin 58, if the ring connection wiring is wired by using the first layer metal wiring, the degree of freedom of arrangement on the LSI does not change. The same applies to the fourth embodiment, and the VSS pins 58 may exist on the left and right sides. In this case, regardless of the position of the VSS pin 58, the second pin
If the ring connection wiring is wired using the layer metal wiring,
The degree of freedom of arrangement on I does not change.

Further, in the formula embodiments 3 to 5, the present invention is not limited to the illustrated configuration, and for example, VD
The relationship between D and VSS or the relationship between the first-layer metal wiring and the second-layer metal wiring may be reversed. In the above Examples 3 to 5, V
Although DD is "power supply potential" and VSS is "ground potential", the absolute values of these potentials are arbitrary. When the number of metal wiring layers that can be used for wiring is three or more, the present invention can be applied between any two layers. Further, although the above embodiments 3 to 5 have been described by using the ECA as an example, the same can be applied to the gate array and the standard cell type LSI.

[0068]

As described above, according to the first aspect of the invention, the first power supply wiring for applying the first potential to the large-scale functional block is provided so as to surround the large-scale functional block. And forming a second power supply line for applying a second potential to the large-scale functional block so as to surround the first power supply line and surround the second power supply line. Since the third power supply line for applying the first potential is formed in the large-scale functional block, the width of the third power supply line can be narrowed, and the large-scale function on the LSI chip can be achieved. The degree of freedom in arranging blocks can be increased, and an LSI having a high area efficiency can be realized.

According to the invention of claim 2, the first
Since the power source wiring and the third power source are connected to each other, the potential variation between these power source wirings can be eliminated and there is an effect of stabilizing.

According to the invention of claim 3, a first power supply line for applying a first potential to the large-scale functional block is formed so as to surround the large-scale functional block. A second power supply line for applying a second potential to the large-scale functional block is formed between the large-scale functional block and the first power-supply wiring so as to surround the large-scale functional block.
Since one wiring portion of the first power supply wiring facing each other and the second power supply wiring are formed by different wiring layers, the number of through holes for connecting the wiring layers is large. Therefore, the large-scale functional block can be arranged on the LSI chip without being restricted by the position and width of the power supply pin.
There is an effect that the I chip can be used efficiently.

According to the invention of claim 4, the wiring portion of the fourth power wiring in a direction different from the first and second power wirings is formed by the first wiring layer, and the third wiring layer is formed by the third wiring layer.
Since the wiring portion of the power supply wiring in the direction different from the first and second power supply wirings is formed by the second wiring layer different from the first wiring layer, There is no need to form a through hole for connecting the wiring layers at the intersection with the fourth power wiring, so that the large-scale functional block can be mounted on the LSI chip without being restricted by the position and width of the power pin. It can be arranged, and there is an effect that the LSI chip can be efficiently used.

According to the invention of claim 5, a wiring portion of the fourth power wiring in the same direction as the first and second power wirings is a second wiring layer different from the first wiring layer. And the wiring portion of the third power supply wiring in the same direction as the first and second power supply wirings is formed by the first wiring layer. It is not necessary to form a through hole for connecting the wiring layers at the intersection with the third power wiring, so that the large-scale functional block can be mounted on the LSI chip without being restricted by the position and width of the power pin. Can be placed, LS
There is an effect that the I chip can be used efficiently.

According to the invention of claim 6, the fourth
A wiring portion of the power supply wiring in a direction different from that of the first and second power supply wirings is formed by the first wiring layer, and has a direction different from that of the first and second power supply wirings of the third power supply wiring. Since the wiring portion is configured to be formed by the second wiring layer, it is not necessary to form a through hole for wiring interlayer connection at the intersection of the second power wiring and the fourth power wiring. There is an effect that a large-scale functional block can be arranged on an LSI chip without being restricted by the positions of these through holes.

According to the invention of claim 7, the fourth
A fifth portion of the power supply wiring in the same direction as the first and second power supply wirings that applies the second potential to the large-scale functional block from a wiring portion in a direction different from the first and second power supply wirings. Since the power supply wiring is formed by the first wiring layer, the fourth power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer. There is no need to form through holes for connecting wiring layers at intersections, and there is an effect that a large-scale functional block can be arranged on an LSI chip without being restricted by the positions of these through holes.

According to the invention of claim 8, the fourth
A part of the power supply wiring in the same direction as the first and second power supply wirings, and a fifth direction in a direction different from the first and second power supply wirings for applying the second potential to the large-scale functional block. Since the power supply wiring is formed by the first wiring layer, the fourth power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer. There is no need to form through holes for connecting wiring layers at intersections, and there is an effect that a large-scale functional block can be arranged on an LSI chip without being restricted by the positions of these through holes.

According to the invention of claim 9, the third
The fifth power supply wiring, which is in the same direction as the first and second power supply wirings and applies the first potential to the large-scale functional block, from the wiring portion of the power supply wiring in the different direction from the first and second power supply wirings. Since the power supply wiring is formed by the second wiring layer, the third power supply wiring and the fifth power supply wiring, which is the connection wiring, can be formed in the same wiring layer. There is no need to form through holes for connecting wiring layers at intersections, and there is an effect that a large-scale functional block can be arranged on an LSI chip without being restricted by the positions of these through holes.

According to the tenth aspect of the invention, the second potential is applied to the large-scale functional block from the wiring portion of the fourth power wiring in the same direction as the first and second power wirings. Since the fifth power supply wiring in the direction different from the applied first and second power supply wirings is formed by the second wiring layer, the fourth power supply wiring and the connection wiring The power supply wiring of No. 5 can be configured in the same wiring layer, and it is not necessary to form through holes for connecting wiring layers at the intersections thereof, and the scale is large without being restricted by the positions of these through holes. There is an effect that the functional block can be arranged on the LSI chip.

According to the eleventh aspect of the invention, the second potential is applied to the large-scale functional block from the wiring portion of the fourth power wiring in a direction different from that of the first and second power wirings. Since the fifth power supply wiring in the same direction as the first and second power supply wirings is formed by the second wiring layer, the fourth power supply wiring and the connection wiring Power supply wiring can be configured in the same wiring layer, and it is not necessary to form through holes for wiring layer connection at these intersections, and large-scale functions can be performed without being restricted by the positions of these through holes. There is an effect that the blocks can be arranged on the LSI chip.

According to the twelfth aspect of the invention, the first potential is applied to the large-scale functional block from the wiring portion of the third power wiring in the same direction as the first and second power wirings. Since the fifth power supply wiring in the direction different from that of the first and second power supply wirings is formed by the first wiring layer, the third power supply wiring and the connection wiring Power supply wiring can be configured in the same wiring layer, and it is not necessary to form through holes for wiring layer connection at these intersections, and large-scale functions can be performed without being restricted by the positions of these through holes. There is an effect that the blocks can be arranged on the LSI chip.

According to the thirteenth aspect of the invention, the second potential is applied to the large-scale functional block from the wiring portion of the fourth power wiring in a direction different from that of the first and second power wirings. Since the fifth power supply wiring in the same direction as the first and second power supply wirings is formed by the first wiring layer, the fourth power supply wiring and the connection wiring Power supply wiring can be configured in the same wiring layer, and it is not necessary to form through holes for wiring layer connection at these intersections, and large-scale functions can be performed without being restricted by the positions of these through holes. There is an effect that the blocks can be arranged on the LSI chip.

According to the fourteenth aspect of the invention, the second potential is applied to the large-scale functional block from the wiring portion of the fourth power wiring in the same direction as the first and second power wirings. Since the fifth power supply wiring in the direction different from that of the first and second power supply wirings is formed by the second wiring layer, the fourth power supply wiring and the connection wiring Power supply wiring can be configured in the same wiring layer, and it is not necessary to form through holes for wiring layer connection at these intersections, and large-scale functions can be performed without being restricted by the positions of these through holes. There is an effect that the blocks can be arranged on the LSI chip.

According to the fifteenth aspect of the invention, the first potential is applied to the large-scale functional block from a wiring portion of the third power supply wiring in a direction different from that of the first and second power supply wirings. Since the fifth power supply wiring in the same direction as the first and second power supply wirings is formed by the second wiring layer, the third power supply wiring and the connection wiring Power supply wiring can be configured in the same wiring layer, and it is not necessary to form through holes for wiring layer connection at these intersections, and large-scale functions can be performed without being restricted by the positions of these through holes. There is an effect that the blocks can be arranged on the LSI chip.

According to the sixteenth aspect of the present invention, the first potential is applied to the large-scale functional block from the wiring portion of the third power supply wiring in the same direction as the first and second power supply wirings. Since the fifth power supply wiring in the direction different from that of the first and second power supply wirings is formed by the first wiring layer, the third power supply wiring and the connection wiring Power supply wiring can be configured in the same wiring layer, and it is not necessary to form through holes for wiring layer connection at these intersections, and large-scale functions can be performed without being restricted by the positions of these through holes. There is an effect that the blocks can be arranged on the LSI chip.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a large-scale functional block with a power supply ring according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example in which a large-scale functional block with a power ring according to the first embodiment of the present invention is mounted on an LSI.

FIG. 3 is a configuration diagram showing a large-scale functional block with a power ring according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing a large-scale functional block with a power supply ring according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram showing an example in which a large-scale functional block with a power ring according to the third embodiment of the present invention is mounted on an LSI.

FIG. 6 is a configuration diagram showing a large-scale functional block with a power supply ring according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram showing an example in which a large-scale functional block with a power ring according to a fourteenth embodiment of the present invention is mounted on an LSI.

FIG. 8 is a configuration diagram showing a large-scale functional block with a power ring according to a fifth embodiment of the present invention.

FIG. 9 is a configuration diagram showing an example in which a large-scale functional block with a power ring according to a fifth embodiment of the present invention is mounted on an LSI.

FIG. 10 is a configuration diagram showing a transistor array and power supply wiring of a conventional gate array.

FIG. 11 is a plan view showing an example in which a conventional large-scale functional block with a power ring is mounted on an LSI.

12 is a partially enlarged plan view showing a large-scale functional block portion with a power ring of FIG.

FIG. 13 is a partially enlarged plan view showing another example of a conventional large-scale functional block portion with a power ring.

[Explanation of symbols]

 3,4 Follow wiring (power supply wiring) 11,51 Large-scale functional block 31 Inner ring (first power supply wiring) 32 Middle ring (second power supply wiring) 33 Outer ring (third power supply wiring) 34 Inter-ring connection Wiring 52 Inner ring (4th power supply wiring) 53 Outer ring (3rd power supply wiring)

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[Procedure amendment]

[Submission date] October 26, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 5

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

According to a fifth aspect of the semiconductor integrated circuit device of the present invention, a first power supply wiring for applying a first potential and a second power supply for applying a second potential to the logic circuit element. Wirings are formed in parallel with each other by the first wiring layer, and a third power supply wiring for applying the first potential to the large-scale functional block is formed so as to surround the large-scale functional block. A fourth power supply wiring for applying a second potential to the large-scale functional block is formed between the large-scale functional block and the third power-supply wiring so as to surround the periphery of the large-scale functional block. The first potential is applied to the first and third power supply wirings.
Power supply wiring for applying a voltage, and the second and fourth power supplies
The sixth power supply wiring for applying the second potential to the wiring is
The first wiring layer in a direction different from that of the first and second power supply wirings
More formed on different second formed by the wiring layer, the fifth and sixth power supply lines and different direction, that each other in a direction parallel to the wiring portion of the fourth power supply wiring and the second wiring layer and The wiring portion of the third power supply wiring in a direction different from the fifth and sixth power supply wirings, that is, in a direction parallel to each other is formed by the first wiring layer.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

According to a fifth aspect of the semiconductor integrated circuit device of the present invention, a first power supply wiring for applying a first potential and a second power supply wiring for applying a second potential to the logic circuit element are provided as first and second power supply wirings. Second parallel wiring layers are formed in parallel with each other, and a third power supply wiring for applying a first potential to the large-scale functional block is formed so as to surround the large-scale functional block. And a third power supply wiring, a fourth power supply wiring for applying a second potential to the large-scale functional block is formed so as to surround the large-scale functional block, and
A fifth potential applying first potential to the first and third power supply wirings
A power supply line and a second potential on the second and fourth power supply lines
A sixth power supply line for applying a voltage to the first and second power supplies.
A second wiring different from the first wiring layer in a direction different from the wiring
A wiring layer, and the fifth and fifth power supply wirings are formed .
The wiring portion in a direction different from the sixth power source line more formed on said second wiring layer, the fifth and the third power supply wiring
By forming the power distribution portion in the direction different from that of the sixth power wiring by the first power distribution layer, a through hole for wiring interlayer connection is formed at the intersection of the sixth power wiring and the fourth power wiring. There is no need to form. Therefore, the large-scale functional block with power wiring can be connected to the LS without being restricted by the position and width of the power pin of the large-scale functional block.
It can be arranged on the I chip, and the LSI chip can be efficiently used.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction content]

According to a twelfth aspect of the present invention, there is provided a semiconductor integrated circuit device, wherein the first and second power supply wirings are provided.
The first power wiring in a direction different from the first and second power wirings for applying the first potential to the large-scale functional block from the wiring portion in the same direction as the power wiring of the first wiring layer. The third power supply wiring and the fifth power supply wiring, which is a connection wiring, are formed in the same wiring layer
Therefore, it is not necessary to form through holes for connecting wiring layers at these intersections.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0072

[Correction method] Change

[Correction content]

According to the invention of claim 5, the first and second
And a fifth power supply for applying the first potential to the third power supply wiring.
Applying a second potential to the line and the second and fourth power supply wirings
And a sixth power supply wiring for the first and second power supply wirings
A second wiring layer different from the first wiring layer in a different direction
Formed by the fifth and sixth power supply lines and different direction of the wiring portion of the fourth power supply wiring is formed from <br/> to said second wiring layer, said third power supply wiring 5th and 6th
Since the wiring portion in the direction different from that of the power supply wiring is formed by the first wiring layer, the through portion for connecting the wiring layers to the intersection of the first power supply wiring and the third power supply wiring is formed. Since it is not necessary to form a hole, the large-scale functional block can be arranged on the LSI chip without being restricted by the position and width of the power supply pin, and the LSI chip can be used efficiently. effective.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 13

[Correction method] Change

[Correction content]

[Fig. 13]

Claims (16)

[Claims] 1. In a semiconductor integrated circuit device having at least one large-scale functional block, a first large-scale functional block is provided so as to surround the large-scale functional block.
Forming a first power supply wiring for applying the second potential, and forming a second power supply wiring for applying the second potential to the large-scale functional block so as to surround the first power supply wiring. A semiconductor integrated circuit device, comprising: a third power supply line for applying the first potential to the large-scale functional block so as to surround the second power supply line. 2. The semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring and the third power supply wiring are connected to each other. 3. A semiconductor integrated circuit device having at least one large-scale functional block, wherein the large-scale functional block has a first portion so as to surround the periphery of the large-scale functional block.
Forming a first power supply wiring for applying the potential of the second power supply wiring to the second large-scale functional block so as to surround the large-scale functional block between the large-scale functional block and the first power-supply wiring. Forming a second power supply line for applying a potential of
2. The semiconductor integrated circuit device according to claim 1, wherein one of the power supply wirings facing each other and the second power supply wiring are formed of the same wiring layer. 4. A semiconductor integrated circuit device having a plurality of logic circuit elements having the same height and a large-scale functional block higher than the logic circuit elements, wherein a first potential is applied to the logic circuit element. The power supply wiring and the second power supply wiring for applying the second potential are formed in parallel with each other by the first wiring layer, and the first large-scale functional block is provided with the first power-supply wiring so as to surround the periphery of the large-scale functional block. A third power supply line for applying a potential is formed, and a second power supply line is formed on the large scale function block so as to surround the large scale function block between the large scale function block and the third power supply line. A fourth power supply line for applying a potential is formed, and a wiring portion of the fourth power supply line in a direction different from that of the first and second power supply lines is formed by the first wiring layer and the third power supply line is formed. Direction of power supply wiring different from the first and second power supply wirings 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring portion is formed of a second wiring layer different from the first wiring layer. 5. A semiconductor integrated circuit device having a plurality of logic circuit elements having the same height and a large-scale functional block higher than the logic circuit elements, wherein a first potential is applied to the logic circuit element. The power supply wiring and the second power supply wiring for applying the second potential are formed in parallel with each other by the first wiring layer, and the first large-scale functional block is provided with the first power-supply wiring so as to surround the periphery of the large-scale functional block. A third power supply line for applying a potential is formed, and a second power supply line is formed on the large scale function block so as to surround the large scale function block between the large scale function block and the third power supply line. A fourth power supply line for applying a potential is formed, and a wiring portion of the fourth power supply line in the same direction as the first and second power supply lines is formed by a second wiring layer different from the first wiring layer. Is formed, and the first and second power lines of the third power wiring are formed. A semiconductor integrated circuit device, wherein a wiring portion in the same direction as the source wiring is formed by the first wiring layer. 6. The first and second of the fourth power supply wiring
A wiring portion in a direction different from that of the power supply wiring is formed by the first wiring layer, and a wiring portion of the third power supply wiring in a direction different from the first and second power supply wirings is formed by the second wiring layer. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is formed. 7. The first and second of the fourth power supply wiring
The fifth power supply line in the same direction as the first and second power supply lines for applying the second potential to the large-scale functional block from the wiring part in the direction different from the power supply line
5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is formed of the wiring layer. 8. The first and second of the fourth power supply wiring
The first and second portions for applying the second potential to the large-scale functional block from a wiring portion in the same direction as the power wiring of
The fifth power supply wiring in a direction different from the power supply wiring of
5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is formed of the wiring layer. 9. The first and second of the third power supply wiring
The second power supply wiring in the same direction as the first and second power supply wirings for applying the first potential to the large-scale functional block from the wiring portion in the direction different from the power supply wiring
5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is formed of the wiring layer. 10. The first and second portions for applying the second potential to the large-scale functional block from a wiring portion of the fourth power wiring in the same direction as the first and second power wirings. 6. The semiconductor integrated circuit device according to claim 5, wherein a fifth power supply wiring in a direction different from that of the power supply wiring is formed by the second wiring layer. 11. The first and second applying a second potential to the large-scale functional block from a wiring portion of the fourth power supply wiring in a direction different from the first and second power supply wirings.
6. The semiconductor integrated circuit device according to claim 5, wherein a fifth power supply wiring in the same direction as the power supply wiring is formed by the second wiring layer. 12. The first and second power supplies for applying a first potential to the large-scale functional block from a wiring portion of the third power supply wiring in the same direction as the first and second power supply wirings. The semiconductor integrated circuit device according to claim 5, wherein a fifth power supply wiring in a direction different from that of the wiring is formed by the first wiring layer. 13. The first and second applying a second potential to the large-scale functional block from a wiring portion of the fourth power supply wiring in a direction different from the first and second power supply wirings.
7. The semiconductor integrated circuit device according to claim 6, wherein a fifth power supply wiring in the same direction as said power supply wiring is formed by said first wiring layer. 14. The first and second power supplies for applying a second potential to the large-scale functional block from a wiring portion of the fourth power supply wiring in the same direction as the first and second power supply wirings. 7. The semiconductor integrated circuit device according to claim 6, wherein a fifth power supply wiring in a direction different from that of the wiring is formed by the second wiring layer. 15. The first and second portions for applying a first potential to the large-scale functional block from a wiring portion of the third power wiring in a direction different from the first and second power wirings.
7. The semiconductor integrated circuit device according to claim 6, wherein a fifth power supply wiring in the same direction as said power supply wiring is formed by said second wiring layer. 16. The first and second power supplies for applying a first potential to the large-scale functional block from a wiring portion of the third power supply wiring in the same direction as the first and second power supply wirings. 7. The semiconductor integrated circuit device according to claim 6, wherein a fifth power supply wiring in a direction different from that of the wiring is formed by the first wiring layer.