JPH0729644Y2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0729644Y2 JPH0729644Y2 JP5129089U JP5129089U JPH0729644Y2 JP H0729644 Y2 JPH0729644 Y2 JP H0729644Y2 JP 5129089 U JP5129089 U JP 5129089U JP 5129089 U JP5129089 U JP 5129089U JP H0729644 Y2 JPH0729644 Y2 JP H0729644Y2
- Authority
- JP
- Japan
- Prior art keywords
- connecting lead
- spring mechanism
- lead portion
- lower substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Connections Arranged To Contact A Plurality Of Conductors (AREA)
- Combinations Of Printed Boards (AREA)
Description
【考案の詳細な説明】 〈産業上の利用分野〉 本考案は、パツケージを小型化するために上側基板およ
び下側基板が二段重ねされた半導体装置に関し、特にそ
のパツケージの膨張、収縮時に上側基板および下側基板
に加わる応力を吸収するばね機構を備えたタブ端子を利
用した半導体装置に係る。DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a semiconductor device in which an upper substrate and a lower substrate are stacked in two stages in order to miniaturize a package, and in particular, when the package expands or contracts, The present invention relates to a semiconductor device using a tab terminal provided with a spring mechanism that absorbs stress applied to a substrate and a lower substrate.
〈従来技術〉 従来、電力用半導体装置において、パツケージを小型化
にする方法として、二枚の基板を二段重ねにする構造に
より小型化を図つていた。この上側基板および下側基板
の接続手段として、タブ端子を利用していた。<Prior Art> Conventionally, in a power semiconductor device, as a method of miniaturizing a package, miniaturization has been achieved by a structure in which two substrates are stacked in two stages. Tab terminals have been used as connecting means for the upper and lower substrates.
このタブ端子Ｆは、第4,5図の如く、パツケージの膨
張、収縮時に上側基板および下側基板に加わる応力を吸
収するばね機構１を備えており、外部に熱を放熱する平
板部２と、下側基板に接続さればね機構１を有する下側
基板接続用リード部３と、上側基板に接続される上側基
板接続用リード部４とから構成され、下側基板接続用リ
ード部３が平板部２の側端下部より延設され、上側基板
接続用リード部４が下側基板接続用リード部３の一部よ
り延設されている。As shown in FIGS. 4 and 5, the tab terminal F includes a spring mechanism 1 that absorbs stress applied to the upper and lower substrates when the package expands and contracts, and a flat plate portion 2 that radiates heat to the outside. , A lower substrate connecting lead portion 3 connected to the lower substrate and having a spring mechanism 1, and an upper substrate connecting lead portion 4 connected to the upper substrate, the lower substrate connecting lead portion 3 being a flat plate. An upper substrate connecting lead portion 4 is extended from a lower portion of a side end of the portion 2, and an upper substrate connecting lead portion 4 is extended from a part of the lower substrate connecting lead portion 3.
〈考案が解決しようとする課題〉 上記従来の上下基板接続用タブ端子Ｆの形状で、パツケ
ージが膨張、収縮する際に加わる応力と、接続用リード
部３のばね機構１の長さとの関係について説明する。な
お、ばね機構１の前述の如くその形状が複雑であるの
で、第６図に示す片持ちばりの場合のばねの長さｌと、
そのばねに加わる力との関係について説明する。<Problems to be Solved by the Invention> Regarding the relationship between the stress applied when the package expands and contracts and the length of the spring mechanism 1 of the connecting lead portion 3 in the shape of the above-mentioned conventional upper and lower substrate connecting tab terminals F. explain. Since the shape of the spring mechanism 1 is complicated as described above, the length l of the spring in the case of the cantilever shown in FIG.
The relationship with the force applied to the spring will be described.
第６図の如く、長さｌでａ点が固定されている片持ちば
りのばねにおいて、ｂ点がｙだけ変位したときのばねに
加わる力Ｗは、次式のように表わされる。As shown in FIG. 6, in a cantilevered spring having a length a and a point fixed, the force W applied to the spring when the point b is displaced by y is expressed by the following equation.
Ｗ＝3E・Ｉ・y/l3（E:縦弾性係数、I:断面二次モーメン
ト） この式から分かるように、ばねに加わる力Ｗは、ばねの
長さｌの３乗に反比例しており、ばねの長さｌが長いほ
どばねに加わる力Ｗが小さくなる。W = 3E · I · y / l 3 (E: modulus of longitudinal elasticity, I: second moment of area) As can be seen from this equation, the force W applied to the spring is inversely proportional to the cube of the length l of the spring. Therefore, the longer the spring length l, the smaller the force W applied to the spring.
これは、第4,5図の形状を有するタブ端子Ｆのばね機構
１にもいえ、ばね機構１の一部である１の長さを長く
した方がパッケージの膨張、収縮によるばね機構１に加
わる応力が小さくなる。This is also true for the spring mechanism 1 of the tab terminal F having the shape shown in FIGS. The applied stress becomes small.
したがつて、従来のタブ端子Ｆのばね機構１に加わる応
力を小さくしようとすると、上側基板接続用リード部４
が下側基板接続用リード部３より延設されているため、
ばね機構１が１だけしかない。Therefore, if it is attempted to reduce the stress applied to the spring mechanism 1 of the conventional tab terminal F, the upper substrate connecting lead portion 4
Is extended from the lower board connecting lead portion 3,
There is only one spring mechanism 1.
しかし、タブ端子Ｆの周辺部のスペースが制限されてい
る場合は、ばね機構１の延長部分１の長さをあまり長
くできないので、パツケージの膨張、収縮のばねに加わ
る応力を小さくすることが困難となる。また、パツケー
ジの膨張、収縮時のばね機構１に加わる応力が大きい
と、下側基板接続用リード部３の半田付け片５および半
田付け片５と下側基板との半田付け部に応力が加わり、
信頼性の面で問題が生じる。However, when the space around the tab terminal F is limited, the length of the extension portion 1 of the spring mechanism 1 cannot be increased so much that it is difficult to reduce the stress applied to the spring for expanding and contracting the package. Becomes Further, if the stress applied to the spring mechanism 1 when the package expands and contracts is large, stress is applied to the soldering piece 5 of the lower board connecting lead portion 3 and the soldering section between the soldering piece 5 and the lower board. ,
There is a reliability problem.
そこで、本考案は、上記課題に鑑み、パツケージの膨
張、収縮時に上下の基板に加わる応力を吸収するばね機
構の機能をより効果的に発揮させ、ばね機構に加わる応
力を減少させ信頼性を向上させることができるタブ端子
を利用した半導体装置の提供を目的とする。Therefore, in view of the above problems, the present invention more effectively exerts the function of the spring mechanism that absorbs the stress applied to the upper and lower substrates when the package expands and contracts, and reduces the stress applied to the spring mechanism to improve reliability. An object of the present invention is to provide a semiconductor device using a tab terminal that can be turned on.
〈課題を解決するための手段〉 本考案による課題解決手段は、第１図ないし第３図の如
く、パツケージを小型化するために上側基板10および下
側基板11が二段重ねされた半導体装置において、前記パ
ツケージの膨張、収縮時に上側基板10および下側基板11
に加わる応力を吸収するばね機構１を備えたタブ端子Ｆ
であつて、外部に熱を放熱する平板部２と、前記下側基
板11に接続さればね機構１を有する下側基板接続用リー
ド部３と、前記上側基板10に接続される上側基板接続用
リード部４とから構成され、前記上側基板接続用リード
部４が下側基板接続用リード部３とは別に平板部２の側
端から延設されたものである。<Means for Solving the Problem> A means for solving the problem according to the present invention is a semiconductor device in which an upper substrate 10 and a lower substrate 11 are stacked in two stages in order to miniaturize a package, as shown in FIGS. 1 to 3. At the time of expansion and contraction of the package, the upper substrate 10 and the lower substrate 11 are
Tab terminal F provided with a spring mechanism 1 for absorbing stress applied to
The flat plate portion 2 for radiating heat to the outside, the lower board connecting lead portion 3 connected to the lower board 11 and having the spring mechanism 1, and the upper board connecting board connected to the upper board 10. The upper substrate connecting lead portion 4 is formed of a lead portion 4 and extends from the side end of the flat plate portion 2 separately from the lower substrate connecting lead portion 3.
〈作用〉 上記課題解決手段において、パツケージの小型化を図る
ため、上側基板10および下側基板11を二段重ねに装着す
る。そして、タブ端子Ｆの上側基板接続用リード部４と
上側基板10および下側基板接続用リード部３と下側基板
11が半田付けされる。<Operation> In the above means for solving the problem, the upper substrate 10 and the lower substrate 11 are mounted in two layers in order to reduce the size of the package. Then, the upper substrate connecting lead portion 4 of the tab terminal F, the upper substrate 10 and the lower substrate connecting lead portion 3 and the lower substrate
11 is soldered.
このとき、上側基板接続用リード部４が、半導体装置の
パツケージの膨張、収縮時に上側基板10および下側基板
11に加わる応力を吸収するばね機構１を有する下側基板
接続用リード部３とは別に平板部２の側端より延設して
いるので、パツケージのスペースに余裕がなくばね機構
１の幅を広くできない場合でも、従来に比べてばね機構
１の長さを長くできる。これにより、ばね機構１に加わ
る応力は小さくなり、ばね機構１の機能を効果的に発揮
できる。At this time, the upper substrate connecting lead portion 4 causes the upper substrate 10 and the lower substrate to move when the package of the semiconductor device expands or contracts.
In addition to the lower board connecting lead portion 3 having the spring mechanism 1 that absorbs the stress applied to the plate 11, it is extended from the side edge of the flat plate portion 2, so that there is no room in the package space and the width of the spring mechanism 1 is small. Even if it cannot be widened, the length of the spring mechanism 1 can be made longer than in the conventional case. Thereby, the stress applied to the spring mechanism 1 is reduced, and the function of the spring mechanism 1 can be effectively exhibited.
したがつて、半導体装置の組み立て時に、下側基板接続
用リード部３、および下側基板接続用リード部３と下側
基板11との半田付け部に加わる応力を小さくでき、これ
に伴ない半導体装置の信頼性を向上させることができ
る。Therefore, when assembling the semiconductor device, the stress applied to the lower substrate connecting lead portion 3 and the soldering portion between the lower substrate connecting lead portion 3 and the lower substrate 11 can be reduced, and the semiconductor associated therewith can be reduced. The reliability of the device can be improved.
〈実施例〉 以下、本考案の一実施例を図面により説明する。<Embodiment> An embodiment of the present invention will be described below with reference to the drawings.
第１図は本考案の一実施例を示す半導体装置のタブ端子
の平面図、第２図は同じくその側面図、第３図は同じく
そのタブ端子を利用した半導体装置の断面図である。な
お、第4,5図に示した従来技術と同一機能部品について
は同一符号を付している。FIG. 1 is a plan view of a tab terminal of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a side view thereof, and FIG. 3 is a sectional view of a semiconductor device using the tab terminal. The same functional parts as those of the prior art shown in FIGS. 4 and 5 are designated by the same reference numerals.
まず、本実施例の半導体装置のタブ端子を第1,2図に基
づいて説明する。First, the tab terminal of the semiconductor device of this embodiment will be described with reference to FIGS.
図示の如く、本実施例のタブ端子Ｆは、パツケージを小
型化するために上側基板10および下側基板11が二段重ね
された半導体装置において、前記パツケージの膨張、収
縮時に上側基板10および下側基板11に加わる応力を吸収
するばね機構１を備え、外部に熱を放熱する平板部２
と、前記下側基板11に接続さればね機構１を有する下側
基板接続用リード部３と、前記上側基板10に接続される
上側基板接続用リード部４とから構成され、前記上側基
板接続用リード部４が下側基板接続用リード部３とは別
に平板部２の側端から延設されたものである。As shown in the figure, the tab terminal F of this embodiment is a semiconductor device in which an upper substrate 10 and a lower substrate 11 are stacked in two stages in order to miniaturize the package. A flat plate portion 2 that includes a spring mechanism 1 that absorbs stress applied to the side substrate 11 and radiates heat to the outside
And a lower substrate connecting lead portion 3 connected to the lower substrate 11 and having a spring mechanism 1, and an upper substrate connecting lead portion 4 connected to the upper substrate 10 for connecting the upper substrate. The lead portion 4 is extended from the side end of the flat plate portion 2 separately from the lower substrate connecting lead portion 3.
前記平板部２は、第１図の如く、矩形状に形成されてお
り、その上部中央には放熱フイン取付け用のピン孔６が
穿孔されている。As shown in FIG. 1, the flat plate portion 2 is formed in a rectangular shape, and a pin hole 6 for attaching a heat radiation fin is formed at the center of the upper portion thereof.
前記下側基板接続用リード部３は、平板部２の側端下部
に配されており、該平板部２に連結されたばね機構１
と、該ばね機構１と一体的に形成され下側基板11に半田
付けされる半田付け片５とから構成されている。前記ば
ね機構１は、Ｕ字形に形成され、その長さｌは上側基板
接続用リード部４よりも１だけ長く設けられている。
そして、前記半田付け片５の下端は、第２図の如く、湾
曲して形成されている。The lower board connecting lead portion 3 is arranged at a lower side end of the flat plate portion 2 and is connected to the flat plate portion 2 by a spring mechanism 1
And a soldering piece 5 integrally formed with the spring mechanism 1 and soldered to the lower substrate 11. The spring mechanism 1 is formed in a U-shape, and its length 1 is set to be longer than that of the upper substrate connecting lead portion 4 by one.
The lower end of the soldering piece 5 is formed in a curved shape as shown in FIG.
前記上側基板接続用リード部４は、第１図の如く、Ｌ字
形に形成されており、第1,2図の如く、一定間隔ｄをも
つて下側基板接続用リード部３より上側に配されてい
る。The upper substrate connecting lead portion 4 is formed in an L shape as shown in FIG. 1, and is arranged above the lower substrate connecting lead portion 3 with a constant distance d as shown in FIGS. Has been done.
次に、上記タブ端子Ｆを利用した電力用半導体装置の組
み立て方法を第３図に基づいて説明する。Next, a method of assembling the power semiconductor device using the tab terminal F will be described with reference to FIG.
図示の如く、パツケージの小型化を図るため、外枠12,1
3に上側基板10および下側基板11を二段重ねに装着す
る。そして、タブ端子Ｆの上側基板接続用リード部４と
上側基板10とを半田付けし、下側基板接続用リード部３
と下側基板11とを半田付けして半導体装置が完成する。As shown in the figure, the outer frame 12,1
The upper substrate 10 and the lower substrate 11 are mounted on the 3 in a two-tier stack. Then, the upper substrate connecting lead portion 4 of the tab terminal F and the upper substrate 10 are soldered to each other, and the lower substrate connecting lead portion 3 is formed.
The lower substrate 11 and the lower substrate 11 are soldered to complete the semiconductor device.
このとき、上側基板接続用リード部４が、半導体装置の
パツケージの膨張、収縮時に上側基板10および下側基板
11に加わる応力を吸収するばね機構１を有する下側基板
接続用リード部３とは別に平板部２の側端より延設して
いるので、パツケージのスペースに余裕がなくばね機構
１の幅を広くできない場合でも、従来のタブ端子のばね
機構１の長さに比べ、第１図の如く、l2だけばね機構１
の長さｌを長くできる。これにより、ばね機構１に加わ
る応力は小さくなり、ばね機構１の機能を効果的に発揮
できる。At this time, the upper substrate connecting lead portion 4 causes the upper substrate 10 and the lower substrate to move when the package of the semiconductor device expands or contracts.
In addition to the lower board connecting lead portion 3 having the spring mechanism 1 that absorbs the stress applied to the plate 11, it is extended from the side edge of the flat plate portion 2, so that there is no room in the package space and the width of the spring mechanism 1 is small. Even if it cannot be widened, compared to the length of the conventional spring mechanism 1 for tab terminals, as shown in FIG.
The length l can be increased. Thereby, the stress applied to the spring mechanism 1 is reduced, and the function of the spring mechanism 1 can be effectively exhibited.
したがつて、半導体装置の組み立て時に、下側基板接続
用リード部３、および下側基板接続用リード部３と下側
基板11との半田付け部に加わる応力を小さくでき、これ
に伴ない半導体装置の信頼性を向上させることができ
る。Therefore, when assembling the semiconductor device, the stress applied to the lower substrate connecting lead portion 3 and the soldering portion between the lower substrate connecting lead portion 3 and the lower substrate 11 can be reduced, and the semiconductor associated therewith can be reduced. The reliability of the device can be improved.
なお、本考案は、上記実施例に限定されるものではな
く、本考案の範囲内で上記実施例に多くの修正および変
更を加え得ることは勿論である。It should be noted that the present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.
〈考案の効果〉 以上の説明から明らかな通り、本考案によると、上側基
板接続用リード部が、半導体装置のパツケージの膨張、
収縮時に上側基板および下側基板に加わる応力を吸収す
るばね機構を有する下側基板接続用リード部とは別に平
板部の側端より延設しているので、パツケージのスペー
スに余裕がなくばね機構の幅を広くできない場合でも、
従来の比べてばね機構の長さを長くできる。これによ
り、ばね機構に加わる応力は小さくなり、ばね機構の機
能を効果的に発揮できる。<Effect of the Invention> As is apparent from the above description, according to the present invention, the upper substrate connecting lead portion causes expansion of the package of the semiconductor device,
Apart from the lower board connecting lead part, which has a spring mechanism that absorbs the stress applied to the upper and lower boards during contraction, it extends from the side edge of the flat plate part, so there is no room in the package space and there is no spring mechanism. Even if you can't widen the
The length of the spring mechanism can be made longer than in the past. Thereby, the stress applied to the spring mechanism is reduced, and the function of the spring mechanism can be effectively exhibited.
したがつて、半導体装置の組み立て時に、下側基板接続
用リード部、および下側基板接続用リード部と下側基板
との半田付け部に加わる応力を小さくでき、これに伴な
い半導体装置の信頼性を向上させることができる。Therefore, when assembling the semiconductor device, it is possible to reduce the stress applied to the lower board connecting lead part and the soldering part of the lower board connecting lead part and the lower board. It is possible to improve the sex.
第１図は本考案の一実施例を示す半導体装置のタブ端子
の平面図、第２図は同じくその側面図、第３図は同じく
そのタブ端子を利用した半導体装置の断面図、第４図は
従来の半導体装置のタブ端子を示す平面図、第５図は同
じくその側面図、第６図は片持ちばりのばねの長さとば
ね機構に加わる力との関係を示す図である。 F:タブ端子、1:ばね機構、2:平板部、3:下側基板接続用
リード部、4:上側基板接続用リード部、10:上側基板、1
1:下側基板。1 is a plan view of a tab terminal of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a side view of the same, FIG. 3 is a sectional view of a semiconductor device using the tab terminal, and FIG. FIG. 5 is a plan view showing a tab terminal of a conventional semiconductor device, FIG. 5 is a side view of the same, and FIG. F: Tab terminal, 1: Spring mechanism, 2: Flat plate part, 3: Lower board connecting lead part, 4: Upper board connecting lead part, 10: Upper board, 1
1: Lower substrate.
Claims (1)
よび下側基板が二段重ねされた半導体装置において、前
記パツケージの膨張、収縮時に上側基板および下側基板
に加わる応力を吸収するばね機構を備えたタブ端子であ
つて、外部に熱を放熱する平板部と、前記下側基板に接
続さればね機構を有する下側基板接続用リード部と、前
記上側基板に接続される上側基板接続用リード部とから
構成され、前記上側基板接続用リード部が下側基板接続
用リード部とは別に平板部の側端から延設されたことを
特徴とする半導体装置。1. In a semiconductor device in which an upper substrate and a lower substrate are stacked in two in order to miniaturize the package, a spring mechanism for absorbing stress applied to the upper substrate and the lower substrate when the package expands and contracts. A tab terminal provided, a flat plate portion for radiating heat to the outside, a lower substrate connecting lead portion connected to the lower substrate and having a spring mechanism, and an upper substrate connecting lead connected to the upper substrate. A semiconductor device, wherein the upper substrate connecting lead portion is extended from a side end of the flat plate portion separately from the lower substrate connecting lead portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5129089U JPH0729644Y2 (en) | 1989-04-28 | 1989-04-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5129089U JPH0729644Y2 (en) | 1989-04-28 | 1989-04-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02142548U JPH02142548U (en) | 1990-12-04 |
| JPH0729644Y2 true JPH0729644Y2 (en) | 1995-07-05 |
Family
ID=31570596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5129089U Expired - Fee Related JPH0729644Y2 (en) | 1989-04-28 | 1989-04-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0729644Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245362A (en) * | 2005-03-04 | 2006-09-14 | Mitsubishi Electric Corp | Semiconductor apparatus and electrode terminal used for the same |
| JP5561527B2 (en) * | 2010-03-24 | 2014-07-30 | 株式会社オートネットワーク技術研究所 | Circuit assembly and electrical junction box |
-
1989
- 1989-04-28 JP JP5129089U patent/JPH0729644Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02142548U (en) | 1990-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6370027B1 (en) | Semiconductor module and heat sink used in such module | |
| US7193303B2 (en) | Supporting frame for surface-mount diode package | |
| JPH0729644Y2 (en) | Semiconductor device | |
| JPS62113452A (en) | Power semiconductor device | |
| JPH05259334A (en) | Semiconductor device | |
| JP3442349B2 (en) | Terminal fitting | |
| KR0169272B1 (en) | Semiconductor device | |
| JP2819825B2 (en) | Semiconductor device with built-in TAB | |
| JP2005129552A (en) | Circuit board | |
| JPS5843232Y2 (en) | transistor mounting device | |
| JP2003051562A (en) | Semiconductor device | |
| JP2003133681A (en) | Fixture of semiconductor device and fixing structure thereof | |
| JPH0727639Y2 (en) | Semiconductor device | |
| JPH0631723Y2 (en) | Semiconductor device | |
| JPS61128550A (en) | Semiconductor device | |
| JPH0745774A (en) | Hybrid integrated circuit device | |
| JP2562773Y2 (en) | Semiconductor integrated circuit device | |
| JP2003007899A (en) | Semiconductor device and its manufacturing method | |
| JPS602873U (en) | Soldering structure of surface mount transistor | |
| JP2000068665A (en) | Grounding structure to deck chassis for board | |
| JPH041743Y2 (en) | ||
| JPH0577972U (en) | Connection structure of electronic parts | |
| JPH07106457A (en) | Package for hybrid ic chip | |
| JPH10229104A (en) | Semiconductor device and tape carrier which is used for manufacturing method thereof | |
| JPH08264909A (en) | Chip type electronic component |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |