JPH07288847A - Video signal phase correction device - Google Patents

Abstract

PURPOSE:To reproduce a video image with high image quality by providing a data phase correction device between blocks operated by a line clock of a signal processing circuit and a D/A converter so as to correct a phase of the signal suitable for the clock. CONSTITUTION:A data phase correction device 15 detects a phase difference between a received burst lock clock CKB and a line lock clock CKL. Then a Y signal, an I signal and a Q signal received while being sampled by the burst lock clock CKB are corrected for the phase with respect to the phase of the line lock clock CKL. The Y, I, Q signals are given to a signal processing circuit 16, in which an image quality of the video signal is enhanced. Since the phase of the Y, I, Q signals inputted to the signal processing circuit 16 is converted into a sampling phase of the line lock clock CKL, the signals are processed with high accuracy by using the line lock clock CKL used for the signal processing circuit 16 even when the received signals are non-standard signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has fluctuations when a standard television signal (hereinafter referred to as a standard signal) is input or in a horizontal synchronizing signal such as a reproduced video signal from a VTR. The present invention relates to a video signal processing device capable of reproducing high quality video even when a non-standard television signal (hereinafter, referred to as non-standard signal) is input.

[0002]

2. Description of the Related Art Conventionally, two types of system clocks, a burst lock clock locked to a color burst signal or a line lock clock locked to a horizontal sync signal, have been considered as a signal processing synchronization clock for high quality reproduction. ing.

FIG. 11 is a block diagram showing a video signal processing device including these conventional clock generators in a television receiver. FIG. 11A shows an example of a video signal processing device using a burst lock clock.
(B) is an example of a video signal processing device using a line lock clock. Each video signal processing device includes a video signal input terminal 1, a burst lock clock generation circuit 2 that outputs a burst lock clock CKb or a line lock clock generation circuit 3 that outputs a line lock clock CKl, a synchronization signal generation circuit 4, It is composed of a signal processing circuit 5, a synchronization signal output terminal 6, and a video signal output terminal 7.

In the example shown in FIG. 11A, the burst lock clock generating circuit 2 uses a crystal oscillator (not shown) to convert a color burst signal included in a video signal input from the video signal input terminal 1 into a color burst signal. Generates a stable and stable burst lock clock. Here, the input video signal is the above-mentioned standard signal that is compatible with the standard television broadcasting system, and the frequency (fsc) of the color burst signal and the frequency (f) of the horizontal synchronizing signal included in this standard signal.
The relationship with h) is

Fsc = 455 · fh / 2 (1)

[0006] The burst lock clock CKb from the burst lock clock generator 2 is input to the sync signal generation circuit 4, and the sync signal generation circuit 4 generates a sync signal created by utilizing the relationship of the above equation (1).

The video signal input from the terminal 1 and the burst lock clock CKb from the burst lock clock generation circuit 2 are input to the signal processing circuit 5, and the above (1)
Video signals are processed using the relationship of formulas to improve the image quality of the images. Note that as a publication that describes a conventional signal processing method for improving the image quality of such a video signal, there is, for example, Japanese Patent Laid-Open No. 64-89791.

In the example shown in FIG. 11B, the line lock clock generation circuit 3 generates a line lock clock CKl synchronized with a horizontal sync signal included in the video signal input from the terminal 1. Further, the signal processing circuit 5 receives the video signal input from the terminal 1 and the line lock clock CKl from the line lock clock generation circuit 3, performs video signal processing, and achieves high image quality of the video as described above. It was

[0009]

In the prior art described above, in the circuit of FIG. 11A, when the video signal input to the video signal input terminal 1 is a standard signal, a very stable sync signal is generated. In addition to being generated, the signal processing for improving the image quality of the video signal can be accurately performed.

However, VTR (video tape recorder)
Such as a video signal reproduced from a non-standard signal which does not strictly adhere to the standard television broadcasting system, that is, a signal which does not necessarily maintain the relationship of the above formula (1) is input. If this happens, not only is it impossible to perform signal processing to improve image quality, that is, to improve image quality,
There is a problem that the entire circuit operation in the receiver cannot be synchronized.

On the other hand, in the circuit of FIG. 11B, since the horizontal synchronizing signal included in the video signal is used as a reference, sufficient synchronization can be achieved even when a non-standard signal is input.
Therefore, it is possible to handle video signals from various devices having different pull-in ranges. Further, regarding signal processing for improving image quality, when a non-standard signal is input, the non-standard signal does not maintain the relationship of the equation (1) as described above, and therefore, in the range where the relationship is not used, It is possible to perform signal processing for improving image quality.

However, when the standard signal is input, the relationship of the above equation (1) is maintained for the standard signal.
In the circuit of (b), the value of Q of the oscillator (not shown) of the line lock clock generation circuit 3 is not higher than that of the oscillator (not shown) of the burst clock generation circuit 2 of FIG. Since the stability of the generated clock is also low, when the signal processing for improving the image quality is attempted by using the relationship of the above formula (1), the improvement effect is not sufficient.

An object of the present invention is to provide a television receiver capable of maintaining an image quality improving effect by performing signal processing with an optimum clock suitable for both standard and non-standard signal input. To do.

[0014]

In order to achieve the above object, according to the present invention, a system clock generating means for generating a burst lock clock and a line lock clock and a frequency and a phase of a clock for reproducing a phase of a video signal are provided. A data phase correction means for performing correction and a signal processing means for optimally switching the two system clocks to perform signal processing are provided. Further, as the data phase correction means, a clock average phase difference data generation means, an interpolation coefficient generation means, and a linear interpolation means are provided. Further, standard / non-standard signal mode determining means for determining whether the mode is the standard signal mode or the non-standard signal mode based on the clock average phase difference data detecting means, and the signal / clock switching means for switching the signal and the clock based on the standard / non-standard signal mode determining means. Equipped with.

[0015]

The system clock generating means simultaneously generates the clock locked to the burst signal and the line lock clock locked to the horizontal synchronizing signal. The data phase correction means phase-converts the burst lock sampling video data locked to the burst signal into the line lock sampling video data locked to the horizontal synchronizing signal according to the frequency or phase difference between the reproduced burst lock clock and the line lock clock. to correct. The signal processing up to the input of the data phase correction means is performed by the burst lock clock, and the signal processing after the correction means is performed by the line lock clock. Further, the clock average phase difference data generation means in the data phase correction means detects the average phase difference between the burst lock clock and the line lock clock, and based on this, the interpolation coefficient generation means obtains the phase error data for each sample. Then, an interpolation coefficient for linear interpolation calculation is generated. The linear interpolation means linearly interpolates the input video signal based on this interpolation coefficient, and outputs the video signal converted into the phase of the line lock clock. Further, in the standard / non-standard signal mode determination means, 1 in the clock average phase difference data generation means is used.
A determination signal is generated based on the signal from the clock difference detection means, and based on the determination signal, the signal switching means adds the data phase correction and switches the optimal system clock and supplies it to each signal processing circuit.

[0016]

The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of a digital video signal processing device to which the present invention is applied. In the figure, the digital video signal processing device includes a video signal input terminal 8, an A / D converter 9, a Y / C separation circuit 10, and a burst signal extraction circuit 1.
1, a sync separation circuit 12, a clock generation circuit 13,
A color demodulation circuit 14, a data phase corrector 15, and a signal processing circuit 16 that performs scanning line conversion processing, matrix conversion, etc.
And a D / A converter 17.

Next, the operation will be described. A / D converter 9
The video signal converted into a digital signal in
It is input to the C separation circuit 10, the burst signal extraction circuit 11, and the synchronization separation circuit 12, respectively. As a sampling clock of the A / D converter 9 and a system clock of the Y / C separation circuit 10 and the color demodulation circuit 14, a burst lock clock CKB output from a clock generation circuit 13 described later is input. This clock frequency is usually 4 fsc, which is four times the subcarrier frequency. The Y / C separation circuit 10 three-dimensionally filters the input video signal using, for example, a frame comb filter,
The luminance (Y) signal and the color (C) signal are separated and output. The burst signal extraction circuit 11 uses the 3.58 MHz band pass filter or the like to generate the burst signal B included in the video signal.
Is extracted and supplied to the clock generation circuit 13. The sync separation circuit 12 separates and extracts the horizontal sync signal and the vertical sync signal included in the video signal, and supplies the horizontal sync signal H to the clock generation circuit 13 among them.

The clock generation circuit 13 has a burst lock clock CKB synchronized with the burst signal B, based on the input burst signal B and horizontal synchronization signal H.
Line lock clock CK locked to horizontal sync signal H
Produces L. Here, burst lock clock CKB
Is supplied as the system clock of the A / D converter 9, the Y / C separation circuit 10 and the color demodulation circuit 14 as described above, and is further supplied as one input of the data phase corrector 15. Also, line lock clock CKL
Is supplied as the system clock of the signal processing circuit 16 and the D / A converter 17, and is also supplied as the other input of the data phase corrector 15. The color demodulation circuit 14 demodulates the input color (C) signal and separates and outputs it into an I signal and a Q signal.

The data phase corrector 15 uses the burst lock clock CKB which is the two input system clocks.
And the phase difference of the line lock clock CKL is detected,
According to the phase difference, the Y signal, the I signal, and the Q signal sampled by the burst lock clock CKB and input are phase-corrected in accordance with the phase of the line lock clock CKL. The configuration of the data phase corrector 15 will be described later in detail.

The Y signal, the I signal and the Q signal whose phases have been corrected by the data phase corrector 15 are the signal processing circuit 1
6 is input, and for example, processing such as scanning line conversion and noise reduction is performed to improve the image quality of the video signal. The Y signal, the I signal, and the Q signal input to the signal processing circuit 16 are converted to the sampling phase of the line lock clock CKL, and therefore, for example, even if the input signal is a nonstandard signal, it is used in this signal processing circuit. The signal processing can be performed with high accuracy by the line lock clock CKL which is a system clock for the operation. Although not described, the signal processing circuit 16 also performs matrix conversion processing of the color (C) signal, and the video signal finally becomes Y.
The signal and the C signal are input to the D / A converter 17. The D / A converter 17 converts the input digital Y signal and C signal into analog signals and outputs them to the Y signal output terminal 18 and the C signal output terminal 19, respectively.

In the video signal processing device described above,
The configuration of the data phase corrector 15, which is a feature of the present invention, will be described below. In the following drawings, the reference numerals of the parts and circuits that have come before are denoted by the same reference numerals.

FIG. 2 is a block diagram showing the concept of the data phase corrector 15. The data phase corrector 15 includes a Y signal input terminal 20, an I signal input terminal 21, a Q signal input terminal 22, and a burst lock clock CKB input terminal 23.
A line lock clock CKL input terminal 24, a clock average phase difference data generation circuit 25, an interpolation coefficient generation circuit 26, a Y signal linear interpolation filter 27, an I signal linear interpolation filter 28, and a Q signal straight line. Interpolation filter 2
9, Y signal output terminal 30, I signal output terminal 31,
It is composed of a Q signal output terminal 32.

Next, the general operation will be described. Burst lock clock CKB input to phase difference data generation circuit 25
The line lock clock CKL detects the average phase difference between both clocks in the detector provided in the phase difference data generation circuit 25, and supplies the interpolation coefficient generation circuit 26 with data N indicating the average phase difference amount. The coefficient generating circuit 26 generates interpolation coefficient signals K1 and K2 according to the input phase difference data N.

Here, K2 = 1-K1.

The Y signal, the I signal, and the Q signal are input to each of the linear interpolation filters 27 to 29, and the burst lock clock CKB, the interpolation coefficient signal K1, and the interpolation coefficient are input to all of these interpolation filters. A signal K2 (coefficient values are also K1 and K2, respectively) is input. Each of the linear interpolation filters 27 to 29 linearly interpolates the input video signal data with respect to the sampling data one clock before using the interpolation coefficient K1 and the interpolation coefficient K2, and outputs a new video signal. The interpolation coefficient K1 indicates the distance from one clock before the input video signal, and the interpolation coefficient K2 indicates the distance from the one clock after the input video signal.

FIG. 3 shows an embodiment of the clock average phase difference data generation circuit 25 in FIG. Further, the figure also shows an interpolation coefficient generating circuit 26 and a standard / non-standard mode signal generating circuit 80 described later. The clock average phase difference generation circuit 25 includes a one-clock difference detection circuit 33, a latch circuit 41, and an average phase error data generation circuit 42. In FIG. 3, the one-clock difference detection circuit 3 shown by the broken line portion
3 is a counter 34, an up / down counter 35,
It includes decoders 36 to 38, an OR gate 39, a counting stop circuit 40, and a decoder 52.

The interpolation coefficient generating circuit 26 includes a cumulative adder 43.
And a coefficient generation ROM (Read Only Memory) 44, and has an output terminal 70 for the interpolation coefficient signal K1 and an output terminal 71 for the interpolation coefficient signal K2.

The standard / non-standard mode signal generation circuit 80 is
It comprises a standard / non-standard signal mode determination circuit 61 and a control signal generation circuit 62.

Next, the operation will be described. The 1-clock difference detection circuit 33 has a burst lock clock CKB input to the terminal 23 and a line lock clock CKL input to the terminal 24.
The phase difference of the burst lock clock CKB is 1
It is a circuit that detects the time when the clock count is reached. The average phase difference for each clock is calculated from the count value of the burst lock clock CKB until the phase difference between both clocks detected by this circuit reaches the one clock width of the burst lock clock CKB. The counter 34 counts the burst lock clock CKB, and at the same time, the up / down counter 35.
Performs the up-count operation with the line lock clock CKL and the down-count operation with the burst lock clock CKB.

A preset value "2" is set in the up / down counter 35 by the signal from the OR gate 39, and at the same time, the counter 34 is reset. The output value of the up / down counter 35 is "
1 ”, and“ 2 ”or“ 3 ”in the decoder 37,
The decoder 38 decodes and outputs each "4". The outputs of the decoder 36 and the decoder 38 are O
It is input to the R gate 39, and its output is the counter 3
4 is reset and the up / down counter 35 is preset. Further, the output of the OR gate 39 is also used as a latch clock signal of a latch circuit 41 and a reset signal of the cumulative adder 43 which will be described later.

The standard / non-standard signal mode judging circuit 61 in FIG. 3 judges the standard signal mode based on the signal from the decoder 37 and the non-standard signal mode based on the signal from the gate 39 to judge the judgment signal. Output SD. further,
Based on the determination signal SD, the control signal generation circuit 62 generates a control signal CO for performing signal switching described later, and outputs the control signal CO to the terminal 63.

FIG. 4 shows the one-clock difference detection circuit 33 described above.
The counting operation of the up / down counter 35 for explaining the operation of FIG. (A) shows the line lock clock CKL for up-counting, (B) shows the burst lock clock CKB for down-counting, and (C) shows the count value of the counter. FIG. 4A shows a case where the burst lock clock CKB and the line lock clock CKL have constant frequencies and phases (standard signal mode). In this case, the content of the up / down counter 35 constantly changes from “3” to “2” with respect to the preset value “2”, which indicates that both clocks have no frequency and phase shift. This state is detected by the decoder 37 of the 1-clock difference detection circuit 33.

FIG. 4B shows the line lock clock CK.
The case where the frequency of L is lower than the frequency of the burst lock clock CKB is shown. At this time, at the moment when the phase difference between both clocks becomes one clock difference, the burst lock clock C
KB has arrived twice in a row and the count value of the counter is "2".
→ "3" → "4" when it went up. This count value ”
4 ″ is detected by the decoder 38 of the 1-clock difference detection circuit 33.

FIG. 4C shows the line lock clock CK.
The case where the frequency of L is higher than the frequency of the burst lock clock CKB is shown. At this time, at the moment when the phase difference of both clocks becomes one clock difference, the line lock clock CK
L has arrived twice in a row, and the count value of the counter is "3" → "
It is when it decreases from 2 "to" 1 ". This count value" 1 "
Is detected by the decoder 36 of the 1-clock difference detection circuit 33.

As described above, the signals detected by the decoder 36 and the coder 38 are output when the phase difference between the two clocks becomes exactly one clock after the up / down counter 35 is preset, and the OR gate 39 outputs the signal. The count value of the counter 34 is latched in the latch circuit 41 via the same, and the up / down counter 35 is preset. At this time, the count data φd latched by the latch circuit 41 represents the time until the phase difference between the two clocks reaches one clock.

Therefore, the latch circuit 41 for this data φd
1 from the burst lock clock CKB in the next average phase difference data generation circuit 42.
Convert to average phase difference in clock units. The average phase difference data generation circuit 42 is, for example, a ROM (Read Only M).
emory). Assuming that one cycle of the burst lock clock CKB is Tb, the data conversion output N is

N = Tb / φ.

This average phase difference signal N is fed to the cumulative adder 43 provided in the subsequent interpolation coefficient generating circuit 26 by N → 2N → when the burst lock clock CKB arrives.
3N ... Cumulatively added, and the 1-clock difference detection circuit 33 is added.
Phase difference data for each sample clock is generated based on the clock phase difference data obtained in step 1. Also, the adder 43
Is reset by the signal from the OR gate 39 every time the 1-clock difference detection circuit 33 detects the 1-clock phase difference between the two clocks, and new average phase difference data N is cumulatively added from the next clock input. To start.

The cumulatively added phase difference data D from the adder 43 is supplied to the interpolation coefficient generation ROM 44, and the phase difference data D and the interpolation coefficient K1 and the interpolation coefficient K2 table stored in the interpolation coefficient generation ROM 44 are referred to. Then, the interpolation coefficient K1 and the interpolation coefficient K2 corresponding to the phase difference data D are generated and output to the terminals 70 and 71. See also FIG.
The decoder 52 and the counting stop circuit 40 in the 1-clock difference detection circuit 33 of FIG. 2 stop the counting operation of the counter 34 when the frequency and phase of the two clocks are constant for a long period of time, that is, when the standard signal mode continues for a long time. The phase difference data is operated so as not to be supplied.

FIG. 5 shows an embodiment of the linear interpolation filter shown in FIG. Three linear interpolation filters 27-2
Since all 9 have the same configuration, the outline thereof will be described here using the linear interpolation filter 27. The linear interpolation filter 27 includes a Y signal input terminal 20, a burst lock clock CKB input terminal 45, a latch circuit 46, and a multiplier 4.
7 and 48, an adder 49, an input terminal 50 for the coefficient signal K2, and an input terminal 51 for the coefficient signal K1.

The linear interpolation filter 27 operates as follows. The Y signal input to the Y input terminal 20 is input to the latch circuit 46 and the multiplier 47. Latch circuit 4
The Y signal input to 6 is applied to the burst lock clock terminal 4
The signal is delayed by one sample by the burst lock clock CKB input to 5 and output, and input to the multiplier 48.
The Y signal input to the multiplier 47 is multiplied by the interpolation coefficient K1 output from the interpolation coefficient generation circuit 26, and the adder 49
Is output to. The Y signal delayed by one sample input to the multiplier 48 is multiplied by the interpolation coefficient K2 output from the interpolation coefficient generation circuit 26 and output to the adder 49. The multiplication results are added by the adder 49, and the addition signal Yt is output to the output terminal 30.

FIG. 6 is a timing waveform diagram showing the above operation. In FIG. 6, (a) shows n of the input Y signal,
n + 1, n + 2nd sample data sequence I _n , I _{n + 1} , I
_{n + 2} , (b) is the burst lock clock CKB,
(C) shows the line lock clock CKL, and (D) shows the sample data strings O _n and O _{n + 1} after linear interpolation. The interpolation coefficient K1 is the burst lock clock C at this point.
Deviation between KB and line lock clock CKL, that is,
The distance between the sample data I _n and the sample data O _n after linear interpolation is shown, and the interpolation coefficient K2 shows the distance between the sample data I _{n + 1} at this point and the sample data O _n after linear interpolation. As is clear from the above description, the output after linear interpolation is

O _n = K1 · I _{n + 1} + K2 · I _n .

The clock average phase difference data generation circuit 25 and the interpolation coefficient generation circuit 26 in FIG.
A flowchart of the circuit operation up to is shown in FIG.

In FIG. 7, the counter 34 factors the input burst lock clock CKB (S1).
The up / down counter 35 repeats up / down by the input of the burst lock clock CKB and the line lock clock CKL and monitors it by its output decoders 36 to 38 to judge whether the phase difference between the two clocks is one clock. Yes (S2). When the phase difference does not reach one clock (NO), the counter 34 continues counting the burst lock clock CKB. When the phase difference reaches 1 clock and the output CKd of the decoder A36 or the decoder C37 is present, the count content φ of the counter 34
d is latched in the latch circuit 41 (S3) and the counter 34 is reset to prepare for the subsequent counting.

The average phase error generating circuit 42 divides the period Tb of the burst lock clock CKB by using the content φ of the latch circuit 41 to obtain the average phase difference data N in one clock unit (S4). This average phase difference data N is output to the cumulative adder 43 in the interpolation coefficient generating circuit 26, and this data is added for each burst lock clock CKB to obtain added data D (S5). The data of the adder 43 is
When the next one clock difference is detected, it is cleared and the cumulative addition of the next average phase difference is started. The higher-order bits of the addition data D of the cumulative adder 43 are transferred to the ROM 44 (S
6), interpolation coefficients K1 and K2 corresponding to the addition data D
Is read out and an interpolation coefficient is generated (S7).

When the frequency and phase of the two clocks are constant for a long period of time, the counter 34 is not reset and continues counting. The count value φd of the counter 34 is a constant value, for example,
When reaching 238766, the decoder 52 operates the counting stop circuit 40 as the standard signal mode, stops the counting of the counter 34, and prevents the count content φd from being supplied as phase difference data.

FIG. 8 shows another embodiment of the 1-clock difference detection circuit 33 shown in FIG. The 1-clock difference detection circuit 33 of the present embodiment shown by the broken line includes a counter 34, a B counter 53, an L counter 54, and a pulse forming circuit 55.
A latch circuit 57, an edge detection circuit 58, a decoder 52, a counting stop circuit 40, and a CKd output terminal 59.
And a φd output terminal 60. Further, the standard / non-standard mode signal generation circuit 80 includes a standard / non-standard signal mode determination circuit 64 and a control signal generation circuit 62. The feature of the present embodiment is that the instant when the phase difference between the two clocks, the burst lock clock CKB and the line lock clock CKL, becomes just one clock of the burst lock clock CKB, the output values of the two divided clocks are compared. This is the point to detect.

Next, the operation will be described. Burst lock clock CKB is input to B counter 53, and L counter 5
The line lock clock CKL is input to 4. The divide-by-two output QA of the B counter 53 is output to the pulse forming circuit 55, and the divide-by-2 output QA of the L counter 54 is the latch circuit 5.
It is output to 7. The pulse forming circuit 55 forms a pulse which rises at the rising edge of the divide-by-2 output pulse of the B counter 53 and has a small rise time, and inputs it to the latch circuit 57 as a latch pulse. Further, the latch circuit 57 latches the frequency-divided output QA of the L counter 54 based on the latch pulse and inputs it to the edge detection circuit 58. When the output of the latch circuit 57 changes from "H" to "L" or from "L" to "H", it indicates that the phase difference between the two clocks has reached one clock. Therefore, the edge detection circuit 58 detects the edge portion (leading edge or trailing edge portion) of the output of the latch circuit 57 and generates the pulse CKd.

The output signal CKd of the edge detection circuit 58 is "
At the time of H ", the count value φd of the counter 34 counting the burst lock clock CKB is supplied to the latch circuit 41 shown in FIG. 3 in parallel with the above operation, and the subsequent processing is carried out as shown in FIG. The detection signal C is derived in the same manner as the example.
Kd is the counter 34 and B counter 53 and L
The counter 54 is reset. The standard / non-standard signal mode determination circuit 64 uses the detection signal CKd from the edge detection circuit 58 to determine whether it is the standard signal mode or the non-standard signal mode, and outputs the determination signal SD. Similar to the previous embodiment of FIG. 3, the control signal generation circuit 62 generates the control signal CO based on the judgment signal SD.

FIG. 9 is a signal timing diagram for explaining the above operation. In FIG. 9, (a) shows the B counter 53.
The burst lock clock CKB to be input to
(B) is the divided-by-2 output QA, (C) is the output pulse (latch pulse) of the pulse forming circuit 55, and (D) is the line lock clock CKL to be input to the L counter 54.
(E) is the divided-by-2 output QA, (f) is the latch circuit 5
7 shows the output signal of No. 7, and (g) shows the output signal CKd of the edge detection circuit 58.

FIG. 9A shows the line lock clock CK.
The case where the frequency of L is lower than the frequency of the burst lock clock CKB is shown.

Burst lock clock CKB (b) n
N- of the count eye and line lock clock CKL (d)
When the phase difference becomes 1 clock difference at the first count,
The divide-by-2 signal (B) of the B counter 53 rises, and the output pulse (latch pulse) (C) of the pulse forming circuit 55 rises. The latch pulse causes the frequency-divided signal QA (e) of the L counter 54 to be latched in the latch circuit 57. At this time, the divided-by-2 signal QA (e) of the L counter 54 is "
H ”, the content of the latch circuit 57 is latched at“ H ”and its output (f) also changes to“ H. ”The edge detection circuit 58 detects the change in the output of the latch circuit 57 and detects one clock difference. The detection signal CKd is output, and the B counter 53, the L counter 54, and the counter 34 are reset by the one-clock difference detection signal CKd, and the B counter 5
The divided-by-2 signal QA (b) of 3 is set to "L" and the L counter 5
The frequency-divided signal QA (e) of 4 also changes to "L". By the 1-clock difference detection signal CKd, the contents of the counter 34 are
Return to 0.

At this moment, at the moment when the phase difference between the two clocks becomes one clock difference, the n-th count output of the burst lock clock CKB and the (n-1) th count of the line lock clock CKL are divided by two ((R Note that the output signal CKd of the edge detection circuit 58 is "
It can be detected when it becomes "H" ((f) (g), point A).

FIG. 9B shows the case where the frequency of the clock CKL is higher than the frequency of the clock CKB.

Burst lock clock CKB (b) n
N + of the count eye and line lock clock CKL (d)
When the phase difference becomes 1 clock difference at the first count,
The divide-by-2 signal (B) of the B counter 53 rises, and the output pulse (latch pulse) (C) of the pulse forming circuit 55 rises. The latch pulse causes the frequency-divided signal QA (e) of the L counter 54 to be latched in the latch circuit 57. At this time, the divided-by-2 signal QA (e) of the L counter 54 is "
L ", the content of the latch circuit 57 is latched to" L "and its output (f) also changes to" L ". The edge detection circuit 58 detects the change of the output of the latch circuit 57 and detects one clock difference. The detection signal CKd is output, and the B counter 53, the L counter 54, and the counter 34 are reset by the one-clock difference detection signal CKd, and the B counter 5
The divided-by-2 signal QA (b) of 3 is set to "L" and the L counter 5
The frequency-divided signal QA (e) of 4 also changes to "L". By the 1-clock difference detection signal CKd, the contents of the counter 34 are
Return to 0.

At this time, at the moment when the phase difference between the two clocks becomes one clock difference, the nth count of the burst lock clock CKB and the nth count of the line lock clock CKL are the same as above.
+1 count each divided by 2 output ((b) and (e))
Can be detected by the output signal “H” of the edge detection circuit 58, paying attention to the fact that the latch circuit 57 outputs different values due to the latch pulse (C). ((F) (G), A point) At this A point, the B counter 53 and the L counter 5
4 is reset.

As described above, the data phase corrector 15 according to the present invention, when the input signal is a non-standard signal, when the burst lock clock CKB and the line lock clock CKL have a difference in frequency and phase. In addition, in order to perform optimal signal processing with each clock, a line for performing a high-quality signal processing with a burst lock drive processing unit such as Y / C separation and color demodulation suitable for signal processing of an input video signal. It is inserted between the lock clock drive processing unit and the phase of the video signal can be converted and corrected from the burst lock system to the line lock system.
Especially effective in non-standard signal mode.

The standard / non-standard signal mode determination circuit 61 or 64 shown in the above-described embodiment and FIGS. 3 and 8 is the two system clocks from the one-clock difference detection circuit 33.
This is a circuit for generating a non-standard signal mode determination signal SD based on a signal generated when the phase difference between the burst lock clock CKB and the line lock clock CKL reaches just one clock with the burst lock clock CKB as a unit. . Based on the determination signal SD, the control signal generation circuit 62 can also perform signal processing switching in various standard / non-standard signal modes.

FIG. 10 is a block diagram showing the first embodiment. This embodiment is provided with a signal selector 66, a signal selector 67, and a clock selector 68 in the video signal processing device including the data phase correction device 15 shown in FIG. 1, and only when the input video signal is a non-standard signal, The input video signal is subjected to the data phase correction processing via the data phase correction device 15, and the system clock supplied to the signal processing circuit 16 and the D / A converter 17 is line locked in the non-standard signal mode. Clock CKL
, Burst lock clock CKB in standard signal mode
It has a feature in selecting.

Next, the configuration and operation will be described with reference to FIG. The Y signal from the Y / C separation circuit 10 and the I and Q signals from the color demodulation circuit 14 are input to the three movable contacts c of the signal selector 66 that switches between three signals. The three fixed contacts s of the signal selector 66 are connected to the three fixed contacts s of the signal selector 67 which also switch three signals. The three fixed contacts n of the signal selector 66 are connected to the input terminals of the data phase corrector 15, and the output terminals of the data phase corrector 15 are connected to the three fixed contacts n of the signal selector 67. The Y signal, the I signal, and the Q signal input from the n-contact of the signal selector 66 are subjected to the data phase correction by the data phase corrector 15, and the Y signal, the I signal, and the Q signal whose data phase has been corrected respectively. The signal is guided to the n-contact of the signal selector 67 and output to the signal processing circuit 16 via the three movable contacts c.

The fixed contact s of the clock selector 68 is
The burst lock clock CKB is guided, and the fixed contact n is guided by the line lock clock CKL. The movable contact c of the clock selector 68 is conductively connected to the signal processing circuit 16 and the D / A converter 17.

Signal selector 66 and signal selector 67
The movable contact c of the clock selector 68 is a control signal generation circuit (6 in FIG. 3) provided in the data phase corrector 15.
By the control signal CO from 2), it is connected to the fixed contact s side at the time of the standard signal and switched to the fixed contact n side at the time of the non-standard signal.

By the above operation, when the input video signal is a non-standard signal, the data phase correction corresponding to the phase of the line lock clock CKL is performed, and at the same time, the subsequent signal processing is performed by the line lock clock CKL. In the case of a signal, data phase correction is not performed and all signal processing is performed with the highly stable burst lock clock CKB, so that a higher quality image can be obtained in both the standard mode and the non-standard mode.

[0065]

According to the present invention, in a television receiver, an A / D converter for an input video signal, a Y / C separation circuit, and a block operating with a burst lock clock CKB of a color demodulation circuit, a signal processing circuit, and Since the data phase corrector is provided between the blocks that operate with the line lock clock CKL of the D / A converter, the signal is corrected to the phase suitable for the clock, and in each block, the input video signal is the standard signal. Regardless of whether the signal is a non-standard signal or a non-standard signal, signal processing can be performed with an optimum clock, and a high quality image can be reproduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a video signal processing device showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of components of the present invention.

FIG. 3 is a diagram showing an example of components of the present invention.

FIG. 4 is a timing waveform chart for explaining the operation of the device of the present invention.

FIG. 5 is a diagram showing an example of components of the present invention.

FIG. 6 is a timing waveform chart for explaining the operation of the device of the present invention.

FIG. 7 is a flowchart explaining the operation of the device of the present invention.

FIG. 8 is a diagram showing another embodiment of the components of the present invention.

FIG. 9 is a timing waveform chart for explaining the operation of the device of the present invention.

FIG. 10 is a configuration diagram of a video signal processing device showing another embodiment of the present invention.

FIG. 11 is a diagram showing a conventional example of a video signal processing device.

[Explanation of symbols]

 9 A / D converter 10 Y / C separation circuit 11 Burst signal extraction circuit 12 Sync separation circuit 13 Clock generation circuit 14 Color demodulation circuit 15 Data phase corrector 16 Signal processing circuit 17 D / A converter 25 Clock average phase difference data Generation circuit 26 Interpolation coefficient generation circuit 27 to 29 Linear interpolation filter 33 1 Clock difference detection circuit 34, 53, 54 counter 35 Up / down counter 36 to 38, 52 Decoder 39 OR gate 40 Count stop means 41, 46, 57 Latch circuit 42 Average phase error generation circuit 43 Cumulative adder 44 Interpolation coefficient generation circuit 47, 48 Multiplier 49 Adder 55 Pulse formation circuit 58 Edge detection circuit 61, 64 Standard / non-standard determination circuit 62 Control signal generation circuit 66, 67 Signal selector 68 Clock selector 80 standard / non-standard mode Signal generation circuit 80 Standard / non-standard mode signal generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Yamamoto 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Inside Hitachi Media Media Research Laboratories

Claims (6)

[Claims] 1. A video signal phase correction apparatus for a television receiver, wherein A / D conversion means for converting an analog input video signal into a digital signal, and a predetermined signal synchronized with a burst signal and a horizontal synchronizing signal included in the input video signal. Clock generating means for generating two types of frequency clocks;
An average phase difference data generating means for generating average phase difference data between these two clocks, and an interpolation coefficient for interpolating a plurality of sample data of the input video signal based on the average phase difference data, at predetermined sampling intervals. An interpolating coefficient generating means for continuously generating an input video signal, an interpolating means for interpolating an input video signal with the sample data and the interpolating coefficient, and a D / A converting means for converting a digital video signal into an analog signal. Video signal phase correction device characterized by the above. 2. The average phase difference data generating means detects a clock difference detecting means for detecting a time point when the phase difference between the two clocks from the clock generating means reaches a predetermined value, and a period until the predetermined phase difference is reached. The video according to claim 1, further comprising: counting means for measuring, and average phase error data generating means for calculating average phase error data for each unit sampling based on one of the two clocks from the detection result. Signal phase correction device. 3. The interpolation coefficient generation means cumulatively adds the average phase error data from the average phase difference data generation means for each sampling clock, and continuously outputs the phase error data between two types of clocks for each unit sampling. The video signal phase correction apparatus according to claim 1 or 2, further comprising a cumulative addition unit that generates the video signal. 4. A video signal phase correction apparatus for a television receiver, wherein A / D conversion means for converting an analog input video signal into a digital signal, and a predetermined signal synchronized with a burst signal and a horizontal synchronizing signal included in the input video signal. Clock generating means for generating two types of frequency clocks;
An average phase difference data generating means for generating average phase difference data between these two clocks, and an interpolation coefficient for interpolating a plurality of sample data of the input video signal based on the average phase difference data, at predetermined sampling intervals. , An interpolation coefficient generating means for continuously generating an input video signal by the sample data and the interpolation coefficient, a D / A converting means for converting a digital video signal into an analog signal, and the average phase difference data. Standard / non-standard signal mode determining means for determining whether the input video signal is the standard signal mode or the non-standard signal mode based on the phase difference data from the generating means, and at least the non-standard signal based on the determination result. At the same time, the phase correction means corrects the phase of the video signal, and all the system clocks used in this apparatus are set to the above 2 Video signal phase correction apparatus characterized by comprising a selection means for selecting one of the clock classes only. 5. The average phase difference data generation means detects a clock difference detection means for detecting a time point when the phase difference between the two clocks from the clock generation means reaches a predetermined value, and a period until the predetermined phase difference is reached. 5. The video signal according to claim 4, further comprising coefficient means for measuring and average phase error data calculating means for calculating average phase error data for each unit sampling based on one of the two clocks from the detection result. Phase correction device. 6. The standard / non-standard signal mode determination means includes a determination means based on a detection result when the phase difference between two types of clocks in the average phase difference data generation means reaches a predetermined value. The video signal phase correction apparatus according to claim 4 or 5.