JPH0728485A - Alarm device - Google Patents

Alarm device

Info

Publication number
JPH0728485A
JPH0728485A JP19554993A JP19554993A JPH0728485A JP H0728485 A JPH0728485 A JP H0728485A JP 19554993 A JP19554993 A JP 19554993A JP 19554993 A JP19554993 A JP 19554993A JP H0728485 A JPH0728485 A JP H0728485A
Authority
JP
Japan
Prior art keywords
output
frequency
buzzer
logic circuit
frequency dividing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19554993A
Other languages
Japanese (ja)
Inventor
Yukiaki Morita
到明 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19554993A priority Critical patent/JPH0728485A/en
Publication of JPH0728485A publication Critical patent/JPH0728485A/en
Pending legal-status Critical Current

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  • Accessory Devices And Overall Control Thereof (AREA)
  • Emergency Alarm Devices (AREA)

Abstract

PURPOSE:To provide an alarm device which expresses plural sounds and sound patterns employing a single buzzer. CONSTITUTION:The device is provided with two oscillators 1 and 2 which generate different oscillation frequencies and two frequency divider circuits 3 and 4 which operate based on separately inputted control signals and frequency divide the oscillator output that only corresponds to the specified number of frequencies. Moreover, the device is provided with a logic circuit 11 which selects the output of one circuit 3 or 4 within each of the two frequency divider circuits 3 and 4 by an external instruction and a buzzer 13 which operates based on the output of the circuit 11 and outputs different interval vibration sounds in accordance with the output frequency.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、アラーム装置に係り、
とくに複数のブザー音等を発生させるプリンタ装置用と
して好適なアラーム装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm device,
Particularly, the present invention relates to an alarm device suitable for a printer device that generates a plurality of buzzer sounds and the like.

【0002】[0002]

【従来の技術】従来より、プリンタ装置は、一種類のブ
ザー音でプリンタ装置の状態,例えばエラー状態や使用
可能な状態,又は状態の変化をアラームとして表現して
いる(例えば特開昭62−216768号公報)。
2. Description of the Related Art Conventionally, a printer device expresses a state of the printer device, for example, an error state, a usable state, or a change in the state as an alarm with one kind of buzzer sound (for example, JP-A-62-62). 216768).

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
プリンタ装置のブザー音は一種類しか発生しないため、
ブザー音の発生時におけるプリンタ装置の状態は、プリ
ンタ装置の表示部を見るまで区別ができないという不都
合があった。他の警報システムにあっても、同様のもの
が多い。
However, since only one type of buzzer sound is generated in the conventional printer,
There is an inconvenience that the state of the printer device when the buzzer sound is generated cannot be distinguished until the display unit of the printer device is seen. Many other alarm systems are similar.

【0004】[0004]

【発明の目的】本発明は、かかる従来例の有する不都合
を改善し、とくに1個のブザーで複数の音や、音のパタ
ーンで表現するアラーム装置を提供することを、その目
的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the conventional example, and in particular to provide an alarm device which expresses a plurality of sounds and a sound pattern with one buzzer.

【0005】[0005]

【課題を解決するための手段】本発明では、発振周波数
の異なるn個の発振器と、このn個の発振器に個別に対
応して装備され,別に入力される制御信号に基づいて作
動し指定された回数分だけ対応する発振器出力を分周す
るn個の分周回路と、この各n個の分周回路の内の一の
分周回路出力を外部指令によって選択する論理回路と、
この論理回路の出力に応じて作動し当該出力周波数に応
じて異なった音程の振動音を出力するブザーとを備えて
いる、という構成を採っている。これによって前述した
目的を達成しようとするものである。
According to the present invention, n oscillators having different oscillating frequencies and the n oscillators are individually provided so as to operate and designated based on a control signal input separately. N frequency dividing circuits for dividing the corresponding oscillator output by the number of times, and a logic circuit for selecting one frequency dividing circuit output of each of the n frequency dividing circuits by an external command,
A buzzer that operates in response to the output of the logic circuit and that outputs a vibrating sound with a different pitch according to the output frequency is provided. This aims to achieve the above-mentioned object.

【0006】[0006]

【作 用】発振器1及び発振器2は、それぞれ発振周波
数が異なり、分周回路3及び分周回路4の入力信号とし
て出力する。分周回路3及び分周回路4は、発振器1及
び発振器2からの入力信号を、CPUなどにより制御さ
れる周波数決定信号5及び6で指定された回数を分周し
出力する。この分周回路3,4の出力信号14及び15
は、論理回路11に入力される。
[Operation] The oscillator 1 and the oscillator 2 have different oscillation frequencies, and output as an input signal of the frequency dividing circuit 3 and the frequency dividing circuit 4. The frequency dividing circuit 3 and the frequency dividing circuit 4 frequency-divide the input signals from the oscillator 1 and the oscillator 2 by the number of times specified by the frequency determination signals 5 and 6 controlled by the CPU or the like, and output the frequency-divided signals. Output signals 14 and 15 of the frequency dividing circuits 3 and 4
Is input to the logic circuit 11.

【0007】論理回路11は、CPUなどにより制御さ
れる音声パターン信号12によって分周回路の出力信号
14または15のどちらか一方の出力が入力周波数によ
って音程の変化するブザー13に対して有効となるよう
にする。周波数決定信号5及び6で音の高さ(音程)を
制御し、音声パターン信号12で音のパターンが制御さ
れる。
The logic circuit 11 is effective for the buzzer 13 in which the output of either the output signal 14 or 15 of the frequency dividing circuit is changed by the voice pattern signal 12 controlled by the CPU or the like according to the input frequency. To do so. The frequency determination signals 5 and 6 control the pitch (pitch) of the sound, and the voice pattern signal 12 controls the sound pattern.

【0008】[0008]

【実施例】以下、本発明の一実施例を図1乃至図2に基
づいて説明する。この図1乃至図2に示す実施例は、発
振周波数の異なる二個の発振器1,2と、この2個の発
振器1,2に個別に対応して装備され,別に入力される
制御信号に基づいて作動し指定された回数分だけ対応す
る発振器出力を分周する二個の分周回路3,4と、この
各二個の分周回路3,4の内の一の分周回路3又は4の
出力を外部指令によって選択する論理回路11と、この
論理回路11の出力に応じて作動し当該出力周波数に応
じて異なった音程の振動音を出力するブザー13とを備
えている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The embodiment shown in FIGS. 1 and 2 is based on two oscillators 1 and 2 having different oscillating frequencies, and a control signal which is individually provided corresponding to the two oscillators 1 and 2 and is input separately. Are operated to divide the corresponding oscillator output by a specified number of times, and one of the two frequency dividing circuits 3 and 4 is divided by 3 or 4. A logic circuit 11 for selecting the output of 1 according to an external command and a buzzer 13 that operates according to the output of the logic circuit 11 and outputs a vibrating sound of a different pitch according to the output frequency.

【0009】論理回路11は、二個の分周回路3,4の
各々に入力される制御信号により前述したブザー13の
振動周波数を特定すると共に、別に入力される外部指令
によって異なったパターンのブザー信号を出力する機能
を備えている。
The logic circuit 11 specifies the vibration frequency of the buzzer 13 by the control signal input to each of the two frequency dividing circuits 3 and 4, and the buzzer having a different pattern according to an external command input separately. It has a function to output signals.

【0010】これを更に詳述すると、図1に本実施例に
おけるプリンタ装置のブザー回路を示す。この図1の本
実施例では、発振器が2個用いられているが、3個以上
出会ってもよい。
This will be described in more detail. FIG. 1 shows a buzzer circuit of the printer device in this embodiment. Although two oscillators are used in this embodiment of FIG. 1, three or more oscillators may be encountered.

【0011】発振器1及び発振器2は、それぞれ発振周
波数が異なり、分周回路3及び分周回路4の入力信号と
して出力する。分周回路3及び分周回路4は、発振器1
及び発振器2からの入力信号を、CPUなどにより制御
される周波数決定信号5及び6で指定された回数を分周
し出力する。この分周回路3,4の出力信号14及び1
5は、1個のNOT回路8と、3個のNAND回路7,
9及び10で構成される論理回路11に入力される。
The oscillators 1 and 2 have different oscillation frequencies and output as input signals to the frequency dividing circuit 3 and the frequency dividing circuit 4. The frequency dividing circuit 3 and the frequency dividing circuit 4 are the oscillator 1
Also, the input signal from the oscillator 2 is divided by the number of times specified by the frequency determination signals 5 and 6 controlled by the CPU or the like and output. Output signals 14 and 1 of the frequency dividing circuits 3 and 4
5 is one NOT circuit 8 and three NAND circuits 7,
It is input to the logic circuit 11 composed of 9 and 10.

【0012】論理回路11は、CPUなどにより制御さ
れる音声パターン信号12によって分周回路の出力信号
14または15のどちらか一方の出力が入力周波数によ
って音程の変化するブザー13に対して有効となるよう
にする。周波数決定信号5及び6で音の高さ(音程)を
制御し、音声パターン信号12で音のパターンが制御さ
れる。
The logic circuit 11 is effective for the buzzer 13 in which the output of either the output signal 14 or 15 of the frequency dividing circuit is changed by the voice pattern signal 12 controlled by the CPU or the like according to the input frequency. To do so. The frequency determination signals 5 and 6 control the pitch (pitch) of the sound, and the voice pattern signal 12 controls the sound pattern.

【0013】例えば図2のように、分周回路3の出力信
号14の波形がa)で、分周回路4の出力信号15の波
形がb)で、論理回路11に入力する音声パターン信号
12がc)ならば、ブザー13に入力する信号16の波
形はd)となる。このように、入力周波数によって音程
の変化するブザー13の発振音の音程及び音のパターン
が変化する。
For example, as shown in FIG. 2, the waveform of the output signal 14 of the frequency dividing circuit 3 is a), the waveform of the output signal 15 of the frequency dividing circuit 4 is b), and the voice pattern signal 12 input to the logic circuit 11 is shown. Is c), the waveform of the signal 16 input to the buzzer 13 is d). In this way, the pitch and the sound pattern of the oscillating sound of the buzzer 13 whose pitch changes according to the input frequency change.

【0014】ここで、上記図1に示す実施例では、発振
器及び分周回路をそれぞれ二個の場合について例示した
が、3個以上の複数個(n個)であってもよい。この場
合、論理回路11も、この3個以上の複数個(n個)に
対応したものとしてもよい。
In the embodiment shown in FIG. 1, the number of oscillators and the number of frequency dividing circuits are each two, but the number may be three or more (n). In this case, the logic circuit 11 may correspond to a plurality (n) of three or more.

【0015】[0015]

【発明の効果】本発明は以上のように構成され機能する
ので、これによると、1個のブザーを用いて複数の音を
発生させることができるため、ブザー音発生時における
装置の状態が音色等により判別することができるという
従来にない優れたアラーム装置を提供することができ
る。
Since the present invention is constructed and functions as described above, it is possible to generate a plurality of sounds using one buzzer. It is possible to provide an alarm device which is excellent in the past and which can be discriminated by the above.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】図1の動作を示すタイミングチャートである。FIG. 2 is a timing chart showing the operation of FIG.

【符号の説明】[Explanation of symbols]

1,2 発振器 3,4 分周回路 11 論理回路 13 ブザー 1, 2 oscillator 3, 4 frequency divider circuit 11 logic circuit 13 buzzer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 発振周波数の異なるn個の発振器と、こ
のn個の発振器に個別に対応して装備され,別に入力さ
れる制御信号に基づいて作動し指定された回数分だけ対
応する発振器出力を分周するn個の分周回路と、この各
n個の分周回路の内の一の分周回路出力を外部指令によ
って選択する論理回路と、この論理回路の出力に応じて
作動し当該出力周波数に応じて異なった音程の振動音を
出力するブザーとを備えていることを特徴としたアラー
ム装置。
1. An n number of oscillators having different oscillation frequencies, and an oscillator output which is provided corresponding to each of the n number of oscillators, operates based on a control signal input separately, and corresponds to a specified number of times. Of n frequency dividing circuits, a logic circuit that selects one of the frequency dividing circuits of the n frequency dividing circuits by an external command, and operates according to the output of the logic circuit. An alarm device comprising: a buzzer that outputs a vibrating sound having a different pitch according to an output frequency.
【請求項2】 前記論理回路が、前記n個の分周回路の
各々に入力される制御信号により前記ブザーの振動周波
数を特定すると共に、別に入力される外部指令によって
異なったパターンのブザー信号を出力する機能を備えて
いることを特徴とした請求項1記載のアラーム装置。
2. The logic circuit specifies the vibration frequency of the buzzer by a control signal input to each of the n frequency divider circuits, and outputs a buzzer signal having a different pattern according to an external command input separately. The alarm device according to claim 1, wherein the alarm device has a function of outputting.
JP19554993A 1993-07-13 1993-07-13 Alarm device Pending JPH0728485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19554993A JPH0728485A (en) 1993-07-13 1993-07-13 Alarm device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19554993A JPH0728485A (en) 1993-07-13 1993-07-13 Alarm device

Publications (1)

Publication Number Publication Date
JPH0728485A true JPH0728485A (en) 1995-01-31

Family

ID=16342953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19554993A Pending JPH0728485A (en) 1993-07-13 1993-07-13 Alarm device

Country Status (1)

Country Link
JP (1) JPH0728485A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750759B2 (en) 1999-12-07 2004-06-15 Nec Infrontia Corporation Annunciatory signal generating method and device for generating the annunciatory signal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325800A (en) * 1976-08-23 1978-03-09 Kazuhiko Terada Container for disposing low level radioactive waste in deep sea

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5325800A (en) * 1976-08-23 1978-03-09 Kazuhiko Terada Container for disposing low level radioactive waste in deep sea

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6750759B2 (en) 1999-12-07 2004-06-15 Nec Infrontia Corporation Annunciatory signal generating method and device for generating the annunciatory signal

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Effective date: 19961015