JPH042133U - - Google Patents
Info
- Publication number
- JPH042133U JPH042133U JP4198790U JP4198790U JPH042133U JP H042133 U JPH042133 U JP H042133U JP 4198790 U JP4198790 U JP 4198790U JP 4198790 U JP4198790 U JP 4198790U JP H042133 U JPH042133 U JP H042133U
- Authority
- JP
- Japan
- Prior art keywords
- frequency dividing
- circuit
- composite
- multiple systems
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 1
Description
第１図は本考案に係る複合分周回路の一実施例
をクロツク発生回路とともに示すブロツク図、第
２図は第１図の複合分周回路の動作を説明するブ
ロツク図、第３図は本考案の複合分周回路を搭載
する携帯用電子機器の例として電子手帳を概略的
に示すブロツク図、第４図は従来のクロツク発生
回路を示すブロツク図である。
１……キー入力装置、３……ＣＰＵ、５……記
憶回路、７……表示装置、９……クロツク発生回
路、１１，１７……発振回路、１３，２１……ｍ
分周回路、１５，２５……ｎ分周回路、１９……
複合分周回路、２３……ｎ／２分周回路、２７…
…選択回路。
FIG. 1 is a block diagram showing an embodiment of the composite frequency divider circuit according to the present invention together with a clock generation circuit, FIG. 2 is a block diagram explaining the operation of the composite frequency divider circuit of FIG. 1, and FIG. FIG. 4 is a block diagram schematically showing an electronic notebook as an example of a portable electronic device equipped with the invented composite frequency dividing circuit. FIG. 4 is a block diagram showing a conventional clock generating circuit. 1... Key input device, 3... CPU, 5... Memory circuit, 7... Display device, 9... Clock generation circuit, 11, 17... Oscillation circuit, 13, 21... m
Frequency divider circuit, 15, 25...n frequency divider circuit, 19...
Composite frequency divider circuit, 23... n/2 frequency divider circuit, 27...
...selection circuit.
Claims (1)
複数系統で互に異なる周波数のクロツク信号を出
力する複合分周回路において、 前記複数系統のうち少なくとも１系統が、異な
る分周数の複数の分周回路およびこれらの分周回
路を選択する選択回路を有することを特徴とする
複合分周回路。[Claims for Utility Model Registration] In a composite frequency dividing circuit that is integrated into one and divides a fundamental frequency signal and outputs clock signals of different frequencies in multiple systems, at least one of the multiple systems. A composite frequency dividing circuit comprising a plurality of frequency dividing circuits having different frequency dividing numbers and a selection circuit for selecting these frequency dividing circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4198790U JPH042133U (en) | 1990-04-19 | 1990-04-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4198790U JPH042133U (en) | 1990-04-19 | 1990-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH042133U true JPH042133U (en) | 1992-01-09 |
Family
ID=31553133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4198790U Pending JPH042133U (en) | 1990-04-19 | 1990-04-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042133U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49117575U (en) * | 1973-02-01 | 1974-10-08 |
-
1990
- 1990-04-19 JP JP4198790U patent/JPH042133U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49117575U (en) * | 1973-02-01 | 1974-10-08 |
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