JPH05130391A - Dither generator - Google Patents

Dither generator

Info

Publication number
JPH05130391A
JPH05130391A JP2404162A JP40416290A JPH05130391A JP H05130391 A JPH05130391 A JP H05130391A JP 2404162 A JP2404162 A JP 2404162A JP 40416290 A JP40416290 A JP 40416290A JP H05130391 A JPH05130391 A JP H05130391A
Authority
JP
Japan
Prior art keywords
output
dither
flip
flops
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2404162A
Other languages
Japanese (ja)
Inventor
Yasuo Yonezawa
沢 安 雄 米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Machinery Ltd
Original Assignee
Murata Machinery Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Machinery Ltd filed Critical Murata Machinery Ltd
Priority to JP2404162A priority Critical patent/JPH05130391A/en
Publication of JPH05130391A publication Critical patent/JPH05130391A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the need for a ROM used to store a dither pattern and to revise optionally the dither pattern. CONSTITUTION:Unstable multivibrators 1a-1d as plural oscillation means oscillate a pulse signal of a frequency not in the relation of a common multiple to each other. D flip-flops 2a-2d as plural sampling means sample outputs of the astable multivibrators 1a-1d for each prescribed time. Thus, a binary signal with a prescribed bit number changed irregularly for each prescribed time is obtained. A multiplier 3 as a multiplier means applies weighting in response to a level to each output of the D flip-flops 2a-2d and calculates the product. Thus, an irregular output changing for each prescribed time is obtained in which an appearance ratio of a large number and a small number is smaller than an appearance ratio of an intermediate number.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えばディザ法を利用
して階調記録を行うファクシミリ装置等に用いられるデ
ィザ発生装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dither generator used in, for example, a facsimile machine for performing gradation recording using a dither method.

【0002】[0002]

【従来の技術】従来のディザ発生装置は、ディザ・パタ
ーンをROMに記憶させていた。
2. Description of the Related Art A conventional dither generator stores a dither pattern in a ROM.

【0003】[0003]

【発明が解決しようとする課題】しかし従来のディザ発
生装置では、ディザ・パターンを記憶するROMが必要
であり、製作コストが高価であった。また、ディザ・パ
ターンを任意に変更することができなかった。本発明は
かかる従来の問題点に鑑みてなされたもので、ディザ・
パターンを記憶するためのROMが不要で、しかもディ
ザ・パターンを任意に変更できるディザ発生装置を提供
することを目的とする。
However, in the conventional dither generator, the ROM for storing the dither pattern is required, and the manufacturing cost is high. Moreover, the dither pattern could not be changed arbitrarily. The present invention has been made in view of the above-mentioned conventional problems.
It is an object of the present invention to provide a dither generation device which does not require a ROM for storing patterns and which can arbitrarily change a dither pattern.

【0004】[0004]

【課題を解決するための手段】本発明は、相互に倍数関
係にない周波数のパルス信号を発振する複数の発振手段
と、これら発振手段の出力を所定時間毎にサンプリング
する複数のサンプリング手段と、これらサンプリング手
段の各出力にそのレベルに応じた重み付けをしてそれら
の積を演算する乗算手段とを設けたことを特徴とする。
SUMMARY OF THE INVENTION The present invention comprises a plurality of oscillating means for oscillating pulse signals having frequencies that are not in a multiple relationship with each other, and a plurality of sampling means for sampling the outputs of these oscillating means at predetermined time intervals. It is characterized in that each output of these sampling means is provided with a multiplying means for weighting according to its level and calculating a product of them.

【0005】[0005]

【作用】複数の発振手段は、相互に倍数関係にない周波
数のパルス信号を発振する。複数のサンプリング手段
は、発振手段の出力を所定時間毎にサンプリングする。
これにより、所定時間毎に不規則に変化する所定ビット
数の2値信号が得られる。乗算手段は、サンプリング手
段の各出力にそのレベルに応じた重み付けをしてそれら
の積を演算する。これにより、大きい数および小さい数
の出現率が中間の数の出現率よりも小さい、所定時間毎
に変化する不規則な出力が得られる。したがって、ディ
ザ・パターンを記憶するためのROMが不要である。ま
た発振手段の発振周波数やデューティー比を変化させる
ことによりディザ・パターンを任意に変更できる。また
大きい数および小さい数の出現率が中間の数の出現率よ
りも小さいので、極端なディザによるノイズ感を軽減で
きる。
The plurality of oscillating means oscillate pulse signals having frequencies that are not in a multiple relationship with each other. The plurality of sampling means samples the output of the oscillating means at predetermined time intervals.
As a result, a binary signal having a predetermined number of bits that changes irregularly every predetermined time is obtained. The multiplying unit weights each output of the sampling unit according to its level and calculates the product of them. As a result, an irregular output is obtained in which the appearance rates of the large number and the small number are smaller than the appearance rate of the intermediate number, and which change every predetermined time. Therefore, no ROM is required to store the dither pattern. Further, the dither pattern can be arbitrarily changed by changing the oscillation frequency or duty ratio of the oscillation means. Further, since the appearance rates of the large number and the small number are smaller than the appearance rate of the intermediate number, it is possible to reduce the noise feeling due to the extreme dither.

【0006】[0006]

【実施例】以下に本発明を図面に示す実施例に基づいて
説明する。図1は本発明の一実施例におけるディザ発生
装置の回路図で、発振手段としての非安定マルチバイブ
レータ1a〜1dの出力端はサンプリング手段としての
Dフリップフロップ2a〜2dの入力端に接続されてい
る。Dフリップフロップ2a〜2dの出力端は乗算手段
としての乗算器3の入力端に接続されており、Dフリッ
プフロップ2a〜2dのクロック入力端には所定周波数
のサンプリングクロックが入力される。乗算器3は、A
ND回路4a〜4kと、EX−OR回路5a,5bと、
NOR回路6a,6bと、OR回路7a〜7cとにより
構成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the drawings. FIG. 1 is a circuit diagram of a dither generator according to an embodiment of the present invention, in which the output terminals of the unstable multivibrator 1a to 1d as the oscillating means are connected to the input terminals of the D flip-flops 2a to 2d as the sampling means. There is. The output terminals of the D flip-flops 2a to 2d are connected to the input terminals of a multiplier 3 as a multiplication means, and the sampling clocks of a predetermined frequency are input to the clock input terminals of the D flip-flops 2a to 2d. The multiplier 3 is A
ND circuits 4a to 4k, EX-OR circuits 5a and 5b,
It is composed of NOR circuits 6a and 6b and OR circuits 7a to 7c.

【0007】次に動作を説明する。非安定マルチバイブ
レータ1a〜1dは、図2のようなパルス信号a〜dを
出力する。すなわち非安定マルチバイブレータ1a〜1
dは、相互に異なった、かつ相互に倍数関係にない発振
周波数で発振する。Dフリップフロップ2a〜2dは、
図2のようなサンプリングクロックeの立ち上がりで非
安定マルチバイブレータ1a〜1dの出力であるパルス
信号a〜dをラッチし、図2のようなパルス信号f〜i
を出力する。乗算器3は、Dフリップフロップ2a〜2
dの出力であるパルス信号f〜iの各々が、ローレベル
であれば「1」、ハイレベルであれば「2」、という重
み付けを行って、パルス信号f〜iの積を演算し、図2
のjのような出力を出力端に供給する。すなわち乗算器
3の入出力は、図3のような真理値表に基づいて決定さ
れる。
Next, the operation will be described. The unstable multivibrators 1a to 1d output pulse signals a to d as shown in FIG. That is, the non-stable multivibrator 1a-1
d oscillates at oscillation frequencies different from each other and not in a multiple relationship with each other. The D flip-flops 2a to 2d are
At the rising edge of the sampling clock e as shown in FIG. 2, the pulse signals a to d output from the unstable multivibrators 1a to 1d are latched, and the pulse signals f to i as shown in FIG.
Is output. The multiplier 3 includes D flip-flops 2a to 2
Each of the pulse signals f to i, which is the output of d, is weighted as "1" if it is a low level and "2" if it is a high level, and the product of the pulse signals f to i is calculated. Two
An output such as j of is supplied to the output end. That is, the input / output of the multiplier 3 is determined based on the truth table as shown in FIG.

【0008】このように、ディザ・パターンを記憶する
ためのROMを用いることなく、ディザを出力できる。
また非安定マルチバイブレータ1a〜1dの発振周波数
やデューティー比を変化させることによりディザ・パタ
ーンを任意に変更できる。また乗算器3を設けたので、
大きい数および小さい数の出現率が中間の数の出現率よ
りも小さいことから、極端なディザによるノイズ感を軽
減できる。
As described above, the dither can be output without using the ROM for storing the dither pattern.
Further, the dither pattern can be arbitrarily changed by changing the oscillation frequency or duty ratio of the unstable multivibrators 1a to 1d. Since the multiplier 3 is provided,
Since the appearance rates of the large number and the small number are smaller than the appearance rate of the intermediate number, it is possible to reduce the noise feeling due to the extreme dither.

【0009】なお、上記実施例ではDフリップフロップ
2a〜2dの各出力に対して、ローレベルであれば
「1」、ハイレベルであれば「2」という重み付けを行
ったが、必ずしもこのようにする必要はなく、任意の重
み付けをなし得る。
In the above embodiment, the outputs of the D flip-flops 2a to 2d are weighted as "1" for low level and "2" for high level, but this is not always the case. It is not necessary to do so, and arbitrary weighting can be performed.

【0010】[0010]

【発明の効果】以上説明したように本発明によれば、相
互に倍数関係にない周波数のパルス信号を発振する複数
の発振手段と、これら発振手段の出力を所定時間毎にサ
ンプリングする複数のサンプリング手段と、これらサン
プリング手段の各出力にそのレベルに応じた重み付けを
してそれらの積を演算する乗算手段とを設けたので、デ
ィザ・パターンを記憶するためのROMを用いることな
く、ディザを出力できる。また発振手段の発振周波数や
デューティー比を変化させることにより、ディザ・パタ
ーンを任意に変更できる。また乗算手段を設けたので、
大きい数および小さい数の出現率が中間の数の出現率よ
りも小さいことから、極端なディザによるノイズ感を軽
減できる。
As described above, according to the present invention, a plurality of oscillating means for oscillating pulse signals having frequencies that are not in a multiple relationship with each other, and a plurality of sampling means for sampling the outputs of these oscillating means at predetermined time intervals. Means and a multiplying means for calculating the product of the outputs of the sampling means by weighting the outputs according to the level thereof, the dither is output without using the ROM for storing the dither pattern. it can. Moreover, the dither pattern can be arbitrarily changed by changing the oscillation frequency or the duty ratio of the oscillation means. In addition, because the multiplication means is provided,
Since the appearance rates of the large number and the small number are smaller than the appearance rate of the intermediate number, it is possible to reduce the noise feeling due to the extreme dither.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるディザ発生装置の回
路図である。
FIG. 1 is a circuit diagram of a dither generator according to an embodiment of the present invention.

【図2】図1の回路の各部信号波形図である。FIG. 2 is a signal waveform diagram of each part of the circuit of FIG.

【図3】乗算器の入出力の説明図である。FIG. 3 is an explanatory diagram of input / output of a multiplier.

【符号の説明】[Explanation of symbols]

1a〜1d 非安定マルチバイブレータ(発振手段) 2a〜2d Dフリップフロップ(サンプリング手
段) 3 乗算器(乗算手段)
1a to 1d Astable multivibrator (oscillating means) 2a to 2d D flip-flop (sampling means) 3 Multiplier (multiplying means)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 相互に倍数関係にない周波数のパルス信
号を発振する複数の発振手段と、これら発振手段の出力
を所定時間毎にサンプリングする複数のサンプリング手
段と、これらサンプリング手段の各出力にそのレベルに
応じた重み付けをしてそれらの積を演算する乗算手段と
を設けたことを特徴とするディザ発生装置。
1. A plurality of oscillating means for oscillating pulse signals having frequencies that are not in a multiple relationship with each other, a plurality of sampling means for sampling the outputs of these oscillating means at predetermined time intervals, and a plurality of outputs for each of these sampling means. A dither generating device, comprising: a multiplying unit that performs weighting according to a level and calculates a product of them.
JP2404162A 1990-12-20 1990-12-20 Dither generator Pending JPH05130391A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2404162A JPH05130391A (en) 1990-12-20 1990-12-20 Dither generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2404162A JPH05130391A (en) 1990-12-20 1990-12-20 Dither generator

Publications (1)

Publication Number Publication Date
JPH05130391A true JPH05130391A (en) 1993-05-25

Family

ID=18513858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2404162A Pending JPH05130391A (en) 1990-12-20 1990-12-20 Dither generator

Country Status (1)

Country Link
JP (1) JPH05130391A (en)

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