JPH07263451A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07263451A
JPH07263451A JP6051660A JP5166094A JPH07263451A JP H07263451 A JPH07263451 A JP H07263451A JP 6051660 A JP6051660 A JP 6051660A JP 5166094 A JP5166094 A JP 5166094A JP H07263451 A JPH07263451 A JP H07263451A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
substrate
connection
protruding electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6051660A
Other languages
Japanese (ja)
Inventor
Kazuhiko Torii
和彦 鳥居
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP6051660A priority Critical patent/JPH07263451A/en
Publication of JPH07263451A publication Critical patent/JPH07263451A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a bare chip mounting method having circuit selectivity, as a general mounting method having mass-productivity. CONSTITUTION:The title semiconductor device is provided with a protruding electrode 25 constituted of solder on a connection electrode pad of a connection terminal 26a of a semiconductor device 21, and a protruding electrode 25 constituted of solder whose melting point is higher than that of the protruding electrode 25 of the connection terminal 26a of the semiconductor device 21 on the connection electrode pad of a circuit selection terminal 26b of the semiconductor device 21.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に設けるハ
ンダからなる突起電極と基板との接続に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection between a substrate and a protruding electrode made of solder provided on a semiconductor device.

【0002】[0002]

【従来の技術】電子機器の軽薄短小化の強い要求から半
導体装置の実装においても、実装面積が小さく実装厚が
薄いベアチップ実装が普及している。さらに、製品開発
の激化に伴い、新製品のサイクルが短くなり、短期間で
の製品開発も重要視され、半導体装置メーカではゲート
アレーやスタンダードセルなどの方法で対応している。
2. Description of the Related Art Bare-chip mounting, which has a small mounting area and a small mounting thickness, has been widely used in mounting semiconductor devices because of the strong demand for light, thin, short and small electronic devices. Furthermore, as product development has become more intense, the cycle of new products has become shorter, and it is important to develop products in a short period of time. Semiconductor device manufacturers are responding with methods such as gate arrays and standard cells.

【0003】さらに近年では、アセンブリメーカが対応
できる、回路選択性のあるベアチップ実装が注目されて
いる。この回路選択性のあるベアチップ実装として、下
記記載の実装例が知られている。
Further, in recent years, bare chip mounting with circuit selectivity, which can be handled by an assembly maker, has been receiving attention. As the bare chip mounting having the circuit selectivity, the mounting examples described below are known.

【0004】この従来例によれば、半導体装置の接続電
極パッド上に複数の高さの異なる突起電極を形成した半
導体装置と基板とを、厚さ方向に導電性を有し横方向に
導電性を持たない異方性導電接着剤を用いて接続する。
According to this conventional example, a semiconductor device having a plurality of protruding electrodes having different heights formed on connection electrode pads of the semiconductor device and a substrate are electrically conductive in the thickness direction and electrically conductive in the lateral direction. Connect using an anisotropic conductive adhesive that does not have.

【0005】このとき異方性導電接着剤の導電粒の大き
さを選んで実装することにより、端子と基板とを導通あ
るいは絶縁を選択することが可能となる。
At this time, by selecting and mounting the size of the conductive particles of the anisotropic conductive adhesive, it is possible to select conduction or insulation between the terminal and the substrate.

【0006】このことにより、半導体装置の外付け用の
抵抗素子や容量素子などを半導体装置内部に作り込み、
実装工程でトリミングを行なえる。さらにこの技術を発
展させると、半導体装置内部に機能別の回路を作り込
み、実装工程で任意の回路を選択することができる。
As a result, the external resistance element and capacitance element of the semiconductor device are built in the semiconductor device,
Trimming can be done in the mounting process. If this technique is further developed, circuits for each function can be built in the semiconductor device, and an arbitrary circuit can be selected in the mounting process.

【0007】この従来例を図5と図6と図7とを用いて
説明する。図5と図6は半導体装置21と基板11に配
置した接続電極12とを異方性導電接着剤28を用いて
接続した構造を示す断面図であり、図7は半導体装置2
1と基板11とを押圧するための治具を示す断面図であ
る。
This conventional example will be described with reference to FIGS. 5, 6, and 7. 5 and 6 are cross-sectional views showing a structure in which the semiconductor device 21 and the connection electrode 12 arranged on the substrate 11 are connected using an anisotropic conductive adhesive 28, and FIG. 7 is a semiconductor device 2
It is sectional drawing which shows the jig for pressing 1 and the board | substrate 11. FIG.

【0008】まずはじめに、この従来例の実装構造を説
明する。図5に示すように、半導体装置21の半導体素
子形成領域に設けた抵抗素子30の両端の基板11との
接続用端子26aと、抵抗素子30の中央部の回路選択
用端子26bとに配置した突起電極25を設けた半導体
装置21と、基板11の表面に形成した接続電極12を
有する基板11と、主材28a、導電粒28b、非導電
粒28cからなる異方性導電接着剤28とで構成する。
First, the mounting structure of this conventional example will be described. As shown in FIG. 5, the terminals 26a for connecting to the substrate 11 on both ends of the resistance element 30 provided in the semiconductor element formation region of the semiconductor device 21 and the circuit selection terminal 26b in the central portion of the resistance element 30 are arranged. The semiconductor device 21 provided with the protruding electrodes 25, the substrate 11 having the connection electrodes 12 formed on the surface of the substrate 11, and the anisotropic conductive adhesive 28 composed of the main material 28a, the conductive particles 28b, and the non-conductive particles 28c. Constitute.

【0009】半導体装置21の回路選択用端子26bの
突起電極25は、接続用端子26aの突起電極25より
高さを低く形成することを特徴としている。
The projection electrode 25 of the circuit selection terminal 26b of the semiconductor device 21 is characterized in that it is formed to be lower than the projection electrode 25 of the connection terminal 26a.

【0010】図5に示す実装構造においては、半導体装
置21の回路選択用端子26bの突起電極25を基板1
1と導通しないように、異方性導電接着剤28中に含ま
れる導電粒28bの大きさを、接続用端子26aの突起
電極25の高さ寸法と回路選択用端子26bの突起電極
25の高さ寸法の差に、異方性導電接着剤28の非導電
粒28c大きさを加えた大きさより小さいものを選択し
て接続する。
In the mounting structure shown in FIG. 5, the protruding electrode 25 of the circuit selecting terminal 26b of the semiconductor device 21 is connected to the substrate 1.
1 so that the conductive particles 28b contained in the anisotropic conductive adhesive 28 have a height dimension of the protruding electrode 25 of the connecting terminal 26a and a height of the protruding electrode 25 of the circuit selecting terminal 26b. A size smaller than the size of the anisotropic conductive adhesive 28 plus the size of the non-conductive particles 28c is selected and connected.

【0011】一例として接続用端子26aの突起電極2
5の高さ寸法を20μm、回路選択用端子26bの突起
電極25の高さ寸法を15μm、異方性導電接着剤28
の非導電粒28c大きさを8μmの場合、異方性導電接
着剤28の導電粒28bの大きさを13μm未満にす
る。
As an example, the protruding electrode 2 of the connection terminal 26a
5 has a height of 20 μm, the protruding electrode 25 of the circuit selection terminal 26b has a height of 15 μm, and the anisotropic conductive adhesive 28 is used.
When the size of the non-conductive particles 28c is 8 μm, the size of the conductive particles 28b of the anisotropic conductive adhesive 28 is less than 13 μm.

【0012】図5に示す実装構造の場合、半導体装置2
1の回路選択用端子26bの突起電極25は基板11と
導通しないので、基板11に配置した接続電極12の両
端には、半導体装置11に形成した抵抗素子30の抵抗
値になる。
In the case of the mounting structure shown in FIG. 5, the semiconductor device 2
Since the protruding electrode 25 of the first circuit selection terminal 26b is not electrically connected to the substrate 11, the resistance value of the resistance element 30 formed on the semiconductor device 11 is at both ends of the connection electrode 12 arranged on the substrate 11.

【0013】また図6に示す実装構造は、半導体装置2
1の回路選択用端子26bの突起電極25を基板11と
導通するように、図5で使用した異方性導電接着剤28
の導電粒28bよりも大きい13μm以上ものを選択す
る。
The mounting structure shown in FIG. 6 has a semiconductor device 2
The anisotropic conductive adhesive 28 used in FIG. 5 so that the protruding electrode 25 of the first circuit selection terminal 26b is electrically connected to the substrate 11.
13 μm or more, which is larger than the conductive particles 28 b in FIG.

【0014】この実装構造の場合、基板11に配置した
接続電極12の両端には、半導体装置11に形成した抵
抗素子30の2分の1の抵抗値になる。
In the case of this mounting structure, the resistance value at one end of the connection electrode 12 arranged on the substrate 11 is half that of the resistance element 30 formed on the semiconductor device 11.

【0015】つぎに、この従来例の製造方法について説
明する。図5に示すように、半導体装置21の半導体素
子形成領域に抵抗素子30を不純物拡散層やポリシリコ
ン層によって形成する。
Next, the manufacturing method of this conventional example will be described. As shown in FIG. 5, the resistance element 30 is formed of an impurity diffusion layer or a polysilicon layer in the semiconductor element formation region of the semiconductor device 21.

【0016】抵抗素子30の両端に基板11との接続用
端子26aと、抵抗素子30の中央部に回路選択用端子
26bを設ける。
Terminals 26a for connecting to the substrate 11 are provided at both ends of the resistance element 30, and a circuit selection terminal 26b is provided at the center of the resistance element 30.

【0017】半導体装置21の半導体素子形成表面に設
けたアルミニウムからなる接続電極パッド22が開口露
出するように保護膜23を形成する。この保護膜23は
一般的に燐を含有したシリコン酸化膜、窒化シリコン膜
などの無機質膜や、ポリイミド樹脂などの有機質膜や、
これらの積層構造を用いる。
A protective film 23 is formed so that the connection electrode pad 22 made of aluminum provided on the surface of the semiconductor device 21 on which the semiconductor element is formed is exposed. This protective film 23 is generally an inorganic film such as a silicon oxide film or a silicon nitride film containing phosphorus, an organic film such as a polyimide resin, or the like.
These laminated structures are used.

【0018】さらに半導体装置21の全面にアルミニウ
ム、クロム、銅、ニッケル、チタンなどの金属多層膜を
共通電極膜24として、スパッタリング法や真空蒸着法
などの方法で形成する。
Further, a metal multi-layer film of aluminum, chromium, copper, nickel, titanium or the like is formed as the common electrode film 24 on the entire surface of the semiconductor device 21 by a method such as a sputtering method or a vacuum evaporation method.

【0019】さらに感光性樹脂からなるメッキレジスト
を形成し、メッキ処理を行い接続用端子26aの共通電
極膜24の上に突起電極25を設ける。
Further, a plating resist made of a photosensitive resin is formed, and a plating process is performed to form a protruding electrode 25 on the common electrode film 24 of the connecting terminal 26a.

【0020】メッキレジストを除去後再度、メッキレジ
ストを形成し、メッキ処理を行い接続用端子26aと回
路選択用端子26bの共通電極膜24の上に突起電極2
5を設ける。
After removing the plating resist, the plating resist is formed again, and a plating process is performed to form the protruding electrode 2 on the common electrode film 24 of the connection terminal 26a and the circuit selection terminal 26b.
5 is provided.

【0021】突起電極25は銅、金、ニッケル、アルミ
ニウムなどの金属膜および金属多層膜を用いる。
For the protruding electrode 25, a metal film of copper, gold, nickel, aluminum or the like and a metal multilayer film are used.

【0022】不要になった共通電極膜24とメッキレジ
ストを除去して、接続用端子26aの突起電極25より
高さを低く形成した、回路選択用端子26bの突起電極
25を有する半導体装置21が完成する。
The semiconductor device 21 having the protruding electrode 25 of the circuit selecting terminal 26b, which is formed to have a height lower than that of the protruding electrode 25 of the connecting terminal 26a by removing the unnecessary common electrode film 24 and the plating resist, is provided. Complete.

【0023】基板11は紙フェノールや紙エポキシなど
の有機質材料やアルミナセラミックや結晶化ガラスなど
の無機質材料、またはガラスエポキシなどの有機質無機
質材料からなる。
The substrate 11 is made of an organic material such as paper phenol or paper epoxy, an inorganic material such as alumina ceramic or crystallized glass, or an organic inorganic material such as glass epoxy.

【0024】この基板11の表面全面に、銅、銀、金な
どの金属をメッキ法、圧延法、真空蒸着法、スパッタリ
ング法などなどで接続電極12を形成する。
The connection electrode 12 is formed on the entire surface of the substrate 11 by a metal such as copper, silver or gold by a plating method, a rolling method, a vacuum deposition method, a sputtering method or the like.

【0025】また、液晶表示装置の場合、基板11はガ
ラスを、接続電極12は酸化インジウムスズを用いる。
In the case of a liquid crystal display device, the substrate 11 is made of glass and the connection electrode 12 is made of indium tin oxide.

【0026】この接続電極12を感光性樹脂からなるレ
ジストを用いて、フォトリソグラフィーとエッチングで
配線のパターンを形成する。その後、不要になったレジ
ストを除去する。
A wiring pattern is formed on the connection electrode 12 by photolithography and etching using a resist made of a photosensitive resin. After that, the resist that is no longer needed is removed.

【0027】異方性導電接着剤28は、ガラスペースト
などの無機質材料やエポキシ樹脂、ポリエステル樹脂な
どの有機質材料からなる主材28aと、弾性を有するス
チレンとジビニルベンゼンとの共重合体からなるプラス
ティックビーズにニッケル、アルミニウム、金、銀など
の金属を、1種または2種以上をメッキ処理してなる導
電粒28bと、グラスファイバや金属酸化物などの無機
質材料やポリメチルメタクリレートなどの硬度の高い有
機質材料で形成されたビーズからなる非導電粒28cと
で構成する。
The anisotropic conductive adhesive 28 is composed of a main material 28a made of an inorganic material such as glass paste or an organic material such as epoxy resin or polyester resin, and a plastic made of an elastic copolymer of styrene and divinylbenzene. Conductive particles 28b obtained by plating beads with a metal such as nickel, aluminum, gold, and silver, or one or more of them, and inorganic materials such as glass fiber and metal oxide, and high hardness such as polymethylmethacrylate It is composed of non-conductive particles 28c made of beads formed of an organic material.

【0028】異方性導電接着剤28はロール混練により
主材28aに導電粒28b、非導電粒28cを混ぜ合わ
せ、印刷法によって接続電極12を配置した基板11に
適量塗布し仮焼成する。
The anisotropic conductive adhesive 28 is prepared by mixing the main material 28a with the conductive particles 28b and the non-conductive particles 28c by roll kneading, applying an appropriate amount on the substrate 11 on which the connection electrodes 12 are arranged by a printing method, and pre-baking.

【0029】図7に示すように、異方性導電接着剤28
を仮焼成した基板11と半導体装置21とを位置合わせ
した後、ヒータ33を設置した上金型31と下金型32
に配置して高温で圧力を加えながら異方性導電接着剤を
硬化させる。
As shown in FIG. 7, anisotropic conductive adhesive 28
After aligning the substrate 11 and the semiconductor device 21, which have been calcined, an upper die 31 and a lower die 32 on which a heater 33 is installed.
And the anisotropic conductive adhesive is cured while applying pressure at high temperature.

【0030】以上のように、異方性導電接着剤28の導
電粒28bの大きさを選んで実装することにより、半導
体装置21の内部に形成した抵抗素子30をトリミング
することが可能となる。
As described above, by selecting and mounting the size of the conductive particles 28b of the anisotropic conductive adhesive 28, the resistance element 30 formed inside the semiconductor device 21 can be trimmed.

【0031】また、抵抗素子以外に、容量素子などにも
対応でき、インバータ回路を作り込めば、信号を反転す
ることも可能となる。
Further, in addition to the resistance element, it can be applied to a capacitance element and the like, and if an inverter circuit is built in, the signal can be inverted.

【0032】[0032]

【発明が解決しようとする課題】上述した従来例では、
異方性導電接着剤を用いることを前提としている。半導
体装置の突起電極と基板の接続電極との接続は、異方性
導電接着剤の導電粒の機械的接続だけであるため、突起
電極の高さのばらつきや異方性導電接着剤の導電粒およ
び非導電粒の大きさのばらつきの影響を受けやすい。
In the above-mentioned conventional example,
It is assumed that an anisotropic conductive adhesive is used. Since the connection between the projection electrode of the semiconductor device and the connection electrode of the substrate is only mechanical connection of the conductive particles of the anisotropic conductive adhesive, there are variations in the height of the projection electrode and the conductive particles of the anisotropic conductive adhesive. It is also susceptible to variations in the size of the non-conductive particles.

【0033】とくに半導体装置の突起電極形成は大口径
のウエハ状態で処理を行うため、高さの均一な突起電極
を形成することは非常に難しい。突起電極の高さ、異方
性導電接着剤の導電粒および非導電粒の大きさによって
異なるが、すくなくとも1〜2μmの範囲で、すべての
ばらつき抑えなければならない。そのため微細な多端子
で大型の半導体装置の実装には不向きである。
In particular, since the projection electrodes of a semiconductor device are processed in a wafer having a large diameter, it is very difficult to form the projection electrodes having a uniform height. Although it depends on the height of the protruding electrodes and the sizes of the conductive particles and the non-conductive particles of the anisotropic conductive adhesive, it is necessary to suppress all variations within the range of at least 1 to 2 μm. Therefore, it is not suitable for mounting a large semiconductor device with fine multi-terminals.

【0034】またさらに、異方性導電接着剤は高温で圧
力を加えながら硬化させるため、上金型、下金型のよう
な専用治具が必要である。上金型の半導体装置を押圧す
る面と、下金型の基板を配置する面との平行度および平
坦度が強く要求される。
Furthermore, since the anisotropic conductive adhesive is cured at a high temperature while applying pressure, a special jig such as an upper mold and a lower mold is required. There is a strong demand for parallelism and flatness between the surface of the upper mold for pressing the semiconductor device and the surface of the lower mold for disposing the substrate.

【0035】この課題を解決するため本発明の目的は、
回路選択性のあるベアチップ実装を量産性のある一般的
な実装で提供することにある。
The object of the present invention for solving this problem is to:
It is to provide bare chip mounting with circuit selectivity as a general mounting with mass productivity.

【0036】[0036]

【課題を解決するための手段】上記課題を解決するため
本発明の半導体装置においては、下記記載の構成を採用
する。
In order to solve the above problems, the semiconductor device of the present invention adopts the following structure.

【0037】本発明の半導体装置においては、半導体装
置の接続用端子の接続電極パッド上のハンダからなる突
起電極と、半導体装置の回路選択用端子の接続電極パッ
ド上の半導体装置の接続用端子の突起電極より融点の高
いハンダからなる突起電極とを有することを特徴とす
る。
In the semiconductor device of the present invention, the protruding electrode made of solder on the connection electrode pad of the connection terminal of the semiconductor device and the connection terminal of the semiconductor device on the connection electrode pad of the circuit selection terminal of the semiconductor device And a protruding electrode made of solder having a melting point higher than that of the protruding electrode.

【0038】[0038]

【作用】半導体装置に設けた回路選択用端子の突起電極
は、半導体装置の接続用端子の突起電極より融点の高い
ハンダを採用している。このため基板と半導体装置を接
続するためのハンダの溶融温度を制御して回路選択性の
あるベアチップ実装を実現している。
The protruding electrode of the circuit selecting terminal provided on the semiconductor device employs solder having a higher melting point than the protruding electrode of the connecting terminal of the semiconductor device. Therefore, by controlling the melting temperature of solder for connecting the substrate and the semiconductor device, bare chip mounting with circuit selectivity is realized.

【0039】[0039]

【実施例】以下、本発明による実施例を図面に基づいて
説明する。図1と図2とは半導体装置の実装構造を示す
断面図であり、図3は突起電極を形成した半導体装置を
示す断面図であり、図4は半導体装置との接続部分の基
板の接続電極を示す平面図である。
Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are cross-sectional views showing a mounting structure of a semiconductor device, FIG. 3 is a cross-sectional view showing a semiconductor device in which a protruding electrode is formed, and FIG. 4 is a connection electrode of a substrate at a connection portion with the semiconductor device. FIG.

【0040】まずはじめに、図1を用いて半導体装置と
基板との実装構造を説明する。図1に示すように、半導
体装置21の半導体素子形成領域に設けた抵抗素子30
の両端の基板11との接続用端子26aと、抵抗素子3
0の中央部の回路選択用端子26bとに配置したハンダ
からなる突起電極25を設けた半導体装置21と、基板
11の表面に形成した接続電極12と半導体装置21と
の接続部分の接続電極12が開口露出するように形成し
たカバー絶縁膜13を有する基板11と、半導体装置2
1と基板11との間に配置した封止樹脂27とで構成す
る。
First, the mounting structure of the semiconductor device and the substrate will be described with reference to FIG. As shown in FIG. 1, the resistance element 30 provided in the semiconductor element formation region of the semiconductor device 21.
26a for connecting to the substrate 11 at both ends of the
0, the semiconductor device 21 provided with the projecting electrode 25 made of solder and arranged on the circuit selection terminal 26b in the central portion of 0, the connection electrode 12 formed on the surface of the substrate 11, and the connection electrode 12 at the connection portion of the semiconductor device 21. A substrate 11 having a cover insulating film 13 formed so that the openings are exposed, and a semiconductor device 2
1 and the sealing resin 27 disposed between the substrate 11.

【0041】つぎに図3を用いて半導体装置の構造を説
明する。図3に示すように、半導体装置21の半導体素
子形成面にある接続電極パッド22が開口露出するよう
に保護膜23を設け、接続電極パッド22表面に共通電
極膜24さらにハンダからなる突起電極25を形成す
る。回路選択用端子26bの突起電極25は、接続用端
子26aの突起電極25より融点の高いハンダで形成す
る。
Next, the structure of the semiconductor device will be described with reference to FIG. As shown in FIG. 3, a protective film 23 is provided so that the connection electrode pad 22 on the semiconductor element formation surface of the semiconductor device 21 is exposed and the common electrode film 24 and a protruding electrode 25 made of solder are formed on the surface of the connection electrode pad 22. To form. The protruding electrode 25 of the circuit selecting terminal 26b is formed of solder having a higher melting point than the protruding electrode 25 of the connecting terminal 26a.

【0042】つぎに図4を用いて基板の構造を説明す
る。図4に示すように、基板11は接続電極12とカバ
ー絶縁膜13で構成する。カバー絶縁膜13は、半導体
装置との接続部分の接続電極12が開口露出し、かつ溶
融させない突起電極が接続電極12と接触しないよう
に、半導体装置との接続部分の接続電極12の表面にも
島状に設ける。
Next, the structure of the substrate will be described with reference to FIG. As shown in FIG. 4, the substrate 11 is composed of the connection electrode 12 and the cover insulating film 13. The cover insulating film 13 is also formed on the surface of the connection electrode 12 at the connection portion with the semiconductor device so that the connection electrode 12 at the connection portion with the semiconductor device is exposed and the protruding electrode that does not melt does not come into contact with the connection electrode 12. It is provided in an island shape.

【0043】図1に示す実装構造では、半導体装置21
の回路選択用端子26bの突起電極25を溶融させず、
接続用端子26aの突起電極25を溶融する温度を制御
し接続する。
In the mounting structure shown in FIG. 1, the semiconductor device 21
Without melting the protruding electrode 25 of the circuit selection terminal 26b of
The temperature at which the protruding electrode 25 of the connection terminal 26a is melted is controlled and connected.

【0044】また図2に示す実装構造では、半導体装置
21の回路選択用端子26bの突起電極25と接続用端
子26aの突起電極25と両方を溶融する温度を制御し
接続する。
In the mounting structure shown in FIG. 2, the temperature for melting both the protruding electrode 25 of the circuit selecting terminal 26b of the semiconductor device 21 and the protruding electrode 25 of the connecting terminal 26a is controlled and connected.

【0045】以上のように、半導体装置21と基板11
との接続のための熱処理温度を制御することによって、
半導体装置21に配置した回路選択用端子26bの突起
電極25と基板11に配置した接続電極12とを任意に
導通あるいは絶縁を選択することができる。
As described above, the semiconductor device 21 and the substrate 11
By controlling the heat treatment temperature for connection with
It is possible to arbitrarily select conduction or insulation between the protruding electrode 25 of the circuit selection terminal 26b arranged on the semiconductor device 21 and the connection electrode 12 arranged on the substrate 11.

【0046】つぎに、上述した実装構造の製造方法を説
明する。突起電極の形成方法は、図3に示すように、半
導体装置21の半導体素子形成領域に抵抗素子30を、
不純物拡散層やポリシリコン層によって形成する。
Next, a method of manufacturing the above-mentioned mounting structure will be described. As shown in FIG. 3, the method of forming the bump electrode is to form the resistive element 30 in the semiconductor element forming region of the semiconductor device 21,
It is formed of an impurity diffusion layer or a polysilicon layer.

【0047】半導体装置21の半導体素子形成表面に設
けたアルミニウムからなる接続電極パッド22を含む全
面に保護膜23を形成する。この保護膜23は一般的に
リンを含有したシリコン酸化膜や、窒化シリコン膜など
の無機質膜や、ポリイミド樹脂などの有機質膜や、これ
らの積層構造を用い、形成する膜厚は1〜5μmであ
る。
A protective film 23 is formed on the entire surface of the semiconductor device 21 including the connection electrode pads 22 made of aluminum provided on the semiconductor element formation surface. The protective film 23 is generally formed of a silicon oxide film containing phosphorus, an inorganic film such as a silicon nitride film, an organic film such as a polyimide resin, or a laminated structure of these, and the film thickness to be formed is 1 to 5 μm. is there.

【0048】その後、所定のマスクを用いて露光現像処
理を行なうフォトソリグラフィーとエッチングにより接
続電極パッド22が露出するように保護膜23を開口す
る。
After that, the protective film 23 is opened so that the connection electrode pads 22 are exposed by photolithography and etching in which exposure and development processing is performed using a predetermined mask.

【0049】さらに半導体装置21の全面にアルミニウ
ム、クロム、銅、ニッケル、チタンなどの金属多層膜を
共通電極膜24として、それぞれ0.1〜10μmの厚
さでスパッタリング法や真空蒸着法などの方法で形成す
る。
Further, a metal multilayer film of aluminum, chromium, copper, nickel, titanium or the like is used as the common electrode film 24 on the entire surface of the semiconductor device 21 with a thickness of 0.1 to 10 μm, such as a sputtering method or a vacuum deposition method. To form.

【0050】さらに感光性樹脂からなるメッキレジスト
を厚さ1〜10μm塗布し、フォトリソグラフィーによ
り接続用端子26aの接続電極パッド22上に開口部を
設ける。その後、鉛とスズからなるハンダからなるから
なる突起電極25をメッキ法にて形成する。
Further, a plating resist made of a photosensitive resin is applied to a thickness of 1 to 10 μm, and an opening is provided on the connection electrode pad 22 of the connection terminal 26a by photolithography. After that, the protruding electrode 25 made of solder made of lead and tin is formed by the plating method.

【0051】接続用端子26aの突起電極25は、ス
ズ:鉛=62:38の組成で形成し、融点は約183℃
である。形成する膜厚は、約50〜100μmである。
The protruding electrode 25 of the connection terminal 26a is formed of a composition of tin: lead = 62: 38 and has a melting point of about 183 ° C.
Is. The formed film thickness is about 50 to 100 μm.

【0052】その後不用になったメッキレジストを除去
する。またハンダの形成をメッキ法ではなく、メタルマ
スクを用いた真空蒸着法でも可能である。
After that, the unnecessary plating resist is removed. Further, the solder can be formed not by the plating method but by the vacuum deposition method using a metal mask.

【0053】つぎにメタルマスクを使用して回路選択用
端子26bの接続電極パッド22上に鉛とスズからなる
ハンダからなるからなる突起電極25を真空蒸着法によ
り形成する。
Next, using a metal mask, a protruding electrode 25 made of solder made of lead and tin is formed on the connection electrode pad 22 of the circuit selection terminal 26b by a vacuum evaporation method.

【0054】この回路選択用端子26bの突起電極25
は、スズ:鉛=5:95の組成で形成し、融点は約30
0〜315℃である。形成する膜厚は、接続用端子26
aと同じ膜厚である。
The protruding electrode 25 of this circuit selecting terminal 26b
Is composed of tin: lead = 5: 95 and has a melting point of about 30.
It is 0-315 degreeC. The film thickness to be formed is the connection terminal 26.
It has the same film thickness as a.

【0055】またさらに回路選択用端子26bの突起電
極25の別の形成方法としては、再度メッキレジストを
塗布しフォトリソグラフィーにより接続電極パッド22
上に開口部を設け、共通電極膜24を電極としてメッキ
法によりハンダからなる突起電極25を形成することも
可能である。
Further, as another method of forming the protruding electrode 25 of the circuit selecting terminal 26b, a plating resist is applied again and the connection electrode pad 22 is formed by photolithography.
It is also possible to form an opening on the top and use the common electrode film 24 as an electrode to form the protruding electrode 25 made of solder by a plating method.

【0056】さらにフラックスを塗布し熱処理を行い突
起電極25を半円球状にする丸め処理を行ない、その後
突起電極25をエッチングのマスクとして共通電極膜2
4を除去し、半導体装置21が完成する。
Further, flux is applied and heat treatment is performed to round the protruding electrodes 25 into a semi-spherical shape, after which the common electrode film 2 is formed using the protruding electrodes 25 as an etching mask.
4 is removed, and the semiconductor device 21 is completed.

【0057】基板11の製造方法を説明する。図1に示
すように、基板11は紙フェノールや紙エポキシなどの
有機質材料やアルミナセラミックや結晶化ガラスなどの
無機質材料、またはガラスエポキシなどの有機質無機質
材料からなる。
A method of manufacturing the substrate 11 will be described. As shown in FIG. 1, the substrate 11 is made of an organic material such as paper phenol or paper epoxy, an inorganic material such as alumina ceramic or crystallized glass, or an organic inorganic material such as glass epoxy.

【0058】この基板11の表面全面に、銅、銀、金な
どの金属をメッキ法、圧延法、真空蒸着法、スパッタリ
ング法などなどで10〜100μmの厚さで接続電極1
2を形成する。この接続電極12を感光性樹脂からなる
レジストを用いて、フォトリソグラフィーとエッチング
で配線のパターンを形成する。その後、不要になったレ
ジストを除去する。
A metal such as copper, silver, or gold is plated on the entire surface of the substrate 11 by a plating method, a rolling method, a vacuum deposition method, a sputtering method, or the like to have a thickness of 10 to 100 μm.
Form 2. A wiring pattern is formed on the connection electrode 12 by photolithography and etching using a resist made of a photosensitive resin. After that, the resist that is no longer needed is removed.

【0059】また、この基板11の表面に感光性樹脂か
らなるメッキレジストをフォトリソグラフィーでパター
ン化して銅、銀、金などの金属を無電解メッキ法で形成
し、不用になったメッキレジストを除去しても接続電極
12が形成できる。
A plating resist made of a photosensitive resin is patterned on the surface of the substrate 11 by photolithography to form a metal such as copper, silver or gold by an electroless plating method, and the unnecessary plating resist is removed. However, the connection electrode 12 can be formed.

【0060】つぎに図4に示すように、基板11および
基板11に形成した配線電極12の表面にカバー絶縁膜
13を、半導体装置21との接続部分の接続電極12が
開口露出し、かつ溶融させない突起電極25が接続電極
12と接触しないように、半導体装置21との接続部分
の接続電極12の表面にも島状にスクリーン印刷を用い
て形成する。
Next, as shown in FIG. 4, the cover insulating film 13 is formed on the surface of the substrate 11 and the wiring electrodes 12 formed on the substrate 11, and the connection electrode 12 at the connection portion with the semiconductor device 21 is exposed and melted. In order to prevent the protruding electrode 25 which is not allowed to contact the connection electrode 12, an island shape is formed by screen printing on the surface of the connection electrode 12 at the connection portion with the semiconductor device 21.

【0061】カバー絶縁膜13は、島状以外に十字状や
襷掛け状にパターンを形成しても良い。
The cover insulating film 13 may be patterned in a cross shape or a trapezoidal shape other than the island shape.

【0062】ガバー絶縁膜13は、エポキシアクリル酸
エステル樹脂、エポキシアクリレート樹脂、エポキシ樹
脂などのソルダーレジストを用いる。形成する膜厚は、
突起電極25の高さによって異なるが10〜40μmで
ある。
For the cover insulating film 13, a solder resist such as epoxy acrylate resin, epoxy acrylate resin, epoxy resin is used. The film thickness to be formed is
Although it depends on the height of the protruding electrode 25, it is 10 to 40 μm.

【0063】また、感光性ドライフィルムレジストを用
いてフォトリソグラフィーでパターン化することも可能
である。
It is also possible to pattern by photolithography using a photosensitive dry film resist.

【0064】図1に示すように、突起電極25を形成し
た半導体装置21を接続電極12を配置した基板11と
位置合わせを行なった後熱処理し、半導体装置21のハ
ンダからなる突起電極25を溶融させ接続する。
As shown in FIG. 1, the semiconductor device 21 on which the protruding electrodes 25 are formed is aligned with the substrate 11 on which the connection electrodes 12 are arranged and then heat-treated to melt the protruding electrodes 25 made of solder of the semiconductor device 21. And connect.

【0065】図1に示す実装構造では、半導体装置21
の回路選択用端子26bの突起電極25を溶融させず、
接続用端子26aの突起電極25を溶融する温度、18
3〜299℃で熱処理し接続する。
In the mounting structure shown in FIG. 1, the semiconductor device 21
Without melting the protruding electrode 25 of the circuit selection terminal 26b of
The temperature at which the protruding electrode 25 of the connection terminal 26a is melted, 18
Heat treatment is performed at 3 to 299 ° C. to connect.

【0066】また図2に示す実装構造は、半導体装置2
1の回路選択用端子26bの突起電極25と接続用端子
26aの突起電極25と両方を溶融する温度、315℃
以上で熱処理し接続する。
Further, the mounting structure shown in FIG.
The temperature at which both the protruding electrode 25 of the first circuit selecting terminal 26b and the protruding electrode 25 of the connecting terminal 26a are melted, 315 ° C.
The above is heat-treated and connected.

【0067】その後、基板11と半導体装置21のすき
間に、エポキシ系などの有機質材料からなる封止樹脂2
7を流し込み、80〜150℃で熱処理を行い封止樹脂
を硬化させ、図1、図2に示す構造になる。
After that, the sealing resin 2 made of an organic material such as epoxy is provided in the gap between the substrate 11 and the semiconductor device 21.
7, and heat treatment is performed at 80 to 150 ° C. to cure the sealing resin, and the structure shown in FIGS. 1 and 2 is obtained.

【0068】図1に示すように、回路選択用端子26b
の突起電極25を溶融させない温度で基板11と半導体
装置21を接続すると、基板11に配置した接続電極1
2の間の抵抗は半導体装置21に形成した抵抗素子30
になる。
As shown in FIG. 1, the circuit selection terminal 26b.
When the substrate 11 and the semiconductor device 21 are connected at a temperature at which the protruding electrode 25 of FIG.
The resistance between the two is the resistance element 30 formed in the semiconductor device 21.
become.

【0069】図2に示すように、回路選択用端子26b
の突起電極25を溶融する温度で基板11と半導体装置
21を接続すると、基板11に配置した接続電極12の
間の抵抗は半導体装置21に形成した抵抗素子30の2
分の1になる。
As shown in FIG. 2, the circuit selection terminal 26b.
When the substrate 11 and the semiconductor device 21 are connected at a temperature at which the protruding electrode 25 of FIG. 1 is melted, the resistance between the connection electrodes 12 arranged on the substrate 11 is 2
It becomes one-third.

【0070】このように、半導体装置21と基板11と
の接続するための熱処理の温度を選ぶことによって、任
意の抵抗値を有する回路を実装時に選択することが可能
である。
As described above, by selecting the temperature of the heat treatment for connecting the semiconductor device 21 and the substrate 11, it is possible to select a circuit having an arbitrary resistance value at the time of mounting.

【0071】半導体装置21に形成する接続用端子26
aの突起電極25のハンダ組成(スズ:鉛=62:3
8)と回路選択用端子26bの突起電極25のハンダ組
成(スズ:鉛=5:95)は一例であり、回路選択用端
子26bの突起電極25は、接続用端子26aの突起電
極25より融点の高いハンダを用いる条件を満たせば、
どの組成のハンダを用いても問題はない。
Connection terminals 26 formed on the semiconductor device 21
Solder composition of the protruding electrode 25 of a (tin: lead = 62: 3)
8) and the solder composition (tin: lead = 5: 95) of the protruding electrode 25 of the circuit selecting terminal 26b are examples, and the protruding electrode 25 of the circuit selecting terminal 26b has a higher melting point than the protruding electrode 25 of the connecting terminal 26a. If the condition to use high quality solder is satisfied,
There is no problem in using any composition of solder.

【0072】また、スズと鉛にインジウム、カドミウ
ム、ビスマス、アンチモン、銀、金などの材料を加えた
低融点あるいは高融点のハンダを用いることも可能であ
る。
It is also possible to use solder having a low melting point or a high melting point in which materials such as indium, cadmium, bismuth, antimony, silver and gold are added to tin and lead.

【0073】本発明の実施例では、半導体装置21に作
り込んだ抵抗素子30の中央に回路選択用端子26bを
一端子形成したが、複数の端子を融点の高低順に形成
し、数段階に抵抗値を変化させることも可能である。
In the embodiment of the present invention, one terminal for circuit selection 26b is formed in the center of the resistance element 30 built into the semiconductor device 21, but a plurality of terminals are formed in the order of melting point and resistance is increased in several steps. It is possible to change the value.

【0074】また、抵抗素子以外にも容量素子などにも
対応できる。インバータ回路を半導体装置21に作り込
めば、信号を反転させたり、遅延回路を追加することが
可能である。
Further, in addition to the resistance element, a capacitance element or the like can be applied. If an inverter circuit is built in the semiconductor device 21, it is possible to invert a signal or add a delay circuit.

【0075】[0075]

【発明の効果】以上の説明で明らかなように、本発明に
よる半導体装置の実装構造では、半導体装置の接続用端
子のハンダからなる突起電極と、半導体装置の回路選択
用端子の半導体装置の接続用端子の突起電極より融点の
高いハンダからなる突起電極とを有することを特徴とし
ている。その結果、回路選択性のあるベアチップ実装を
世間一般で普及しているフリップチップ実装法で実現し
ている。また、半導体装置と基板との接続するための熱
処理の温度で制御するため、ハンダの溶融の再現性が良
く、非常に量産性のある実装である。
As is apparent from the above description, in the mounting structure of the semiconductor device according to the present invention, the protruding electrode made of solder of the connecting terminal of the semiconductor device and the semiconductor device of the circuit selecting terminal of the semiconductor device are connected. And a protruding electrode made of solder having a melting point higher than that of the protruding electrode of the working terminal. As a result, bare chip mounting with circuit selectivity is realized by the flip chip mounting method that is popular in the world. Further, since the temperature is controlled by the heat treatment for connecting the semiconductor device and the substrate, the reproducibility of the melting of the solder is good and the mounting is very mass producible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における半導体装置の実装構造
を示す断面図である。
FIG. 1 is a sectional view showing a mounting structure of a semiconductor device according to an embodiment of the invention.

【図2】本発明の実施例における半導体装置の実装構造
を示す断面図である。
FIG. 2 is a cross-sectional view showing a mounting structure of a semiconductor device in an example of the present invention.

【図3】本発明の実施例における半導体装置に用いる半
導体装置の突起電極構造を示す断面図である。
FIG. 3 is a cross-sectional view showing a protruding electrode structure of a semiconductor device used for the semiconductor device in the example of the present invention.

【図4】本発明の実施例における半導体装置に用いる基
板を示す平面図である。
FIG. 4 is a plan view showing a substrate used for a semiconductor device in an example of the present invention.

【図5】従来例を説明するための半導体装置の実装構造
を示す断面図である。
FIG. 5 is a cross-sectional view showing a mounting structure of a semiconductor device for explaining a conventional example.

【図6】従来例を説明するための半導体装置の実装構造
を示す断面図である。
FIG. 6 is a cross-sectional view showing a mounting structure of a semiconductor device for explaining a conventional example.

【図7】従来例を説明するための半導体装置と基板とを
押圧するための治具を示す断面図である。
FIG. 7 is a cross-sectional view showing a jig for pressing a semiconductor device and a substrate for explaining a conventional example.

【符号の説明】[Explanation of symbols]

11 基板 12 接続電極 13 カバー絶縁膜 21 半導体装置 25 突起電極 11 substrate 12 connection electrode 13 cover insulating film 21 semiconductor device 25 protruding electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置の接続用端子の接続電極パッ
ド上のハンダからなる突起電極と、半導体装置の回路選
択用端子の接続電極パッド上の半導体装置の接続用端子
の接続電極パッド上のハンダからなる突起電極より融点
の高いハンダからなる突起電極とを有することを特徴と
する半導体装置。
1. A projecting electrode made of solder on a connection electrode pad of a connection terminal of a semiconductor device and a solder on a connection electrode pad of a connection terminal of a semiconductor device on a connection electrode pad of a circuit selection terminal of a semiconductor device. And a bump electrode made of solder having a melting point higher than that of the bump electrode made of.
JP6051660A 1994-03-23 1994-03-23 Semiconductor device Pending JPH07263451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6051660A JPH07263451A (en) 1994-03-23 1994-03-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6051660A JPH07263451A (en) 1994-03-23 1994-03-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07263451A true JPH07263451A (en) 1995-10-13

Family

ID=12893040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6051660A Pending JPH07263451A (en) 1994-03-23 1994-03-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07263451A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002063681A1 (en) * 2001-02-08 2002-08-15 Hitachi, Ltd. Semiconductor integrated circuit device and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002063681A1 (en) * 2001-02-08 2002-08-15 Hitachi, Ltd. Semiconductor integrated circuit device and its manufacturing method
US6867123B2 (en) 2001-02-08 2005-03-15 Renesas Technology Corp. Semiconductor integrated circuit device and its manufacturing method

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