JPH0724821Y2 - 高速マルチプレクス回路 - Google Patents
高速マルチプレクス回路Info
- Publication number
- JPH0724821Y2 JPH0724821Y2 JP78987U JP78987U JPH0724821Y2 JP H0724821 Y2 JPH0724821 Y2 JP H0724821Y2 JP 78987 U JP78987 U JP 78987U JP 78987 U JP78987 U JP 78987U JP H0724821 Y2 JPH0724821 Y2 JP H0724821Y2
- Authority
- JP
- Japan
- Prior art keywords
- line
- signal
- data
- gate
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Time-Division Multiplex Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP78987U JPH0724821Y2 (ja) | 1987-01-07 | 1987-01-07 | 高速マルチプレクス回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP78987U JPH0724821Y2 (ja) | 1987-01-07 | 1987-01-07 | 高速マルチプレクス回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63111032U JPS63111032U (enrdf_load_stackoverflow) | 1988-07-16 |
JPH0724821Y2 true JPH0724821Y2 (ja) | 1995-06-05 |
Family
ID=30778087
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP78987U Expired - Lifetime JPH0724821Y2 (ja) | 1987-01-07 | 1987-01-07 | 高速マルチプレクス回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0724821Y2 (enrdf_load_stackoverflow) |
-
1987
- 1987-01-07 JP JP78987U patent/JPH0724821Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63111032U (enrdf_load_stackoverflow) | 1988-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0759664A3 (en) | Multiplexer and demultiplexer | |
AU6365500A (en) | Method and apparatus for adjusting control signal timing in a memory device | |
GB1452077A (en) | Logic circuit digital tachometer counter | |
EP0404127B1 (en) | Signal generator | |
US4337433A (en) | Clock signal distributing circuit adjusting device and method | |
KR880009382A (ko) | 반도체 집적회로장치 | |
EP0235303A4 (en) | System for adjusting clock phase. | |
JPH0724821Y2 (ja) | 高速マルチプレクス回路 | |
EP0111262A3 (en) | Output multiplexer having one gate delay | |
US6456137B1 (en) | Semiconductor circuit, delay adjustment method therefor and layout method therefor | |
DE69922161D1 (de) | Leitungstreiber mit linearen übergängen | |
JP2930174B2 (ja) | 半導体集積回路装置 | |
US4918331A (en) | Logic circuits with data resynchronization | |
KR19990057223A (ko) | 입력 버퍼들을 구비한 반도체 장치 | |
GB1236535A (en) | Gate circuit for electronic musical instruments | |
KR100249019B1 (ko) | 주파수 분주회로 | |
EP1096680A3 (en) | A pulse width modulation circuit | |
SU1238256A2 (ru) | Устройство дл формировани биимпульсного сигнала | |
JPS63136713A (ja) | 遅延回路 | |
JPS6491182A (en) | Transfer circuit | |
KR0184153B1 (ko) | 주파수 분주 회로 | |
SU1185637A1 (ru) | Устройство дл передачи дискретной информации | |
CA2066567A1 (en) | Circuit arrangement with at least one input and one output for transmitting a signal which can be filtered, parallelized and digitized | |
JPH0691432B2 (ja) | フリツプフロツプ回路 | |
KR960003372Y1 (ko) | 디지탈 신호지연장치 |