CA2066567A1 - Circuit arrangement with at least one input and one output for transmitting a signal which can be filtered, parallelized and digitized - Google Patents

Circuit arrangement with at least one input and one output for transmitting a signal which can be filtered, parallelized and digitized

Info

Publication number
CA2066567A1
CA2066567A1 CA2066567A CA2066567A CA2066567A1 CA 2066567 A1 CA2066567 A1 CA 2066567A1 CA 2066567 A CA2066567 A CA 2066567A CA 2066567 A CA2066567 A CA 2066567A CA 2066567 A1 CA2066567 A1 CA 2066567A1
Authority
CA
Canada
Prior art keywords
circuit arrangement
signal
parallelized
digitized
filtered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2066567A
Other languages
French (fr)
Other versions
CA2066567C (en
Inventor
Gisbert Lawitzky
Wolf-Dietrich Moller
Franz-Josef Schmitt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Gisbert Lawitzky
Wolf-Dietrich Moller
Franz-Josef Schmitt
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gisbert Lawitzky, Wolf-Dietrich Moller, Franz-Josef Schmitt, Siemens Aktiengesellschaft filed Critical Gisbert Lawitzky
Publication of CA2066567A1 publication Critical patent/CA2066567A1/en
Application granted granted Critical
Publication of CA2066567C publication Critical patent/CA2066567C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • H04L49/1523—Parallel switch fabric planes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Networks Using Active Elements (AREA)

Abstract

A circuit arrangement, preferably for a coupling network component of a network node in a packet-switching data network, is disclosed which has a wide parallelization of the data packet signal by means of shift registers, so that it is possible to operate internally with a greatly reduced operating speed. In particular, an arrangement of the components on a single semiconductor wafer permits an especially wide bus, which can be constructed extremely advantageously with a surface-optimized floor plan.
CA002066567A 1989-09-25 1990-02-09 Circuit arrangement with at least one input and one output for transmitting a signal which can be filtered, parallelized and digitized Expired - Fee Related CA2066567C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3931977A DE3931977A1 (en) 1989-09-25 1989-09-25 CIRCUIT ARRANGEMENT WITH AT LEAST ONE INPUT AND AT LEAST ONE OUTPUT FOR PROVIDING A PARALLELIZABLE DIGITALIZABLE INPUT SIGNAL
DEP3931977.6 1989-09-25

Publications (2)

Publication Number Publication Date
CA2066567A1 true CA2066567A1 (en) 1991-03-26
CA2066567C CA2066567C (en) 1999-02-02

Family

ID=6390149

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002066567A Expired - Fee Related CA2066567C (en) 1989-09-25 1990-02-09 Circuit arrangement with at least one input and one output for transmitting a signal which can be filtered, parallelized and digitized

Country Status (5)

Country Link
EP (1) EP0493381B1 (en)
AT (1) ATE114923T1 (en)
CA (1) CA2066567C (en)
DE (2) DE3931977A1 (en)
WO (1) WO1991004641A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4130318A1 (en) * 1991-09-12 1993-03-18 Standard Elektrik Lorenz Ag Information transmission procedure in coupling network - distributing successive information elements among parallel identical transmission lines.
DE10217313B4 (en) * 2002-04-18 2007-11-29 Infineon Technologies Ag Digital signal processor and method for data processing with a digital signal processor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2339299A1 (en) * 1976-01-20 1977-08-19 Jeumont Schneider CONNECTION NETWORK FOR TEMPORAL TELEPHONE PABX SWITCH WITH CODE PULSE MODULATION
US4661947A (en) * 1984-09-26 1987-04-28 American Telephone And Telegraph Company At&T Bell Laboratories Self-routing packet switching network with intrastage packet communication
US4760570A (en) * 1986-08-06 1988-07-26 American Telephone & Telegraph Company, At&T Bell Laboratories N-by-N "knockout" switch for a high-performance packet switching system
US4935921A (en) * 1986-09-30 1990-06-19 Nec Corporation Cross-connection network using time switch
DE3881813D1 (en) * 1987-09-30 1993-07-22 Siemens Ag SORTING UNIT FOR A SWITCHING NODE WITH A VARIETY OF DIGITAL COUPLERS FOR FAST, ASYNCHRONOUS DATA PACKET SWITCHING NETWORKS.

Also Published As

Publication number Publication date
EP0493381B1 (en) 1994-11-30
EP0493381A1 (en) 1992-07-08
DE59007882D1 (en) 1995-01-12
ATE114923T1 (en) 1994-12-15
WO1991004641A1 (en) 1991-04-04
CA2066567C (en) 1999-02-02
DE3931977A1 (en) 1991-04-04

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Legal Events

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MKLA Lapsed