JPS6491182A - Transfer circuit - Google Patents

Abstract

PURPOSE: To prevent the reduction of a maximum transfer clock frequency by connecting a transfer clock signal to the operation clock terminal of a first FF through a delay circuit and connecting the transfer clock signal to the operation clock terminal of an FF, which outputs a transfer signal, without passing any delay circuit. CONSTITUTION: A plurality of drivers 11 made into ICs are used and are cascaded, and the same transfer clock signal 16 is given to individual drivers 11, and the signal is transferred even between drivers 11. In this case, the operation clock signal of a first FF out of FFs 4 constituting a shift register in each driver 11 is delayed behind the transfer clock signal 16 given to the driver 11. The operation clock signal of the FF 4 which outputs transferred data to an output terminal 12 is used without being delayed behind the transfer clock signal 16 given to the driver 11. Thus, the reduction of the data transfer clock frequency in cascading plural drivers is prevented.