SU1208554A2 - Variable priority device - Google Patents

Abstract

The invention relates to computer technology and can be used in computer systems and is an improvement of the device according to USSR author's certificate No. 737954. The purpose of the invention is to increase the reliability of the device, which is achieved by introducing new blocks and connections that allow the corresponding signal to be generated in the event of a failure. . The device contains a priority storage register, divided into groups of triggers, AND elements, OR elements, NOT elements, interrupt signal interlock nodes, device inputs, device outputs, pulse drivers, OR NOT elements, OR element, delay elements, AND element, signal output . Increased reliability is achieved by introducing a group of drivers, OR-NOT, OR, AND, delay elements. 1 il. s (l

Description

The invention relates to computing and can be used in computing systems.

The aim of the invention is to increase the reliability of the device.

The drawing shows a diagram of the device.

The device contains a priority storage register 1 consisting of three groups of 7.-2 flip-flops, the first group contains three flip-flops 3 (-3, the second contains two flip-flops 4 and 4, and the third contains one flip-flop 5,, And elements 6 6 nodes 7 (- 74 blocking of pre-scan signals, elements OR 8, elements NOT 9, elements AND 10, inputs 11I - 11 devices, outputs 12 devices, pulse formers 13, elements OR NOT 14 and 15, element OR, 16, the delay elements 17 and 18, the And element 19 and the signal output 20 of the device.

The device operates as follows.

The state of the triggers of the priority storage register 1 determines the distribution of priorities between inputs 11 (- 114. The zero content of register 1 sets the priority distribution at which input I1 is assigned the highest priority and input 114 the lowest. If all triggers of register 1 are set to one state, then the distribution of priorities will change to the opposite: input 1 1 / j will be assigned the highest priority and input} the lowest one.

In register 1, you can enter an arbitrary code (the input circuit in register 1 is not shown in the diagram) determining the distribution of priorities between inputs 1 1 (- 114. Each trigger of register 1 determines the mutual priority of two inputs. If the trigger is in zero state, then the input with a lower number is assigned a higher priority, and if in one, a higher priority is assigned to the input with a higher number. The states of group 2 triggers determine the mutual priorities between input 1 C and all other inputs, no triggers groups 2 - between the input 11J, and inputs Pz, 1 Ts, and the state of the trigger 5, (groups 2,) - between the input 1 Ts and input 11. Next208554

Indeed, an arbitrary code is written to register 1 for storing priorities; all possible combinations of priorities can be set between

5 entrances.

Stop signals that are received at one or at the same time at several inputs 1C 114 are sent to the corresponding elements And 10 nodes

10 7, 74, preparing them to work. In addition, a signal appears at the output of the element OR 16. Formers 13 (- 13 pulses give out pulses at their outputs only

15 on the falling edge of the pulses at the inputs, i.e. after removing the signal of the served request, therefore, at the output of the element OR 15, there is a single signal. The signal is also present at the output of the OR-NOT 4 element. After receiving requests for device inputs, an AND 10 element of only that node 7, -7 is triggered, in which all the elements of AND 6-6 are closed with a zero signal removed from one of the triggers. register 1, or a zero signal from one of the inputs 11, - 114. Thus, the most priority input from

30 of all inputs on which there are signals requests. In all other nodes, the blocking signals of the breaking signal necessarily trigger one or several elements.

35 And 6, -65, and the signal from its output

through the elements OR B and NOT 9 (zeros) enter the input of the corresponding element AND 10 and close it, thus not giving the signal

40 of the request for interrogation arriving at its input appears at output 12, - 12 of the device. The signal that passes through one of the elements And 10, is fed to the corresponding output

45 12. The same signal leads to the removal of the signal from the output of the element OR NOT 14. After this, a signal appears at the output of the element 17 of the delay. This signal through the element And 19 does not pass, which indicates the correct operation of the device. If there are signals at the inputs And - 11 and no signal at all outputs 12, a signal appears at the output of the element And 19, which passes to the output 20 of the device, indicating a failure / blocking /. In this case, you need to check and fix

50

the contents of register 1 storage priorities. Element 17 provides a delay for the duration of transients in nodes 7-1, since the signal at the output of the device appears after the arrival of signals at its inputs, which without element 17 can lead to spurious detection of the signal at output 20 of the device. After servicing the next request, the signal of this request is removed from the corresponding input 1 I. If there are other requests, then the output of the delay element 17 is still a signal. The signal at the corresponding output 12 is also removed, and at the other output 12, the signal of the next request appears after some time. This leads to the appearance of a pulse at the output of the OR-NOT 14 element. When the signal from one of the 114 - 1l inputs is removed, the shaper 13 corresponding to this input pulses the pedal to the removal of the signal from the output of the OR-NOT 15 element. there is a blocking of the srabatania element And 19 just at the time when a pulse occurs at the output of the 0808A

ment or NOT 14, which prevents the false signal at the output 20 of the device,

Claims (1)

5 claims The device of variable priority on av.ev, No. 737954, characterized in that, with the aim 10 increase the reliability, it contains a group of pulse shapers, two elements SHS-NOT, element OR, two delay elements and element AND, each input of the device soy) 5 is connected to the input of the same shaper of pulses and with the same input of HJM element, the output of which is connected to the input of the first delay element, the output of which is connected to the first input of the element I, the second input of which is connected to the output of the first element OR NOT, whose inputs are connected to the outputs of the device, the outputs of the pulse drivers 25 owls connected to the inputs of the second element OR NOT, the output of which is connected to the input of the second delay element, the output of which is connected to the third input of the element AND whose output 30 is the signal output of the device.  ; f / 2 h fif sewn Order 289/58 T 20 Circulation 673 Fshshvl ShSh Patent, Uzhgorod, Projecto st., 4 Subscription