SU1269132A1 - Two-input priority device - Google Patents

Abstract

The invention is intended for use in computing systems in organizing the access of two processors to a common resource. The aim of the invention is to improve the reliability of the operation. The device contains two elements SHS-NOT, a delay element, an element NOT, a Schmidt trigger and two controllable delay blocks. The use of the latter allows to ensure stable operation of the device when resolving conflict situations, regardless of the parameters of the elements used. 2 Il. cl

Description

The invention relates to computer technology and can be used to control access to the shared resource of two active devices of a computing system, such as processors.

The purpose of the invention is to increase the reliability of the operation of the device.

In FIG. 1 shows a functional diagram of the device; in FIG. 2 circuit block controlled delay.

The device contains elements ORINE 1 and 2, a threshold element (Schmidt trigger) 3, element NOT 4, blocks 5 · and 6 controlled delay, delay element 7, inputs 8 and 9, outputs 10 and 11. Blocks 5 and 6 contain elements And 12 , information input 13, control input 14, output 15.

The device operates as follows.

Request signals are received at inputs 8 and 9 of the device in the form of logical levels 1. Logical 1 input to input 8 leads to the appearance of the output element NOT 4 logical 0, which is fed to the inputs of the delay element 7 and the element OR NOT 1. The output of the latter is formed logical signal 1, causing the triggering of the threshold element 3, at the inverting output of which a signal is generated with a logic level of 0, then converted using the OR-NOT 2 element to a single value of the request signal at the output 10 of the device. Simultaneously with the output of the threshold element 3, a zero signal is supplied to the control inputs of the controlled delay units 5 and 6, which leads to a prohibition of the passage of the request signal c through them. input 9 of the device to output 11 <>

When the request signal arrives only at the input 9 of the device, it passes through blocks 5 and 6 of the controlled delay to output 11, since a logical unit is supplied to their control inputs from the output of the threshold element 3. At the same time, from the output of the controlled delay unit 5, a signal with a level of 1 ″ is fed to the input of the OR-NOT 2 element, prohibiting the passage of the request signal from input 8 of the device to output 10.

Consider the competition mode that occurs when the interval between requests for inputs 8 and 9 is commensurate with the response time of the elements. In this case, a situation is possible where the signals at the inputs 5 of the OR-NOT 1 element almost simultaneously change to the opposite, as a result of which a short pulse is generated at its output with a logic level 1 or with a level not 10 reaching full level 1. If this pulse does not trigger threshold element 3, the output of the OR-NOT 1 element remains in state 0, the request signal from input 15 9 passes through block 6 to the output

11, and the passage of the signal from input to output 10 is blocked by level 1 coming to the element OR NOT 1 from the output of unit 5 „

In the event that the pulse at the output of the OR-NOT 1 element causes the appearance of a pulse at the output of the threshold element 3, blocks 5 and 6 are reset before the signal 25 has arrived at output 11, Block 5 removes the unit level from the input of the element OR NOT 1, at the output of which a single signal is formed, causing the appearance of a signal at the output 10 of the device. The passage of the signal from input to output 11 is blocked by the zero level acting from the output of the threshold element 3.

For reliable operation of the device, the delay value of blocks 5 and 6 and element 7 must be at least the maximum total response time of the OR-NOT 1 element and threshold element 3.

An example of the implementation of blocks 5 and 6 of the controlled delay in the form of a chain of elements AND is shown in FIG. 2. The signal from the data input 13 to output 15 passes through the total voe45 mja AND operation of all elements 12 with a signal at the control input 14. If during the signal at the control input signal is zero 14, the circulation signal pro.- ₅₀ through elements And 12 stops.

Claims (2)

The invention relates to computing and can be used to control access to the total resource of two active computing system devices, such as processors. The purpose of the invention is to increase the reliability of the operation of the device. FIG. 1 shows a functional diagram of the device; in fig. 2 shows a controllable delay block. The device contains the elements ORINE 1 and 2, the threshold element (Schmidt trigger) 3, the element 4, the blocks 5 and 6 of the controlled delay, the element 7 delay, inputs 8 and 9, the outputs 10 and 11. The blocks 5 and 6 contain elements AND 12, information input, 13, control input 14, output 15. The device operates as follows. The request signals are sent to the inputs 8 and 9 of the device in the form of logical levels 1. The arrival of logical 1 to input 8 results in the output of the NOT element 4 of the logical O, which arrives at the inputs of the delay element 7 and the W-NOT element 1. At the output of the last a signal of logical 1 is generated, which triggers the triggering of the threshold element 3, on the inverting input of which a signal is generated with a logic level O, further converted by the IZHEHONE element 2 into the unit value of the signal at the output 10 of the device. At the same time, from the output of the threshold element 3, the zero signal goes to the control inputs of blocks 5 and 6 of the controlled station, which leads to the interdiction of the request signal from input 9 of device 11 to output 11. When a request signal arrives only at the input 9 of the device, it passes through blocks 5 and 6 of the control of my delay to output 11, since a logical unit arrives at their control inputs from the output of threshold element 3. Simultaneously from the output of the controllable delay unit 5, a signal with a level 1 is input to the I1B1-HE2 element, prohibiting the request signal from the input 8 of the device to the output 10. Consider the competition mode that occurs when the interval between the arrival of requests and inputs 8 and 9 commensurate with the response time of the elements. In this case, a situation is possible when the signals at the inputs of the element OR-NOT 1 almost simultaneously change into opposite ones, as a result of which a short pulse is formed at its output with a logic level 1 or with a level that has not reached full level 1. If this pulse is not triggers the threshold element 3, the output of the element OR NOT 1 remains in the state O, the request signal from input 9 through block 6 passes to output 11, and the passage of the signal from input 8 to output 10 is blocked by level 1 arriving at the element OR NOT 1 from the output of the block 5 "In case In other words, if a pulse at the output of the element OR-NOT 1 causes the appearance of a pulse at the output of threshold element 3, blocks 5 and 6 are reset before the signal at output 11 occurs. 1xblock 5 removes the unit level from the input of element SH- NOT 1, at the output of which a single signal is formed, causing the appearance of a signal at the output 10 of the device. The signal from input 9 to output 11 is blocked by a zero level acting from the output of threshold element 3. For reliable operation of the device, the delay of blocks 5 and 6 and element 7 must be no less than the maximum total response time of the element OR NOT 1 and threshold element 3. An example of the implementation of blocks 5 and 6 of the controlled delay in the form of a chain of elements And is shown in FIG. 2. The signal from information input 13 passes to output 15 through the summing response of all elements And 12 when there is a signal at control input 14. If during the passage of a signal at control input 14 a zero signal appears, then the pro- the signal travels through the elements AND 12 stops. The invention of the two-way device prioritize containing the first and second elements OR-NOT, the threshold element, and the output of the first element ILINE is connected to the input of the threshold element 3112691 Mf-nta, the output of which is connected to the first input of the second element ILNTNE, characterized in that, in order to verify the reliability of the operation, a delay element, an element NOT and two controllable delay units are inserted into it, the first request input of the device is connected through the element NOT with the first input of the first element OR-NOT and the input of the delay element, the output of which is connected to the second input of the second element OR-NOT, the output of which is co324 The device is connected to the information input of the first controllable delay block, the output of which is connected to the information input of the second controllable delay block and to the second input of the first P1I-NO element; the output of the second controllable delay block is the second the output of the device, the first input of the second element OR is NOT connected to the control inputs of the first and second blocks of the controlled delay.