JPH07245395A - High breakdown strength mos transistor and its manufacture - Google Patents

High breakdown strength mos transistor and its manufacture

Info

Publication number
JPH07245395A
JPH07245395A JP3402594A JP3402594A JPH07245395A JP H07245395 A JPH07245395 A JP H07245395A JP 3402594 A JP3402594 A JP 3402594A JP 3402594 A JP3402594 A JP 3402594A JP H07245395 A JPH07245395 A JP H07245395A
Authority
JP
Japan
Prior art keywords
oxide film
gate electrode
field oxide
silicon substrate
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3402594A
Other languages
Japanese (ja)
Inventor
Tadashi Nose
忠司 能勢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP3402594A priority Critical patent/JPH07245395A/en
Publication of JPH07245395A publication Critical patent/JPH07245395A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To prevent leak due to creeping of source and drain regions to below a gate electrode in an edge part of a field oxide film without increasing manhour while ensuring high breakdown strength. CONSTITUTION:In a high breakdown strength MOS transistor, a field oxide film 2 is formed on a surface of a P<->-type silicon substrate 1 by a selective oxidation method, a strip-like gate electrode 11 consisting of polysilicon, etc., is formed in a window opening part of the field oxide film 2 of the silicon substrate 1 extending over the field oxide film 2 with a gate oxide film 3 of SiO2, etc., therebetween, and high concentration N<+>-type impurities are selectively diffused by self-alignment in a surface of the silicon substrate 1 at both sides of the gate electrode 11 for forming a source region 5 and a drain region 6. A wide part 12 is therefore formed in the gate electrode 11 in an edge part (m) of the field oxide film 2 along a direction perpendicular to an extension direction of the gate electrode 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高耐圧MOSトランジス
タ及びその製造方法に関し、例えば、各種の集積回路に
使用されるNチャンネル高耐圧MOSトランジスタ及び
その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MOS transistor and a manufacturing method thereof, for example, an N channel high breakdown voltage MOS transistor used in various integrated circuits and a manufacturing method thereof.

【0002】[0002]

【従来の技術】例えば、Nチャンネル高耐圧MOSトラ
ンジスタは、具体的に以下の構造を有する。
2. Description of the Related Art For example, an N-channel high breakdown voltage MOS transistor has the following specific structure.

【0003】即ち、図3(a)(b)に示すようにP-
型シリコン基板1の表面に選択酸化法によりフィールド
酸化膜2を形成し、そのシリコン基板1のフィールド酸
化膜2の窓開け部分にSiO2 等のゲート酸化膜3を介
してポリシリコン等からなる短冊状のゲート電極4をフ
ィールド酸化膜2に跨がるように形成し、そのゲート電
極4の両側でシリコン基板1の表面に高濃度のN+ 型不
純物をゲート電極4及びフィールド酸化膜2にセルフア
ラインにより選択的に拡散してソース及びドレイン領域
5,6を形成する。尚、図中、7は隣接する他の半導体
素子と絶縁分離するためにフィールド酸化膜2の下に形
成された高濃度のP+ 型不純物からなるチャンネルスト
ッパ領域である。
[0003] That is, as shown in FIG. 3 (a) (b) P -
A field oxide film 2 is formed on the surface of a silicon substrate 1 by a selective oxidation method, and a strip made of polysilicon or the like is formed in the window opening portion of the field oxide film 2 of the silicon substrate 1 via a gate oxide film 3 such as SiO 2. -Shaped gate electrode 4 is formed so as to straddle the field oxide film 2, and high-concentration N + -type impurities are self-applied to the gate electrode 4 and the field oxide film 2 on the surface of the silicon substrate 1 on both sides of the gate electrode 4. Source and drain regions 5 and 6 are formed by selective diffusion by aligning. In the figure, 7 is a channel stopper region made of a high concentration P + -type impurity which is formed under the field oxide film 2 to insulate and separate another semiconductor element adjacent thereto.

【0004】[0004]

【発明が解決しようとする課題】ところで、上述した構
造を有する高耐圧MOSトランジスタでは、図3(a)
(b)に示すようにフィールド酸化膜2の形成により、
ゲート電極4が延びる方向と交差する方向に沿うフィー
ルド酸化膜2のエッジ部分m〔バーズピーク〕で、シリ
コン基板1中のP型不純物であるボロンが侵食されてそ
の不純物濃度が低下する。
By the way, in the high breakdown voltage MOS transistor having the above-mentioned structure, as shown in FIG.
By forming the field oxide film 2 as shown in (b),
At the edge portion m [bird's peak] of the field oxide film 2 along the direction intersecting the direction in which the gate electrode 4 extends, boron which is a P-type impurity in the silicon substrate 1 is eroded and its impurity concentration is lowered.

【0005】一方、ゲート電極4の形成後、N型不純物
をイオン注入によりフィールド酸化膜2の窓開け部分か
らシリコン基板1の表面に押し込み拡散することによ
り、ゲート電極4の両側でシリコン基板1の表面にソー
ス領域5とドレイン領域6とを形成するが、この時、図
4(a)に示すように上述したN型不純物からなるソー
ス及びドレイン領域5,6がラテラル拡散によりゲート
電極4の下に若干回り込むことは周知である。
On the other hand, after the gate electrode 4 is formed, N-type impurities are pushed into the surface of the silicon substrate 1 from the window opening portion of the field oxide film 2 by ion implantation and diffused, so that the silicon substrate 1 on both sides of the gate electrode 4 is diffused. The source region 5 and the drain region 6 are formed on the surface. At this time, as shown in FIG. 4A, the source and drain regions 5 and 6 made of the N-type impurities described above are formed below the gate electrode 4 by the lateral diffusion. It is well known that it goes around a little.

【0006】このソース及びドレイン領域5,6の回り
込み量はシリコン基板1の不純物濃度が低いほど大きく
なることから、前述したようにフィールド酸化膜2のエ
ッジ部分mでゲート電極4直下のシリコン基板1中の不
純物濃度が低いと、フィールド酸化膜2のエッジ部分m
では、図4(b)に示すようにソース領域5とドレイン
領域6のゲート電極4直下への回り込み量が大きくな
り、ソース領域5とドレイン領域6とが近接してその両
者5,6間でリークが発生する不具合があった。この問
題は、半導体装置の高集積化、高速化に伴い、ゲート電
極4の幅寸法〔ゲート長〕が小さくなればなるほど顕著
となる。
Since the amount of sneaking in of the source and drain regions 5, 6 increases as the impurity concentration of the silicon substrate 1 decreases, as described above, the silicon substrate 1 immediately below the gate electrode 4 at the edge portion m of the field oxide film 2. If the impurity concentration in the inside is low, the edge portion m of the field oxide film 2
Then, as shown in FIG. 4B, the wraparound amount of the source region 5 and the drain region 6 directly below the gate electrode 4 becomes large, and the source region 5 and the drain region 6 are close to each other, and between them 5 and 6. There was a problem that a leak occurred. This problem becomes more remarkable as the width dimension [gate length] of the gate electrode 4 becomes smaller as the semiconductor device becomes more highly integrated and faster.

【0007】この問題を解消する手段として、特開昭6
3−260178号公報に開示されるようにフィールド
酸化膜よりも内側にチャンネルストッパである高濃度層
を食み出させた構造があるが、この場合、高濃度層が高
濃度のソース及びドレイン領域と接することになり、高
耐圧を確保することが困難となる。また、特開昭62−
7148号公報に開示されるようにフィールド酸化膜の
エッジ部分に沿って高濃度層を形成し、高濃度のソース
及びドレイン領域をその高濃度層に接しないように形成
する構造もあるが、このようにすると、ソース及びドレ
イン領域をフィールド酸化膜に対しセルフアラインによ
り形成することが不可能で、ソース及びドレイン領域を
形成するための専用のマスクを必要として工数が増加す
ると共にコストアップを招来する。
As a means for solving this problem, Japanese Unexamined Patent Publication No.
As disclosed in Japanese Patent Laid-Open No. 3-260178, there is a structure in which a high-concentration layer serving as a channel stopper is exposed inside a field oxide film. In this case, the high-concentration layer has a high-concentration source and drain regions. Therefore, it becomes difficult to secure a high breakdown voltage. In addition, JP-A-62-1
As disclosed in Japanese Patent No. 7148, there is a structure in which a high-concentration layer is formed along the edge portion of a field oxide film and the high-concentration source and drain regions are formed so as not to be in contact with the high-concentration layer. By doing so, it is impossible to form the source and drain regions by self-alignment with the field oxide film, and a dedicated mask for forming the source and drain regions is required, resulting in an increase in man-hours and an increase in cost. .

【0008】そこで、本発明は上記問題点に鑑みて提案
されたもので、その目的とするところは、高耐圧を確保
しながら工数の増加を招来することなく、フィールド酸
化膜のエッジ部分でのソース及びドレイン領域のゲート
電極下への回り込みによるリークを未然に防止し得る高
耐圧MOSトランジスタ及びその製造方法を提供するこ
とにある。
Therefore, the present invention has been proposed in view of the above problems, and an object of the present invention is to secure a high withstand voltage and to increase the number of steps without increasing the man-hours. It is an object of the present invention to provide a high breakdown voltage MOS transistor and a method for manufacturing the same, which can prevent leakage due to the sneak of the source and drain regions under the gate electrode.

【0009】[0009]

【課題を解決するための手段】上述した目的を達成する
ための技術的手段として、本発明は、P型シリコン基板
の表面に素子形成領域を残す選択酸化法によりフィール
ド酸化膜を形成し、そのフィールド酸化膜の窓開け部分
にゲート酸化膜を介してゲート電極をフィールド酸化膜
に跨がるように形成し、そのゲート電極の両側で窓開け
部分に高濃度のN型不純物をゲート電極及びフィールド
酸化膜に対してセルフアラインにより選択的に拡散して
ソース及びドレイン領域を形成した高耐圧MOSトラン
ジスタにおいて、ゲート電極が延びる方向と交差する方
向に沿うフィールド酸化膜のエッジ部分で、ゲート電極
に幅広部を形成したことを特徴とする。
As a technical means for achieving the above-mentioned object, the present invention forms a field oxide film by a selective oxidation method which leaves an element formation region on the surface of a P-type silicon substrate. A gate electrode is formed in the window opening portion of the field oxide film so as to extend over the field oxide film through the gate oxide film, and a high concentration N-type impurity is added to the gate electrode and the field in the window opening portion on both sides of the gate electrode. In a high breakdown voltage MOS transistor in which source and drain regions are selectively diffused by self-alignment with respect to an oxide film, the gate electrode is widened at the edge portion of the field oxide film along the direction intersecting the direction in which the gate electrode extends. It is characterized in that a part is formed.

【0010】また、本発明方法は、P型シリコン基板の
表面に素子形成領域を残して選択酸化法によりフィール
ド酸化膜を形成する工程と、前記素子形成領域となるフ
ィールド酸化膜の窓開け部分を二つに仕切り、フィール
ド酸化膜に跨がり、フィールド酸化膜のエッジ部で幅広
部を有するゲート電極をゲート酸化膜を介して形成する
工程と、前記フィールド酸化膜及び前記ゲート電極をマ
スクにN型不純物を注入する工程と、熱処理により注入
した不純物を拡散する工程とを特徴とする。
Further, the method of the present invention comprises a step of forming a field oxide film by a selective oxidation method while leaving an element formation region on the surface of a P-type silicon substrate, and a window opening portion of the field oxide film which becomes the element formation region. A step of forming a gate electrode having a wide portion at the edge portion of the field oxide film, which is divided into two and spans the field oxide film, through the gate oxide film; and N-type using the field oxide film and the gate electrode as a mask It is characterized by a step of implanting impurities and a step of diffusing the implanted impurities by heat treatment.

【0011】[0011]

【作用】本発明に係る高耐圧MOSトランジスタでは、
ゲート電極が延びる方向と交差する方向に沿うフィール
ド酸化膜のエッジ部分で、ゲート電極に幅広部を形成し
たことにより、そのフィールド酸化膜のエッジ部分での
ソース及びドレイン領域のゲート電極下への回り込みが
生じても、ソース領域とドレイン領域との間隔を十分に
確保することができる。
In the high voltage MOS transistor according to the present invention,
By forming the wide part in the gate electrode at the edge part of the field oxide film along the direction crossing the direction in which the gate electrode extends, the wraparound of the source and drain regions under the gate electrode at the edge part of the field oxide film Even if this occurs, a sufficient space can be secured between the source region and the drain region.

【0012】[0012]

【実施例】本発明に係る高耐圧MOSトランジスタの実
施例を図1及び図2に示して説明する。尚、図3及び図
4と同一部分には同一参照符号を付す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a high breakdown voltage MOS transistor according to the present invention will be described with reference to FIGS. The same parts as those in FIGS. 3 and 4 are designated by the same reference numerals.

【0013】例えば、Nチャンネル高耐圧MOSトラン
ジスタは、従来と同様、図1(a)に示すようにP-
シリコン基板1の表面にSiO2 等からなるフィールド
酸化膜2を選択酸化法により形成し、そのシリコン基板
1のフィールド酸化膜2の窓開け部分にSiO2 等のゲ
ート酸化膜3を介してポリシリコン等からなる短冊状の
ゲート電極11をフィールド酸化膜2に跨がるように形
成し、そのゲート電極11の両側でシリコン基板1の表
面に高濃度のN+ 型不純物をゲート電極11及びフィー
ルド酸化膜2に対しセルフアラインにより選択的に拡散
してソース領域5及びドレイン領域6を形成するが、本
発明の高耐圧MOSトランジスタは、以下の点で従来と
相違する。
For example, in the N-channel high breakdown voltage MOS transistor, as in the conventional case, as shown in FIG. 1A, a field oxide film 2 made of SiO 2 or the like is formed on the surface of a P type silicon substrate 1 by a selective oxidation method. Then, a strip-shaped gate electrode 11 made of polysilicon or the like is formed in the window opening portion of the field oxide film 2 of the silicon substrate 1 via a gate oxide film 3 such as SiO 2 so as to straddle the field oxide film 2. Then, a high concentration N + -type impurity is selectively diffused on the surface of the silicon substrate 1 on both sides of the gate electrode 11 by self-alignment with respect to the gate electrode 11 and the field oxide film 2 to form the source region 5 and the drain region 6. Although formed, the high breakdown voltage MOS transistor of the present invention is different from the conventional one in the following points.

【0014】本発明の特徴はゲート電極11の形状にあ
る。即ち、ゲート電極11の中央部分よりもその両端部
分を幅広にする。特に、ゲート電極11が延びる方向と
交差する方向に沿うフィールド酸化膜2とエッジ部分m
で、ゲート電極11に幅広部12を設ける。尚、上述し
たゲート電極11の形状は、図1(a)に示すもの以外
にも、例えば、図2(a)に示すようにゲート電極1
1’の中央部分から両端部分に向けてテーパ状に幅広と
した形状や、同図(b)に示すようにゲート電極11''
の両側に食み出す形状ではなく、一方の側のみに食み出
す形状とすることも可能である。
The feature of the present invention lies in the shape of the gate electrode 11. That is, both end portions of the gate electrode 11 are made wider than the central portion. In particular, the field oxide film 2 and the edge portion m along the direction intersecting the direction in which the gate electrode 11 extends
Then, the wide portion 12 is provided on the gate electrode 11. The shape of the gate electrode 11 described above is not limited to that shown in FIG. 1A, and for example, as shown in FIG.
The taper shape is widened from the central portion of 1'to both end portions, or as shown in FIG.
It is also possible to have a shape that protrudes on only one side, instead of a shape that protrudes on both sides of.

【0015】ここで、高耐圧MOSトランジスタの製造
では、ゲート電極11の形成後、N型不純物をイオン注
入によりフィールド酸化膜2の窓開け部分からシリコン
基板1の表面に注入し、その後押し込み拡散することに
より、ゲート電極11の両側でシリコン基板1の表面に
ソース領域5とドレイン領域6とを形成するが、この
時、図1(b)に示すように上述したN型不純物からな
るソース及びドレイン領域5,6がラテラル拡散により
ゲート電極11の下に若干回り込む。
Here, in the manufacture of a high voltage MOS transistor, after the gate electrode 11 is formed, N-type impurities are ion-implanted into the surface of the silicon substrate 1 from the window opening portion of the field oxide film 2 and then diffused by pushing. Thus, the source region 5 and the drain region 6 are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 11. At this time, as shown in FIG. The regions 5 and 6 slightly go under the gate electrode 11 due to the lateral diffusion.

【0016】一方、フィールド酸化膜2の形成により、
フィールド酸化膜2のエッジ部分m〔バーズピーク〕で
ゲート電極11直下のシリコン基板1中のP型不純物で
あるボロンが侵食されてその不純物濃度が低下する。こ
のソース領域5及びドレイン領域6の回り込み量はシリ
コン基板1の不純物濃度が低いほど大きくなることか
ら、前述したようにフィールド酸化膜2のエッジ部分m
でゲート電極11直下のシリコン基板1中の不純物濃度
が低く、その結果、ゲート電極11が延びる方向と交差
する方向に沿うフィールド酸化膜2のエッジ部分mで
は、ソース領域5とドレイン領域6のゲート電極11直
下への回り込み量が大きくなる。
On the other hand, by forming the field oxide film 2,
At the edge portion m [bird's peak] of the field oxide film 2, boron, which is a P-type impurity in the silicon substrate 1 immediately below the gate electrode 11, is eroded and the impurity concentration is lowered. The wraparound amount of the source region 5 and the drain region 6 increases as the impurity concentration of the silicon substrate 1 decreases, so that the edge portion m of the field oxide film 2 as described above.
Therefore, the impurity concentration in the silicon substrate 1 immediately below the gate electrode 11 is low, and as a result, at the edge portion m of the field oxide film 2 along the direction intersecting the direction in which the gate electrode 11 extends, the gates of the source region 5 and the drain region 6 are The amount of wraparound just below the electrode 11 increases.

【0017】しかし、本発明の高耐圧MOSトランジス
タでは、フィールド酸化膜2のエッジ部分mでのゲート
電極11に幅広部12を形成したことにより、図1
(c)に示すようにソース領域5とドレイン領域6のゲ
ート電極11直下への回り込み量が大きくなっても、ソ
ース領域5とドレイン領域6との間隔を十分確保するこ
とができるので、ソース領域5とドレイン領域6間でリ
ークが発生することを回避することができる。これによ
り、半導体装置の高集積化、高速化に伴い、ゲート電極
11の幅寸法〔ゲート長〕が小さくなっても、リーク発
生を確実に防止できる。
However, in the high withstand voltage MOS transistor of the present invention, the wide portion 12 is formed in the gate electrode 11 at the edge portion m of the field oxide film 2, so that FIG.
As shown in (c), even if the amount of the source region 5 and the drain region 6 sneaking directly under the gate electrode 11 is large, a sufficient distance between the source region 5 and the drain region 6 can be ensured. It is possible to prevent a leak from occurring between the drain region 5 and the drain region 6. As a result, even if the width dimension [gate length] of the gate electrode 11 becomes smaller due to the higher integration and higher speed of the semiconductor device, it is possible to reliably prevent the occurrence of leakage.

【0018】尚、上記実施例では、P型シリコン基板を
使用したNチャンネルMOSトランジスタについて説明
したが、本発明はこれに限定されることなく、N型シリ
コン基板を使用してP型不純物拡散層〔Pウエル〕を形
成し、その拡散層内に素子を形成したNチャンネルMO
Sトランジスタについても適用可能である。
Although the N-channel MOS transistor using the P-type silicon substrate has been described in the above embodiment, the present invention is not limited to this, and the P-type impurity diffusion layer may be used using the N-type silicon substrate. N channel MO in which a [P well] is formed and an element is formed in the diffusion layer
It is also applicable to the S transistor.

【0019】[0019]

【発明の効果】本発明によれば、ゲート電極が延びる方
向と交差する方向に沿うフィールド酸化膜のエッジ部分
で、ゲート電極に幅広部を形成したことにより、そのフ
ィールド酸化膜のエッジ部分でのソース及びドレイン領
域のゲート電極下への回り込みが生じても、ソース領域
とドレイン領域との間隔を十分に確保することができ、
その回り込みによるリークの発生を未然に防止できて信
頼性の高いMOSトランジスタを提供できると共に製品
の歩留まりも向上する。
According to the present invention, since the wide portion is formed in the gate electrode at the edge portion of the field oxide film along the direction intersecting with the extending direction of the gate electrode, the edge portion of the field oxide film is formed. Even if the source and drain regions go under the gate electrode, a sufficient distance can be secured between the source region and the drain region,
Leakage due to the wraparound can be prevented in advance, a highly reliable MOS transistor can be provided, and the product yield is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る高耐圧MOSトランジスタの一実
施例を示すもので、(a)はその平面図、(b)は
(a)のA−A線に沿う断面図、(c)は(a)のB−
B線に沿う断面図
1A and 1B show an embodiment of a high breakdown voltage MOS transistor according to the present invention, in which FIG. 1A is a plan view thereof, FIG. 1B is a sectional view taken along line AA of FIG. 1A, and FIG. B- in (a)
Sectional view along line B

【図2】本発明の変形例を説明するためのもので、
(a)(b)はゲート電極の形状の二例を示す平面図
FIG. 2 is for explaining a modified example of the present invention,
(A) (b) is a top view which shows two examples of the shape of a gate electrode.

【図3】高耐圧MOSトランジスタの従来例を説明する
ためのもので、(a)はその平面図、(b)は(a)の
C−C線に沿う断面図
3A and 3B are diagrams for explaining a conventional example of a high breakdown voltage MOS transistor, in which FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view taken along line CC of FIG.

【図4】(a)は図3(a)のD−D線に沿う断面図、
(b)は図3(a)のE−E線に沿う断面図
4A is a sectional view taken along the line D-D in FIG.
3B is a sectional view taken along the line EE of FIG.

【符号の説明】[Explanation of symbols]

1 P型シリコン基板 2 フィールド酸化膜 3 ゲート酸化膜 5 ソース領域 6 ドレイン領域 11 ゲート電極 12 幅広部 m フィールド酸化膜のエッジ部分 1 P-type silicon substrate 2 Field oxide film 3 Gate oxide film 5 Source region 6 Drain region 11 Gate electrode 12 Wide part m Field oxide film edge part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 P型シリコン基板の表面に素子形成領域
を残す選択酸化法によりフィールド酸化膜を形成し、そ
のフィールド酸化膜の窓開け部分にゲート酸化膜を介し
てゲート電極をフィールド酸化膜に跨がるように形成
し、そのゲート電極の両側で窓開け部分に高濃度のN型
不純物をゲート電極及びフィールド酸化膜に対してセル
フアラインにより選択的に拡散してソース及びドレイン
領域を形成した高耐圧MOSトランジスタにおいて、ゲ
ート電極が延びる方向と交差する方向に沿うフィールド
酸化膜のエッジ部分で、ゲート電極に幅広部を形成した
ことを特徴とする高耐圧MOSトランジスタ。
1. A field oxide film is formed on a surface of a P-type silicon substrate by a selective oxidation method which leaves an element formation region, and a gate electrode is formed into a field oxide film through a gate oxide film in a window opening portion of the field oxide film. The gate electrode and the gate electrode are formed so as to straddle, and high-concentration N-type impurities are selectively diffused by self-alignment with respect to the gate electrode and the field oxide film in the window opening portions on both sides of the gate electrode to form the source and drain regions. A high breakdown voltage MOS transistor, characterized in that, in the high breakdown voltage MOS transistor, a wide portion is formed in a gate electrode at an edge portion of a field oxide film along a direction intersecting a direction in which a gate electrode extends.
【請求項2】 P型シリコン基板の表面に素子形成領域
を残して選択酸化法によりフィールド酸化膜を形成する
工程と、 前記素子形成領域となるフィールド酸化膜の窓開け部分
を二つに仕切り、フィールド酸化膜に跨がり、フィール
ド酸化膜のエッジ部で幅広部を有するゲート電極をゲー
ト酸化膜を介して形成する工程と、 前記フィールド酸化膜及び前記ゲート電極をマスクにN
型不純物を注入する工程と、 熱処理により注入した不純物を拡散する工程とを特徴と
する高耐圧MOSトランジスタの製造方法。
2. A step of forming a field oxide film by a selective oxidation method while leaving an element formation region on the surface of a P-type silicon substrate, and dividing a window opening portion of the field oxide film to be the element formation region into two. Forming a gate electrode across the field oxide film and having a wide portion at an edge portion of the field oxide film through the gate oxide film; and using the field oxide film and the gate electrode as a mask
A method of manufacturing a high breakdown voltage MOS transistor, comprising: a step of implanting a type impurity; and a step of diffusing the implanted impurity by heat treatment.
JP3402594A 1994-03-04 1994-03-04 High breakdown strength mos transistor and its manufacture Withdrawn JPH07245395A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3402594A JPH07245395A (en) 1994-03-04 1994-03-04 High breakdown strength mos transistor and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3402594A JPH07245395A (en) 1994-03-04 1994-03-04 High breakdown strength mos transistor and its manufacture

Publications (1)

Publication Number Publication Date
JPH07245395A true JPH07245395A (en) 1995-09-19

Family

ID=12402840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3402594A Withdrawn JPH07245395A (en) 1994-03-04 1994-03-04 High breakdown strength mos transistor and its manufacture

Country Status (1)

Country Link
JP (1) JPH07245395A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0800216A2 (en) * 1996-04-04 1997-10-08 International Business Machines Corporation Transistor gate to minimize agglomeration defect sensitivity
JP2002118176A (en) * 2000-10-05 2002-04-19 Nec Corp Semiconductor device
JP2012500496A (en) * 2008-08-19 2012-01-05 フリースケール セミコンダクター インコーポレイテッド Transistor with gain change compensation
JP2012094874A (en) * 2011-11-11 2012-05-17 Canon Inc Photoelectric conversion device, and method of manufacturing semiconductor device
CN109888001A (en) * 2019-02-03 2019-06-14 中国科学院微电子研究所 Semiconductor devices and its manufacturing method and electronic equipment including the device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0800216A2 (en) * 1996-04-04 1997-10-08 International Business Machines Corporation Transistor gate to minimize agglomeration defect sensitivity
EP0800216A3 (en) * 1996-04-04 1998-10-07 International Business Machines Corporation Transistor gate to minimize agglomeration defect sensitivity
JP2002118176A (en) * 2000-10-05 2002-04-19 Nec Corp Semiconductor device
JP2012500496A (en) * 2008-08-19 2012-01-05 フリースケール セミコンダクター インコーポレイテッド Transistor with gain change compensation
JP2012094874A (en) * 2011-11-11 2012-05-17 Canon Inc Photoelectric conversion device, and method of manufacturing semiconductor device
CN109888001A (en) * 2019-02-03 2019-06-14 中国科学院微电子研究所 Semiconductor devices and its manufacturing method and electronic equipment including the device
WO2020155432A1 (en) * 2019-02-03 2020-08-06 中国科学院微电子研究所 Semiconductor device and fabrication method therefor, and electronic device comprising device

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