JPH07245309A - Formation of bump - Google Patents
Formation of bumpInfo
- Publication number
- JPH07245309A JPH07245309A JP6034375A JP3437594A JPH07245309A JP H07245309 A JPH07245309 A JP H07245309A JP 6034375 A JP6034375 A JP 6034375A JP 3437594 A JP3437594 A JP 3437594A JP H07245309 A JPH07245309 A JP H07245309A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bump
- flux
- substrate
- metal material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子を回路基板
上にフェースダウン実装するためのバンプの形成方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump forming method for mounting a semiconductor element face down on a circuit board.
【０００２】[0002]
【従来の技術】従来、半導体素子上にバンプを形成する
方法として、例えば特開平４−２３６４３３号公報に示
されるように、半導体素子の電極に対向して、その表面
に凹部を有する支持基板を用いるものがある。2. Description of the Related Art Conventionally, as a method of forming bumps on a semiconductor element, as shown in, for example, Japanese Patent Application Laid-Open No. 4-236433, a support substrate having a concave portion on the surface facing a semiconductor element electrode is used. There is something to use.
【０００３】図１において、１はアルミニウムやステン
レス等により形成された支持基板であり、その表面には
半導体素子の電極に対向して立方体状の凹部２が形成さ
れている。この凹部２にフラックスを一成分とする低融
点合金または金属からなる金属材料３を、スキージ４を
摺動させることにより充填する。そして図１（ｂ）に示
すように、半導体素子５上に形成された突起電極６が支
持基板１の凹部２に対向するよう載置する。この状態で
加熱された窒素雰囲気でリフロー処理を行い、半導体素
子５の突起電極６を加熱するとともに金属材料３を溶融
し、図３に示すようにバンプ９を半導体素子上に形成す
る。In FIG. 1, reference numeral 1 denotes a support substrate made of aluminum, stainless steel or the like, and a cubic recess 2 is formed on the surface thereof so as to face the electrodes of the semiconductor element. The concave portion 2 is filled with a metal material 3 made of a low melting point alloy or a metal containing flux as one component by sliding a squeegee 4. Then, as shown in FIG. 1B, the bump electrodes 6 formed on the semiconductor element 5 are placed so as to face the recesses 2 of the support substrate 1. In this state, reflow treatment is performed in a heated nitrogen atmosphere to heat the protruding electrodes 6 of the semiconductor element 5 and melt the metal material 3 to form bumps 9 on the semiconductor element as shown in FIG.
【０００４】[0004]
【発明が解決しようとする課題】一般にプリント基板上
に電子部品を半田付けする場合に、リフロー処理を加熱
された窒素中で行うと、金属材料中のフラックスの酸化
や劣化が起こりにくいという利点があるのであるが、上
述のフェースダウン実装のように支持基板１に半導体素
子５を載置した状態でリフロー処理を行なうと、半導体
素子５により密閉された凹部２の空間に、窒素置換が行
われない酸素が残存する。この残存酸素により金属材料
３中のフラックス成分が酸化あるいは変性を起こし、図
３に示すようにフラックス残渣８がバンプ９と半導体素
子５との接点付近に残ってしまう。このフラックス残渣
は、洗浄しても除去が困難なうえ、耐電圧の低下やマイ
グレーションによる端子間のショート等を引き起こして
しまう。Generally, when soldering an electronic component on a printed circuit board, if the reflow treatment is performed in heated nitrogen, there is an advantage that the flux in the metal material is less likely to be oxidized or deteriorated. However, if the reflow process is performed with the semiconductor element 5 placed on the support substrate 1 as in the face-down mounting described above, nitrogen replacement is performed in the space of the recess 2 sealed by the semiconductor element 5. No oxygen remains. The residual oxygen oxidizes or modifies the flux component in the metal material 3, and the flux residue 8 remains near the contact point between the bump 9 and the semiconductor element 5 as shown in FIG. This flux residue is difficult to remove even after cleaning, and causes a decrease in withstand voltage and a short circuit between terminals due to migration.
【０００５】また、フラックスによる金属粒子の酸化膜
の除去効果も低下するので、金属粒子の酸化膜が十分除
去されず、金属粒子が完全溶融せず粒子状で残ってしま
う。このため図に示すような崩れた形状のバンプ９にな
ってしまい、接続抵抗の上昇や接続不良を引き起こし、
歩留まりが悪くなる。Further, since the effect of removing the oxide film of the metal particles by the flux is also reduced, the oxide film of the metal particles is not sufficiently removed, and the metal particles remain in a particulate form without being completely melted. For this reason, the bumps 9 have a deformed shape as shown in the figure, which causes an increase in connection resistance and connection failure,
Yield deteriorates.
【０００６】このように従来の方法では、フラックスの
酸化や劣化が起こりにくいという、窒素リフローの効果
を十分に発揮できない。そこで本発明は、半導体素子を
凹部を形成した支持基板上に載置した状態で、窒素雰囲
気でリフロー処理を行っても、隙間の酸素が窒素に置換
されるよう、通気性のある多孔質の支持基板を用いてバ
ンプを形成するものである。As described above, according to the conventional method, the effect of nitrogen reflow, that is, the oxidation and deterioration of the flux hardly occur, cannot be sufficiently exerted. Therefore, the present invention is a porous gas-permeable so that the oxygen in the gap is replaced with nitrogen even when the semiconductor element is placed on the supporting substrate having the concave portion and the reflow treatment is performed in a nitrogen atmosphere. The bumps are formed using a supporting substrate.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に本発明のバンプの形成方法は、多孔質材料よりなる支
持基板の表面に形成した凹部に、フラックスを有する金
属材料を充填し、半導体素子に形成した突起電極が前記
凹部に対向するよう前記半導体素子を支持基板に載置
し、加熱された窒素雰囲気中で前記金属材料を溶融し、
半導体素子の突起電極にバンプを形成するものである。In order to solve the above problems, the bump forming method of the present invention is a semiconductor device in which a concave portion formed on the surface of a support substrate made of a porous material is filled with a metal material having a flux to form a semiconductor. The semiconductor element is placed on a supporting substrate so that the protruding electrodes formed on the element face the concave portion, and the metal material is melted in a heated nitrogen atmosphere,
A bump is formed on a protruding electrode of a semiconductor element.
【０００８】[0008]
【作用】上記方法によれば、窒素雰囲気でリフロー処理
において、窒素が多孔質の支持基板中を通過し、支持基
板の凹部に充填されている金属材料に到達する。これに
より酸素から窒素への置換が十分行われる。このためフ
ラックスの酸化や変性が起こらず洗浄性にすぐれかつ完
全溶融したバンプが得られる。According to the above method, in the reflow process in the nitrogen atmosphere, nitrogen passes through the porous support substrate and reaches the metal material filled in the concave portion of the support substrate. As a result, the replacement of oxygen with nitrogen is sufficiently performed. Therefore, the flux is not oxidized or denatured, and the bump having excellent cleaning property and completely melted can be obtained.
【０００９】[0009]
【実施例】以下に本発明の一実施例を図面を参照して説
明する。図１は本発明のバンプの形成方法の一実施例を
表すものであり、従来と異なる点は、支持基板１を多孔
質材料で形成したことであり、詳しくは炭素の焼結体
（イビデン（株）製）の基板の表面に、半導体素子５の
突起電極６に対向して、金属材料３を充填すべき凹部２
を形成したことである。そしてこの支持基板１を用い加
熱した窒素雰囲気中でリフローを行うことにより、周辺
の窒素が多孔質の支持基板１中を通過して凹部２に到達
し、酸素と置換されるようにしたことである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the bump forming method of the present invention. What is different from the conventional method is that the supporting substrate 1 is made of a porous material. A recessed portion 2 to be filled with the metal material 3 on the surface of the substrate (made by Co., Ltd.) facing the protruding electrode 6 of the semiconductor element 5.
Is formed. Then, by performing reflow in a heated nitrogen atmosphere using this support substrate 1, peripheral nitrogen passes through the porous support substrate 1 to reach the concave portion 2 and is replaced with oxygen. is there.
【００１０】この支持基板１は、炭素の焼結体の板の表
面に、機械加工またはエッチングなどにより半導体素子
の突起電極に対向する位置に金属材料を充填する凹部２
を形成したものである。The supporting substrate 1 is a recess 2 for filling a metal material in a position facing a protruding electrode of a semiconductor element by machining or etching on the surface of a carbon sintered plate.
Is formed.
【００１１】本実施例において金属材料３は、フラック
スを９重量％含有し、金属粒子の平均粒径が１０μｍ以
下であるＳｎ−３７Ｐｂ共晶合金を含有したペースト状
のクリーム半田を用いた。予め半導体素子５上に金線を
用いてスタッドバンプボンディング法により形成された
突起電極６と支持基板１の表面に形成された凹部２とを
位置合わせし整合する。窒素雰囲気でリフロー処理を行
うことにより、クリーム半田を溶融して図２のようにバ
ンプ７として半導体素子５上に転写する。In the present embodiment, the metal material 3 was a paste-like cream solder containing 9% by weight of flux and containing Sn-37Pb eutectic alloy having an average metal particle size of 10 μm or less. The bump electrode 6 previously formed on the semiconductor element 5 by a stud bump bonding method using a gold wire and the recess 2 formed on the surface of the support substrate 1 are aligned and aligned. By performing the reflow process in the nitrogen atmosphere, the cream solder is melted and transferred onto the semiconductor element 5 as the bumps 7 as shown in FIG.
【００１２】本実施例の効果を確認するため、図２の状
態の半導体素子１４を水系洗浄剤で洗浄し、アメリカ軍
用規格のＭＩＬ−Ｐ−２８８０９Ａの４．８．２と６．
６．１に定められたオメガメーターでフラックス残渣を
測定した。従来のものは３０μｇ Ｎａｃｌ／ｓｑ．ｉ
ｎと同規格の１４μｇ Ｎａｃｌ／ｓｑ．ｉｎを大きく
上回っていたのに対し、本実施例によれば、０μｇＮａ
ｃｌ／ｓｑ．ｉｎとフラックス残渣が皆無であった。ま
た粒子状の未溶融部分もなく、すべてのバンプが完全溶
融を呈していた。In order to confirm the effect of this embodiment, the semiconductor element 14 in the state shown in FIG. 2 is washed with a water-based cleaning agent, and the military standard MIL-P-28809A 4.8.2 and 6.
The flux residue was measured with the omega meter specified in 6.1. The conventional one is 30 μg Nacl / sq. i
14 μg Nacl / sq. In contrast to this, according to the present embodiment, 0 μg Na
cl / sq. There was no in or flux residue. Further, there was no particulate unmelted portion, and all the bumps were completely melted.
【００１３】なお上記実施例において、支持基板１に用
いた炭素の焼結体の比重は約１．７であり、他の多孔質
焼結体であるアルミナセラミックの比重（３〜４）より
も小さく軽量化が可能である。さらに熱伝達率もアルミ
ナセラミックよりも優れているので、リフロー時に加え
る熱量が少なくて済むという利点があり、加えて、硬さ
はアルミナセラミックよりも軟らかいので、凹部の加工
が容易であるという利点もある。また、金属材料３には
金属粒子の平均粒径が１０μｍ以下のＳｎ−３７Ｐｂ共
晶合金を用いたが、金属粒子の材料としては、Ｓｎ，Ｐ
ｂ，Ｂｉ，Ｓｂ，Ｉｎを主とする合金あるいは単体を利
用しても同様の効果を得ることができる。また、ペース
ト状の金属材料の代わりにペレット状の金属材料を用い
ることも可能である。In the above embodiment, the specific gravity of the carbon sintered body used for the support substrate 1 is about 1.7, which is higher than the specific gravity (3 to 4) of the other porous sintered alumina ceramics. It can be small and lightweight. In addition, since it has a higher heat transfer coefficient than alumina ceramics, it has the advantage of requiring less heat to be applied during reflow.In addition, the hardness is softer than that of alumina ceramics, so it is easy to process the recesses. is there. Further, Sn-37Pb eutectic alloy having an average particle diameter of metal particles of 10 μm or less was used as the metal material 3, but as the material of the metal particles, Sn, P
The same effect can be obtained by using an alloy containing b, Bi, Sb, or In as a main component or a simple substance. It is also possible to use a pellet-shaped metal material instead of the paste-shaped metal material.
【００１４】[0014]
【発明の効果】以上のように本発明によれば、金属材料
を充填する凹部を有する支持基板に多孔質の材料を用い
ることで、窒素雰囲気でのリフロー処理において半導体
素子と支持基板との間で、酸素から窒素への置換が十分
行わせることができる。このためフラックスが酸化ある
いは変性しないので、完全溶融したバンプが得られ、フ
ラックスの残渣もなくなり、接続抵抗の低いバンプが得
られるのはもちろんのこと、転写歩留りの高い半導体素
子が得られ、実用上極めて有利なものとなる。As described above, according to the present invention, by using a porous material for the supporting substrate having the concave portion filled with the metal material, the gap between the semiconductor element and the supporting substrate is increased during the reflow process in the nitrogen atmosphere. Thus, the replacement of oxygen with nitrogen can be sufficiently performed. Therefore, since the flux is not oxidized or modified, completely melted bumps can be obtained, flux residue can be eliminated, and bumps with low connection resistance can be obtained, and of course, semiconductor elements with high transfer yield can be obtained, which is practically used. It will be extremely advantageous.
【図１】バンプの形成工程を示す断面図FIG. 1 is a sectional view showing a bump forming process.
【図２】本発明の一実施例におけるバンプが形成された
半導体素子の断面図FIG. 2 is a sectional view of a semiconductor device having bumps according to an embodiment of the present invention.
【図３】従来例のバンプが形成された半導体素子の断面
図FIG. 3 is a cross-sectional view of a conventional semiconductor device having bumps formed thereon.
１ 支持基板 ２ 凹部 ３ 金属材料 ４ スキージ ５ 半導体素子 ６ 突起電極 ７，９ バンプ ８ フラックス残渣 1 Support Substrate 2 Recess 3 Metal Material 4 Squeegee 5 Semiconductor Element 6 Projection Electrode 7,9 Bump 8 Flux Residue
Claims (1)
した凹部に、フラックスを有する金属材料を充填し、半
導体素子に形成した突起電極が前記凹部に対向するよう
前記半導体素子を支持基板に載置し、加熱された窒素雰
囲気中で前記金属材料を溶融し、半導体素子の突起電極
にバンプを形成するバンプの形成方法。1. A supporting substrate made of a porous material is filled with a metal material having a flux in a concave portion formed on the surface of the supporting substrate, and the semiconductor element is used as a supporting substrate so that the protruding electrode formed on the semiconductor element faces the concave portion. A method of forming a bump, comprising placing and melting the metal material in a heated nitrogen atmosphere to form a bump on a protruding electrode of a semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03437594A JP3173546B2 (en) | 1994-03-04 | 1994-03-04 | Method of forming bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03437594A JP3173546B2 (en) | 1994-03-04 | 1994-03-04 | Method of forming bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07245309A true JPH07245309A (en) | 1995-09-19 |
| JP3173546B2 JP3173546B2 (en) | 2001-06-04 |
Family
ID=12412429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03437594A Expired - Fee Related JP3173546B2 (en) | 1994-03-04 | 1994-03-04 | Method of forming bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3173546B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6432807B1 (en) | 1999-06-10 | 2002-08-13 | Nec Corporation | Method of forming solder bumps on a semiconductor device using bump transfer plate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4376533B2 (en) | 2003-03-25 | 2009-12-02 | パナソニック株式会社 | Ultrasonic probe |
-
1994
- 1994-03-04 JP JP03437594A patent/JP3173546B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6432807B1 (en) | 1999-06-10 | 2002-08-13 | Nec Corporation | Method of forming solder bumps on a semiconductor device using bump transfer plate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3173546B2 (en) | 2001-06-04 |
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