JPH07240423A - Method of manufacturing bipolar transistor and method of manufacturing bimos - Google Patents

Abstract

PURPOSE:To improve the characteristics of a transistor, by preventing unneces sary etching of a part where an emitter is to be formed. CONSTITUTION:An aperture part 29 which exposes a part where a base region is to be formed is formed, and a base leading-out electrode 31a is formed on the side wall of the aperture part 29. A TEOS oxide film 43 is formed on the whole surface of a specimen. The TEOS oxide film on a part where an emitter is to be formed is selectively eliminated, by using a wet etching method in the state that the TEOS oxide film part on the base leading-out electrode 31a is covered with a thin film (a poly silicon side wall) 49a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor manufacturing method and a BiMOS manufacturing method.

[0002]

2. Description of the Related Art BiCMOS which is a kind of BiMOS
Is the high speed of bipolar transistor and CMOSFET
(Hereinafter, CMOS) has attracted attention as a semiconductor device having high integration. As a conventional method of manufacturing a bipolar transistor portion in such a BiCMOS, there is a method based on a self-aligned two-layer polysilicon structure (for example, Document I: "Technical Research Report of Institute of Electronics, Information and Communication Engineers" (SDM91-39)). ) p.43-48 Especially Fig.6).
According to the method disclosed in this document, the bipolar transistor portion in BiCMOS is manufactured as follows. (1) A thermal oxide film and a conductive film are formed on the silicon substrate on which the collector region has been formed. (2) An opening is formed in a predetermined portion of the conductive film and the thermal oxide film to expose a portion where the base region is to be formed in the collector region. (3) A base contact made of polysilicon is formed on the side wall of the opening so as to connect the portion where the base region is to be formed and the conductive film. (4) A spacer made of an insulating film is further formed on the base contact, that is, on the side wall of the opening. (5) After that, the base region, emitter region, and
Form an emitter electrode. With this method, the base contact (also referred to as a base extraction electrode), the spacer made of an insulating film, the base region, the emitter region, and the emitter electrode could be formed by self-alignment.

[0003]

However, in the above-described conventional method for manufacturing a bipolar transistor, the base lead-out electrode and the spacer made of an insulating film are both formed by forming RIE (reactive ion) thin films for forming them. It is obtained by selectively etching by etching method and leaving it as sidewalls on the side wall of the opening, so that the silicon substrate (actually the epitaxial layer) is also etched in each etching. Therefore, there is a problem in that the effective thickness of the epitaxial layer becomes thin and the thickness of the epitaxial layer varies in various parts of the substrate. Such a problem causes a decrease and variation in the BV _CEO (collector-emitter breakdown voltage) of the bipolar transistor, which in turn leads to a decrease in the yield of the integrated circuit. Therefore, improvement is desired. Further, in particular, in RIE when forming a spacer made of an insulating film, the surface of the portion where the emitter region is to be formed is directly damaged by etching ions, so there is a high risk that defects will occur in the portion where the emitter region is to be formed. This flaw is
It adversely affects the device characteristics. This defect is especially
When it occurs near the base junction, it becomes a recombination center and increases the recombination current (leakage current) in the low current region of the base current, which in turn reduces the h _FE (current amplification factor) of the bipolar transistor in the low current region. Will lead to a decline.

[0004]

Therefore, in the first invention of this application, a bipolar transistor is described in the following (a) to (a).
It is manufactured by a method including the step (j).

(A) A step of forming a thermal oxide film and a conductive film for forming a part of a base electrode in this order on a silicon substrate having a collector region.

(B) A step of forming an opening for exposing a base region formation planned portion in the collector region in the conductive film and the thermal oxide film.

(C) On the side wall of the opening, a conductive side wall film to be a base take-out electrode for connecting the portion where the base region is to be formed and the conductive film which is a part of the base electrode is formed. Process.

(D) A step of forming a tetraethyl orthosilicate (TEOS) oxide film on the entire surface of the sample on which the conductive side wall film has been formed.

(E) A step of obtaining a base region by implanting impurities into the portion where the base region is to be formed through the formed TEOS oxide film.

(F) A step of forming a thin film of a material having a large selection ratio with respect to the TEOS oxide film on the entire surface of the sample on which the base region has been formed.

(G) The thin film of the material having a large selection ratio is selectively removed so that the portion corresponding to the upper side of the emitter region formation planned portion is removed and the portion corresponding to the upper side of the conductive sidewall film remains. Process.

(H) T exposed by the selective removal
A step of removing the EOS oxide film portion by a wet etching method.

(I) A step of forming an emitter region in a portion where an emitter region is to be formed, which is exposed by removing the TEOS oxide film.

In implementing the first invention, it is preferable that the conductive side wall film is formed by a process including the following steps (1) to (3).

A step of forming a thin film of a material for forming the conductive side wall film on the entire surface of the sample in which the opening has been formed, the thin film being formed according to the shape of the opening.

Step of forming a sidewall film as an etching mask of the thin film on the sidewall of the opening where the thin film is formed.

Step of removing a portion of the thin film of the material for forming the conductive sidewall film, which is not covered with the etching mask.

Step of removing the sidewall film as the etching mask.

According to the method of manufacturing a BiMOS of the second invention of this application, the bipolar transistor in the BiMOS is manufactured by the method of manufacturing a bipolar transistor described in claim 1, and (A): the method of claim 1. The thermal oxide film is also used as a film for forming a gate insulating film of a MOS field effect transistor, and (B): the conductive film of claim 1 is also used as a film for forming a gate electrode of the MOS field effect transistor. C): The TEOS oxide film according to claim 1 is formed by the M
The MOS type field effect transistor is characterized by being used also as a film for forming a side wall film of the OS type field effect transistor.

In carrying out the second invention, after the step (a) in the manufacturing method of the first invention is completed, instead of the step (b), (i) the conductive film is placed in a bipolar transistor formation planned region. Patterning into a shape that will become a part of the base electrode, and into a shape that will become a gate electrode in the MOS field effect transistor formation-scheduled region, and (ii) each of the formed base electrode and gate electrode A step of forming a protective oxide film on the surface of the protective film to protect the gate electrode from being damaged in an etching step for forming a conductive side wall film later, and (iii) the formation of the protective oxide film is completed. It is preferable to perform a step of forming an opening for exposing a base region formation planned portion in the thermal oxide film on the substrate surface of the sample.

[0021]

According to the structure of the first invention, the portion of the TEOS oxide film on the conductive side wall film serving as the base take-out electrode is covered with a thin film, and further, the portion where the emitter region is to be formed is formed by the wet etching method. Selectively remove the TEOS oxide film at. In such selective removal,
It is known that an etchant that can etch the TEOS oxide film and that does not substantially etch the underlying emitter region formation portion (silicon epilayer) is used. Can be exposed. Further, since it is wet etching, damage due to etching ions, which is a problem during dry etching, does not occur. Further, the TEOS oxide film is superior in step coverage to a general CVD oxide film made of silane as a raw material, for example, and a relatively thin film is grown on the side wall surface with good film quality.

Further, in the structure of the first invention in which the conductive side wall film is formed by the method including the steps (1) to (3), the formed conductive side wall film has relatively sharp side surfaces. Such a steep side surface facilitates leaving a thin film of a material having a large selection ratio with respect to the TEOS oxide film in a sidewall shape on the TEOS oxide film portion on the conductive sidewall film.

According to the structure of the second invention, a BiM including a bipolar transistor having the characteristics of the first invention is provided.
OS is obtained. In addition, the TEOS oxide film is used as a MOSFET.
Used to form the side wall of. As I said,
The TEOS oxide film has a better step coverage than a general CVD oxide film made of silane as a raw material, and has a relatively thin film thickness even on the side wall surface with good film quality. This means that a thin sidewall having a good film quality can be obtained as the sidewall of the MOSFET having the LDD structure, which is advantageous, for example, when the sidewall thickness is thinned by the proportional reduction rule.

Further, in the second invention, in the constitution in which the steps (i) to (iii) are carried out instead of the step (b),
In the photolithography step, exposure for forming an opening for exposing a portion where a base region is to be formed and exposure for forming a base electrode and a gate electrode can be performed with one mask. Therefore, the number of exposure masks used can be reduced as compared with the case where the step (b) is performed (for details, refer to the third embodiment described later).

[0025]

Embodiments of the bipolar transistor manufacturing method and the BiMOS manufacturing method of the present application will be described together with reference to the drawings. However, the drawings used for the description only schematically show the dimensions, shapes, and positional relationships of the respective constituent components to the extent that the present invention can be understood. Further, in each drawing used for the explanation, the same components are denoted by the same reference numerals, and the duplicated explanation thereof may be omitted. Further, numerical conditions such as specific resistance, film thickness, temperature, time, etc., materials used, film forming method and the like described below are merely examples of the scope of the present invention.

1. First Example First, a first example will be described with reference to FIGS. In addition, these figures show the state of the cut end of the cross section cut along the gate length direction of the MOSFET in the main process in the manufacturing process of the embodiment (the same applies to FIG. 9 and subsequent figures). . The hatching showing the cross section is partially omitted in order to avoid complication of the drawing.

As the silicon substrate 11, here, a P-type silicon substrate 11 having a specific resistance of 10 to 20 Ω · cm is used.
To prepare. An N-type buried layer 13 is formed in each of the bipolar transistor formation planned region and the P-type MOS transistor (hereinafter referred to as PMOS) formation planned region of the silicon substrate 11 under the conditions of a layer resistance of 40Ω / □ and a diffusion depth of 3.0 μm. Form. Then, the N-type epitaxial layer 15 is grown on this sample under the conditions of a specific resistance of 5 Ω · cm and a thickness of 1.4 μm. Then, in order to form a bipolar isolation layer and an NMOS P well region in this sample, a P
The type impurities are diffused to have a surface concentration of 5 × 10 ¹⁶ and a diffusion depth of 1.4 μm to form a P well layer 17. Then, at the portion corresponding to the N-type buried layer 13 of the sample, P
N type impurities such as (phosphorus) are implanted by ion implantation so that the surface concentration is 5 × 10 ^{16 and the} diffusion depth is 1.4 μm, and then diffused to be connected to the N type buried layers 13.
a, 19b (collector region 1 of bipolar transistor
9a and a PMOS N well layer 19b) are formed simultaneously. Then, a diffusion layer 19aa having a surface concentration of 1 × 10 ¹⁹ is formed in the collector extraction region of the collector region 19a by the well-known photolithography method and implantation method. Then L
A thick field oxide film 21 having a thickness of 7,000 Å is formed by using the OCOS method (FIG. 1A).

Next, this sample is subjected to an oxidation treatment in a wet O ₂ atmosphere at a temperature of 850 ° C. to form a 100 Å thermal oxide film (which is a gate oxide film in the MOS formation region) 23.
To form. Next, a non-doped polysilicon film 25a and a WSi _x (tungsten silicide film) 25 are formed here as a conductive film (a conductive film used as a film for forming a gate electrode in the MOS formation region) for forming a part of the base electrode.
The laminated film 25 with b is formed. Here, the former is LPC
Grow 2000Å by VD (Low Pressure Chemical Vapor Deposition) method,
The latter is formed by the sputtering method. Then, by a known photolithography method and an implantation method, boron is added to the bipolar base-emitter region at 40 KeV and 1 × 10 ¹⁵ i.
Ions are implanted under the conditions of ons / cm ² and phosphorus is further added to the gate region of the MOS at 40 KeV, 1 × 10 ¹⁵ ions /
Ion implantation is performed under the condition of cm ² (not shown). Then,
A non-doped CVD SiO ₂ film 27 is grown to a thickness of 2000 Å on the entire surface of the substrate (FIG. 1 (B)).

Next, an opening 29 is formed in the conductive film 25 and the thermal oxide film 23 to expose the base region formation planned portion in the collector region 19a by using the well-known photolithography technique and etching technique (FIG. Two
(A)).

Then, a polysilicon film 31 is formed here as a thin film for forming a conductive side wall film to be a base take-out electrode on the entire surface of the sample in which the opening 29 has been formed.
It is grown to a thickness of 0Å, and 40K of boron is added to the entire surface.
Ion implantation is performed under the conditions of eV and 1 × 10 ¹⁵ ions / cm ² (FIG. 2B).

Next, the polysilicon film 3 is formed by the well-known RIE method.
1 is etched to form a conductive side wall film (side wall layer) 31a as a base extraction electrode on the side wall of the opening 29.
To form. At this time, since the selective ratio between the conductive side wall film 31a and the substrate (collector region 19a) cannot be obtained, the substrate is etched, but this is no different from the conventional example. Further, the resist 33 is left in the regions where the base electrode of the bipolar transistor and the gate electrode of the MOS are to be formed by the well-known photolithography technique (FIG. 3A).

Next, the well-known etching technique is used to remove the portions of the polysilicon 27 and the conductive film 25 which are not covered with the resist 33, and the NMOS gate electrodes 35n and PM are removed.
OS gate electrode 35p, bipolar base electrode 37
Respectively (FIG. 3 (B)).

Next, using the well-known photolithography technique and the implantation technique, phosphorus (P ⁺ ) is added at 40 KeV and 1 × 10 ¹³ ions in the NMOS formation region using the resist 39 as a mask.
/ LD ² (Lightly Doped
Drain) N ⁻ layer 41 is formed (FIG. 4A). afterwards,
This sample is heat-treated in an N ₂ atmosphere at a temperature of 850 ° C. to activate the impurities in the LDDN ⁻ layer 41 (this heat-treatment may not be necessary in some cases, because it is also used in a later step. .).

Next, a TEOS oxide film 43 is formed on the entire surface of this sample.
Is grown here to a thickness of 500 to 700Å. Here, the flow rate of TEOS is 1.0 slm and the ozone concentration is 1
This TEOS oxide film 4 was formed under the condition of 5 g / cm ³
3 is formed. Of course, the method of forming the TEOS oxide film is not limited to this. The TEOS oxide film has a feature that it is superior in step coverage to a conventional oxide film formed by CVD (a CVD oxide film using monosilane or the like as a source gas; the same applies hereinafter). In addition, the conventional CVD oxide film is 500
If an oxide film with a thin film thickness of ~ 700Å is formed, the growth on the side surface is not sufficient, and the insulating property remains a problem. However, with the TEOS oxide film, a desired insulating film with a relatively thin film thickness can be obtained. Is obtained. In addition, this TEOS oxide film 43
Is used as it is as a sidewall of the gate electrode in the MOS field effect transistor region.
Since the desired characteristics can be obtained even when the EOS oxide film 43 has a small film thickness as described above, it is advantageous when it is necessary to reduce the sidewall film thickness in accordance with the proportional reduction rule accompanying miniaturization of MOSFET.

Next, using the well-known photolithographic technique, the resist 45 is used as a mask and boron (B ⁺ ) is added at 30 KeV.
Ion implantation is performed under the condition of 3 × 10 ¹³ ions / cm ² to form a base diffusion layer (base region) 47 (FIG. 4).
(B)).

Next, a polysilicon film 49 is grown on the entire surface of the sample as a film made of a material having a large selection ratio with respect to the TEOS oxide film by 2500.degree. The resist 51 is left only on the formation region (FIG. 5A).

Next, the polysilicon film 49 is etched by using a known etching technique to leave the polysilicon film 49 only on the emitter base formation region (FIG. 5B).

Next, with respect to the polysilicon film 49, the surface of the TEOS oxide film portion on the portion where the emitter region is to be formed is exposed, and is left on the TEOS oxide film portion on the conductive side wall film. Selectively remove. Here, this is performed by the well-known RIE method. As a result, the polysilicon sidewall 49a is obtained so as to cover the TEOS film formed on the sidewall of the conductive sidewall film 31a (FIG. 6A). This polysilicon sidewall 49
a serves to define the emitter region of the bipolar transistor. Further, since the polysilicon can have a large selection ratio with the oxide film (TEOS oxide film), the TEOS oxide film 43 is etched when the polysilicon film 49 is etched.
Acts as an etching stop oxide film, so that the surface of the silicon substrate (the surface of the collector region 19a) is not etched. Therefore, in this step, since the surface of the silicon substrate is not scraped, it is possible to prevent the effective epi thickness from varying. According to the conventional method, the substrate is shaved at the time of forming the base take-out electrode (base contact) and at the time of forming the spacer (polysilicon sidewall here) made of the insulating film, but in the present invention, the substrate is shaved only by the former step. The amount of abrasion and the variation in etching are small. Therefore, as compared with the conventional method, the occurrence of defects due to etching damage can be reduced, and as a result, it is possible to reduce or prevent the variation of BV _CEO and the deterioration of h _{FE in a} low current region.

Next, using the well-known photolithography technique, the resist 5 is formed so as to open only the base-emitter formation region.
3 is left, and then, a portion of the TEOS film 43 which is not covered with the polysilicon sidewall 49a is removed by using an HF-based wet etching solution to expose a portion where an emitter region is to be formed (FIG. 6B).

Next, a polysilicon film 55 is formed on the entire surface of the sample by L
2000 Å is formed by PCVD method, and then polysilicon film 5
5 Arsenic on the entire surface 1 × 10 ¹⁶ ions / cm ² , 40 Ke
Ion implantation is performed under the condition of V (FIG. 7A).

Next, a well-known photolithographic etching technique is used to form a bipolar emitter electrode 55a. After that, a resist pattern 57 having an opening only in the NMOS formation region is formed by using the well-known photolithography technique, and As is added to the portion exposed from the opening at 5 × 10 ¹⁵ ions / c.
Ion implantation under the conditions of m ² and 40 KeV, S
The / D layer 59 is formed (FIG. 7B).

Next, as in the case of forming the NMOS S / D layer 59, a resist 61 that opens only in the PMOS formation region is formed by using the well-known photolithography technique, and then B (boron) is added at 5 × 10 ¹⁵ ions / Ions are implanted under the conditions of cm ² and 40 KeV to form a PMOS S / D layer 63 (FIG. 8A).

Next, a BPSG film 65 is formed on the entire surface of the sample by CVD.
And then heat-treat this sample in a N ₂ atmosphere at a temperature of 900 ° C. for about 30 minutes to obtain BP.
The surface of the SG film 65 is flattened. At the same time, by this heat treatment, from the emitter electrode 55a and the conductive side wall film 31a, arsenic in the former is diffused into the silicon substrate (base region 47) in the latter, and the emitter region 67 and the side base layer 69 are formed. (Fig. 8
(B)). Further, in this heat treatment, the NMOSS / D layer 5
9. The activation of the PMOS S / D layer 63 is also performed at the same time.

Next, although not shown, a BiCMOS structure is completed through a contact opening and a wiring process.

2. Second Example In the above-described first example, the conductive side wall film 31a has the opening 2
9 (see FIG. 2 (A)), a thin film of the material is formed so that the material for forming the conductive side wall film is embedded, and then the thin film is R
It was obtained by selective removal by the IE method. However, in this case, since the conductive sidewall film 31a has a gentle slope, the polysilicon sidewall 4 to be formed later
9a may be difficult to form. This second embodiment improves on this. This description will be given mainly with reference to FIGS.

By the procedure described with reference to FIGS. 1A, 1B and 2A, the opening 29 is formed (FIG. 9).
(A)).

Next, a thin film 71 of a material for forming the conductive sidewall film, which is formed following the shape of the opening 29, is formed on the entire surface of the sample. Here, the polysilicon film 71 having a thin film thickness of 500 to 700 Å is formed as the thin film. The polysilicon film having such a thin film grows along the side wall and bottom surface of the opening 29 (that is, according to the shape of the opening) without filling the inside of the opening 29 (FIG. 9B).

Next, the opening 29 in which the thin film 71 is formed
A side wall film 73 as an etching mask for the thin film 71 is formed on the side wall of the. Here, a thin film of the etching mask forming material is formed so that the etching mask forming material is embedded in the opening 29. Specifically, the CVD oxide film 73 is formed. Then, the CVD oxide film 73 is etched by a well-known RIE method to form an etching mask 73a in a sidewall state (FIG. 10A).
(B)). An enlarged view of a portion indicated by P in FIG.
That is, an enlargement of the etching mask 73a and its peripheral portion is shown in FIG.

Next, the portion of the polysilicon film 71 not covered with the etching mask 73a is selectively removed.
After this etching is completed, a substantially L-shaped conductive side wall film (base extraction electrode) 71a is formed on the region extending over the side wall and part of the bottom surface of the opening 29 (FIG. 11).
(B)). In the second embodiment as well, the substrate (collector region 19a) is etched in the same manner as in the conventional case when the conductive sidewall film 71a is formed.

Next, according to the procedure described in the first embodiment with reference to FIGS.
The formation of the gate electrode for each OS, the formation of the base electrode of the bipolar transistor, the formation of the TEOS oxide film 43, and the formation of the polysilicon sidewall 49a are performed to obtain the structure shown in FIG. An enlarged view of the Q portion in FIG. 12 (A) is shown in FIG. 12 (B). This FIG. 12 (B)
As can be understood from the above, since the conductive side wall film 71a formed in the second embodiment has a steeper side surface than the conductive side wall film 31a in the first embodiment, the TEOS film 43 is formed.
The side wall of the opening 29 after formation is more prominent than in the case of the first embodiment. Therefore, the formation of the polysilicon sidewall 49a is easier than in the case of the first embodiment.

After this, in FIG. 6B in the first embodiment.
8B, a series of processes such as formation of a base region, exposure of a portion where an emitter region is to be formed, formation of an emitter electrode, formation of an emitter region are performed according to the procedure described with reference to FIG.

3. Third Embodiment In the above-described first and second embodiments, the conductive film 25 is processed into the shape of the base electrode and the shape of the gate electrode after the formation of the conductive side wall film 31a (71a) is completed. However, an example (third embodiment) described below may be used. This description will be given mainly with reference to FIGS. 13 to 15.

First, according to the procedure described with reference to FIGS. 1A and 1B in the first embodiment, the conductive film 25 and the polysilicon film 27 are formed (see FIG. 1B).

Next, as shown in FIG. 13A, the laminated film of the conductive film 25 and the polysilicon film 27 is processed into the base electrode shape of the bipolar transistor and the gate electrode shape of the MOS, respectively, to form the base electrode 37 and the NMOS. Gate electrode 35n and PMOS gate electrode 35p are obtained.

Next, a protective oxide film is formed on the surface of each of the base electrode 37 and the gate electrodes 35n and 35p thus formed to protect the electrodes from being damaged in the subsequent thermal oxide film removing step. . Here, this sample is 85
Oxidation is performed in a wet O ₂ atmosphere at a temperature of 0 ° C. to form a protective oxide film 81 having a thickness of about 200Å on the surfaces of the base electrode 37, the NMOS gate electrode 35 _N , and the PMOS gate electrode 35p. The protective oxide film 81
Are gate electrodes 35 _N , 35 _N during the etching of polysilicon which is performed later to form the conductive side wall film 31a.
_This is to prevent the polysilicon in _{P from} being side-etched.

Next, a resist 83 is formed so as to expose only the base region formation planned portion and its periphery and cover the MOSFET formation region, and then the thermal oxide film 23 previously formed for a gate insulating film or the like is formed. First and second openings are formed by a suitable method to expose a portion where the base region is to be formed.
The opening 29 is obtained in the same manner as in the embodiment (FIG. 13B). A polysilicon film 31 is grown to a thickness of 200 Å here as a thin film for forming a conductive side wall film serving as a base extraction electrode on the entire surface of the sample in which the opening 29 has been formed.
Furthermore, 40 KeV of boron on the entire surface, 1 × 10 ¹⁵ ion
Ions are implanted under the condition of s / cm ² (FIG. 14 (A)).

Next, the polysilicon film 31 is formed in the opening 2
9 and its surroundings (FIG. 14 (B)). In the etching of the polysilicon film 31, the gate electrode 35
_{Since N 3} and 35 _P are covered with the protective oxide film 81, the polysilicon portions in the gate electrodes 35 _N and 35 _P are not side-etched.

Next, the polysilicon film 31 is etched by a well-known RIE method, and a conductive side wall film (side wall layer) 3 as a base extraction electrode is formed on the side wall of the opening 29.
1a is formed (FIG. 15A).

After that, in the first embodiment, as shown in FIGS.
A BiMOS is obtained by carrying out the steps in accordance with the procedure described using.

The advantages of the third embodiment over the first and second embodiments are as follows.

Base electrode 37, NMOS gate electrode 3
5 _N , the opening 29 is substantially formed at the time when the PMOS gate electrode 35p is formed (although the thermal oxide film 23 is not opened). That is, in the first and second embodiments, the exposure mask for forming the opening 29 (see FIG. 2A) and the exposure mask for forming each electrode (see FIG. 3A) are required. , Both exposures are 1 in this third embodiment
It can be done with one exposure mask. Therefore, the first
Also, the number of exposure masks can be reduced as compared with the second embodiment.

[0062]

As is apparent from the above description, according to the bipolar transistor manufacturing method of the first aspect of the present invention, a portion of the TEOS oxide film on the conductive side wall film serving as the base take-out electrode is covered with a thin film. In addition, by using the wet etching method, the T
The EOS oxide film is selectively removed. Therefore, this portion can be exposed without etching the portion where the emitter region is to be formed. The base extraction substrate during electrode formation is etched is not prevented in this invention, since the etching of the substrate which occurs prior to the time of exposing the emitter region to be formed portion can be prevented, deterioration and variation in that amount, BV _CEO Can be reduced or prevented. Further, since the etching is wet etching, etching damage is not caused in the portion where the emitter region is to be formed. As a result, it is possible to prevent the occurrence of defects in the portion where the emitter region is to be formed, so that it is possible to suppress deterioration of transistor characteristics due to the occurrence of defects, for example, deterioration of h _{FE in} the low current region.

According to the BiMOS manufacturing method of the second invention of this application, the manufacturing method of the first invention is used and a predetermined film is used as a film for forming these on the bipolar side and the MOS side. Therefore, a BiMOS including a bipolar transistor having the features of the first invention can be obtained.

[Brief description of drawings]

FIG. 1 is a process drawing for explaining a first embodiment.

FIG. 2 is a process diagram following FIG. 1 for explaining the first embodiment.

FIG. 3 is a process diagram following FIG. 2 for explaining the first embodiment.

FIG. 4 is a process chart following FIG. 3 for explaining the first embodiment.

FIG. 5 is a process chart following FIG. 4 for explaining the first embodiment.

FIG. 6 is a process diagram which follows the process of FIG. 5 for explaining the first embodiment.

FIG. 7 is a process chart following FIG. 6 for explaining the first embodiment.

FIG. 8 is a process chart following FIG. 7 for explaining the first embodiment.

FIG. 9 is a process drawing for explaining the second embodiment.

FIG. 10 is a process chart following FIG. 9 for explaining the second embodiment.

FIG. 11 is a process chart following FIG. 10 for explaining the second embodiment.

FIG. 12 is a process chart following FIG. 11 for explaining the second embodiment.

FIG. 13 is a process drawing for explaining the third embodiment.

FIG. 14 is a process drawing following FIG. 13 for explaining the third embodiment.

FIG. 15 is a process chart following FIG. 14 for explaining the third embodiment.

[Explanation of symbols]

 11: Silicon substrate (P-type silicon substrate) 19a: Collector region 23: Thermal oxide film 25: Conductive film 29: Opening 31a: Conductive sidewall film (base extraction electrode) 43: TEOS oxide film 49a: Polysilicon sidewall 67 : Emitter region 71a: Conductive sidewall film (of the second embodiment)

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display area H01L 27/06

Claims (4)

[Claims] 1. A step of: (a) forming a thermal oxide film and a conductive film for forming a part of a base electrode in this order on a silicon substrate having a collector region; and (b) these conductive film and thermal oxide film. A step of forming an opening for exposing a base region formation planned portion in the collector region, and (c) a base region formation planned portion and a part of the base electrode on a side wall of the opening. A step of forming a conductive side wall film to serve as a base take-out electrode for connecting the conductive side wall film, and (d) a tetraethylorthosilicate (TEOS) oxide film on the entire surface of the sample on which the conductive side wall film has been formed. And (e) a step of implanting impurities through the formed TEOS oxide film into the portion where the base region is to be formed to obtain a base region, and (f) the formation of the base region. The T in charge of the entire surface
A step of forming a thin film of a material having a large selection ratio with respect to the EOS oxide film; A step of selectively removing the thin film so that the portion remains, (h) a step of removing the TEOS oxide film portion exposed by the selective removal by a wet etching method, (i) the TEOS oxide film A step of forming an emitter region in a portion where the emitter region is to be formed, which is exposed by the removal of the above step. 2. The method of manufacturing a bipolar transistor according to claim 1, wherein the conductive sidewall film is a thin film of a material for forming the conductive sidewall film on the entire surface of the sample on which the opening has been formed. And a step of forming a thin film having a film thickness formed according to the shape of the opening, and a sidewall film as an etching mask of the thin film on the sidewall of the opening where the thin film is formed. A step of forming, a step of removing a portion of a thin film of a material for forming the conductive sidewall film that is not covered with the etching mask, and a step of removing the sidewall film as the etching mask And a bipolar transistor manufacturing method. 3. A bipolar transistor in BiMOS is manufactured by the method for manufacturing a bipolar transistor according to claim 1, and the thermal oxide film according to claim 1 is also used as a film for forming a gate insulating film of a MOS field effect transistor. The conductive film of claim 1 is also used as a film for forming a gate electrode of the MOS field effect transistor, and the TEOS oxide film of claim 1 is also used as a film for forming a sidewall film of the MOS field effect transistor. Bi characterized by manufacturing the MOS type field effect transistor
Manufacturing method of MOS. 4. The method of manufacturing a BiMOS according to claim 3, wherein after the step (a) is completed, the conductive film is provided in a bipolar transistor formation planned region instead of the step (b). The shape that becomes part of the base electrode, and M
In the area where the OS type field effect transistor is to be formed, a step of patterning into a shape to be a gate electrode, and (ii) for forming a later conductive side wall film on the surface of each of the formed base electrode and gate electrode Forming a protective oxide film for protecting the gate electrode from being damaged in the etching step of (3), and (iii) forming a base region on the thermal oxide film on the substrate surface of the sample on which the protective oxide film has been formed. And a step of forming an opening for exposing a predetermined portion, the method for manufacturing a BiMOS.