JPH0992743A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and a fabrication method thereof, in which a desired current amplification factor can be attained by fabricating a lateral PNP transistor having a desired effective base width and the reliability is enhanced in the operation of the lateral PNP transistor by blocking leak current to the semiconductor substrate. SOLUTION: An emitter region 30, a collector region 31 and a base region 9 are provided with an isolation film 5 while furthermore the emitter region 30 and the collector region 31 are provided with a heavily doped p-type emitter region 7 and a p-type collector region 9 contiguously to an n<+> -type buried layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a BiCMOS.
The present invention relates to a semiconductor device including a lateral PNP transistor and a CMOS transistor in a process and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art First, referring to FIGS.
The structure of a conventional lateral PNP transistor will be described. 18 is a plan view of the lateral PNP transistor, and FIG. 19 is a sectional view taken along the line XX in FIG.

Referring to both figures, an n type epitaxial layer 4 is formed on a p type silicon substrate 1. An n ⁺ type buried layer 2 is formed so as to extend over the p type silicon substrate 1 and the n type epitaxial layer 4. Also, this n
^A p-type diffusion layer 3 is formed so as to surround the ⁺ type buried layer 2.

A high-concentration p-type emitter region 7 and a high-concentration p-type collector region 8 are formed on the surface of the n-type epitaxial layer 4.
And an n-type base region 9 are formed. The high-concentration p-type emitter region 7, the high-concentration p-type collector region 8,
The n-type base region 9 is isolated from each other by an element isolation insulating film 5 made of a silicon oxide film.

On the surface of the epitaxial layer 4, an emitter electrode 10 communicating with the high-concentration p-type emitter region 7, a collector electrode 11 communicating with the high-concentration p-type collector region 8, and n.
A base electrode 12 communicating with the mold base region 9 is formed with an interlayer insulating film 6 made of a silicon oxide film interposed. Further, an interlayer insulating film 13 is formed so as to cover the emitter electrode 10, the collector electrode 11 and the base electrode 12, and a predetermined wiring layer 14 is formed on the interlayer insulating film 13.

In the lateral PNP transistor having the above-mentioned structure, the n-type epitaxial layer 4 serves as a base region, and a current flows in a lateral direction (LATERAL).

Next, a method of manufacturing the lateral PNP transistor having the above structure will be described with reference to FIGS. The sectional views shown in FIGS. 20 to 29 are according to the section of the lateral PNP transistor shown in FIG.

First, referring to FIG. 20, the impurity concentration is 1
× 10 ¹⁵ ~9 × 10 ¹⁵ on the p-type semiconductor substrate 1 of the atom / cm ^3, a silicon oxide film having a thickness of 50 to 200 nm 2
Form 0.

Then, referring to FIG. 21, a resist film 21 having a predetermined pattern is formed on silicon oxide film 20 by using a photolithography technique. After that, the silicon oxide film 20 is formed using the resist film 21 as a mask.
Is performed to expose the surface of the p-type silicon substrate 1.

Next, referring to FIG. 22, a resist film 21
After removing the silicon oxide film, the silicon oxide film 20 is used as a mask to remove p
By implanting n-type impurities into the surface of the type silicon substrate 1, and then performing heat treatment at about 1100 ° C.,
The n ⁺ type buried layer 2 having an impurity concentration of about 1 × 10 ^{19 to} 9 × 10 ¹⁹ atoms / cm ³ is formed.

Next, referring to FIG. 23, a silicon oxide film 22 having a film thickness of 500 to 2000 Å is formed again on the p-type silicon substrate 1, and then the silicon oxide film 22 is formed by using a photolithography technique. Patterning is performed.

Next, referring to FIG. 24, p-type impurities are implanted into the surface of p-type silicon substrate 1 using oxide film 22 as a mask, and then heat treatment is performed at about 1100 ° C. , Impurity concentration 1 × 10 ^{17 to} 9 × 10 ¹⁷ a
The p-type diffusion layer 3 having a thickness of about tom / cm ³ is formed.

Next, referring to FIG. 25, after removing oxide film 22, a film thickness of 1.6 to 2.5 μm and an impurity concentration of 1 × 10 are formed on the surface of p type semiconductor substrate 1 by an epitaxial growth method. The n-type epitaxial layer 4 of about ^{16 to} 9 × 10 ¹⁶ atoms / cm ³ is formed.

Next, referring to FIG. 26, after forming an oxide film having the same pattern as oxide film 22 shown in FIG. 24 on n-type epitaxial layer 4, using this oxide film as a mask, n. implanting p-type impurities on the surface of the type epitaxial layer 4, by thereafter performing a heat treatment of about 1100 ° C., with to complete the p-type diffusion layer 3, as shown in FIG. 27, n ⁺ -type buried The impurities of the layer 3 are diffused into the n-type epitaxial layer 4.

Next, referring to FIG. 28, a film having a thickness of 5 is formed in a predetermined region of n-type epitaxial layer 4 by the LOCOS method.
An element isolation insulating film 5 made of a silicon oxide film having a thickness of about 00 to 700 nm is formed.

Next, referring to FIG. 29, after forming a resist film having a predetermined pattern shape, n-type impurities are implanted to have an impurity concentration of 1 × 10 ^{21 to} 9 × 10 ²¹ ato.
An n-type base region 9 of about m / cm ³ is formed.

Next, a resist film having a predetermined pattern shape is formed again, and then p-type impurities are implanted to obtain an impurity concentration of 1 × 10 ^{20 to} 9 × 10 ²⁰ atom / cm 2.
A high concentration p-type emitter region 7 and a high concentration p-type collector region 8 of about ³ are formed. The n-type base region 9, the p-type emitter region 7 and the p-type collector region 8 are 800 ° C.
It is activated by heat treatment at 950 ° C.

Then, on the n-type epitaxial layer 4,
An interlayer insulating film 6 made of a silicon oxide film or the like is deposited, and a contact hole communicating with the n-type base region 9, the p-type emitter region 7 and the p-type collector region 8 is opened by using a photolithography technique and a fine processing technique. . After that, Al-S
i or Al-Si-Cu is deposited by a sputtering method of 500 to 1000 nm, and patterning is performed using a photoengraving technique to form an emitter electrode 10 and a collector electrode 1.
1 and the base electrode 12 are formed.

Thereafter, an interlayer oxide film 13 made of a silicon oxide film or the like is deposited so as to cover the emitter electrode 10, the collector electrode 11 and the base electrode 12, so that the lateral PNP transistor shown in FIG. 1 is completed.

Although not shown, the high-concentration p-type emitter region 7, the high-concentration p-type collector region 8 and the n-type base region 9 are formed in the CMOS transistor forming region simultaneously with the manufacturing process of the lateral PNP transistor. N-channel MOS transistor of BiCMOS transistor and n-channel MOS transistor of p-channel type
The p-type source / drain region and the p-type source / drain region are formed at the same time.

[0021]

Next, the problems of the above-mentioned lateral PNP transistor will be described.

First, as the first problem, the lateral PN
The P transistor is a semiconductor element that is sensitive to the state of the surface of the n-type epitaxial layer 4. Therefore, the lateral PN
For the operating characteristics of the P-transistor, B has become more miniaturized.
There is a problem of damage to the surface of the n-type epitaxial layer 4 due to a plasma etching process (for example, etching used for patterning a gate electrode of a MOS transistor) used in a manufacturing process of an iCMOS transistor.

Therefore, in order to solve this problem, in the above-mentioned lateral PNP transistor, the region (G in FIGS. 18 and 19) serving as the effective base is set to LOCOS.
By forming the element isolation oxide film 5 using the
By covering the surface of the n-type epitaxial layer 4 serving as an effective base, damage due to the plasma etching process is reduced.

However, since the width of the effective base depends on the width of the element isolation oxide film 5, the width of the effective base depends on the formation state of the element isolation oxide film 5. Here, unless the element isolation oxide film 5 is formed with high precision, a desired effective base width cannot be obtained, so that there is a problem that the current amplification factor cannot also obtain desired characteristics.

Here, the relationship between the effective base width (W _b ) and the current amplification factor (β) has the relationship shown in the following equation (1), and the effective base width (W _b ) and 1 / β It can be seen that is directly proportional.

[0026]

[Equation 1]

Next, as a second problem, the semiconductor substrate 1
There is a leakage current generated. As shown in FIG. 30, in the conventional lateral PNP transistor, a high concentration p
A part of the holes injected from the type emitter region 7 to the base does not reach the high-concentration p-type collector region 8 and flows out to the p-type silicon substrate 1 as a leakage current as shown by an arrow in the figure.

Therefore, as shown in FIG. 31, high concentration p
Type emitter region 7-base region 9-p type silicon substrate 1
Due to the existence of the parasitic transistor, the operating characteristic of the lateral PNP transistor is deteriorated.

The present invention has been made to solve the above problems, and one object of the present invention is to form a desired base width so that a desired current amplification factor can be obtained. It is an object of the present invention to provide a semiconductor device that can be obtained and a manufacturing method thereof.

Another object of the present invention is to provide a semiconductor device capable of preventing the generation of leakage current to the semiconductor substrate and improving the reliability of the operation of the lateral PNP transistor, and a manufacturing method thereof.

[0031]

In order to achieve the above object, according to a semiconductor device of the present invention, a p-type semiconductor substrate, an n-type epitaxial layer formed on the p-type semiconductor substrate, An n-type buried layer formed so as to straddle the p-type semiconductor substrate and the n-type epitaxial layer, and the n-type buried layer straddling the p-type semiconductor substrate and the n-type epitaxial layer. The p-type diffusion layer formed so as to surround it, and the n-type surrounded by the p-type diffusion layer.
Of a p-type epitaxial layer having a p-type emitter region, a p-type collector region and an n-type base region
NP transistor, the p-type emitter region, the p-type collector region and the n-type base region have an element isolation insulating film for isolating each region from each other, and the p-type emitter region or the p-type collector region. At least one of the regions is provided so as to contact the n-type buried layer.

Preferably, the p-type emitter region and the p-type collector region are a p-type high-concentration impurity region formed near the surface of the n-type epitaxial layer,
And a p-type low-concentration impurity region in contact with the n-type buried layer.

Preferably, in the p-type collector region, the p-type low concentration impurity region is provided inside the p-type high concentration impurity region.

To achieve the above object, according to the method of manufacturing a semiconductor device of the present invention, the first region in which the lateral PNP transistor is formed and the CMOS are formed on the same p-type semiconductor substrate. A method of manufacturing a semiconductor device including a second region in which a transistor is formed, including the following steps.

First, an n-type impurity diffusion layer is formed in the first region and the second region on the main surface of the p-type semiconductor substrate. Then, a p-type first impurity diffusion layer is formed so as to surround the n-type impurity diffusion layer formed in the first region.

Next, an n-type epitaxial layer is formed on the main surface of the p-type semiconductor substrate. After that, p-type impurities are introduced into the n-type epitaxial layer located above the p-type first impurity diffusion layer to complete the p-type diffusion layer together with the p-type first impurity diffusion layer.

Next, heat treatment is applied to the p-type semiconductor substrate and the n-type epitaxial layer to form the p-type semiconductor substrate in the first region and the second region together with the n-type impurity diffusion layer. An n-type buried layer straddling the n-type epitaxial layer is completed.

Next, in the n-type epitaxial layer of the second region, the same process as the p-type impurity introduction process for forming the p-type well communicating with the n-type buried layer is performed to form the first region of the first region. A p-type impurity is introduced into at least one of the emitter formation region and the collector formation region to form a p-type low concentration impurity region reaching the n-type buried layer.

Next, on the surface of the n-type epitaxial layer in the first region, an element isolation insulating film is formed by the LOCOS method so as to separate the emitter forming region, the collector forming region and the base forming region from each other. Is formed.

Next, the n-channel MO of the second area is formed.
An n-type base region is formed in the base formation region by the same process as the n-type impurity introduction process for forming the n-type source / drain regions of the S transistor.

Next, the p-channel MO of the second region is formed.
In order to form the p-type source / drain region of the S transistor, a p-type high concentration impurity region is formed on the surface of the emitter forming region and the collector forming region by the same process as the p-type impurity introducing process.

Preferably, in the step of forming the p-type low-concentration impurity region in the p-type collector forming region, the side surface of the p-type low-concentration impurity region is more than the side surface of the p-type high-concentration impurity region. One is formed closer to the p-type diffusion layer.

According to the above-described semiconductor device and the method of manufacturing the same, each region is formed so as to reach the n-type buried layer in at least one of the emitter region and the collector region. In this case, the emitter region or the collector region is different from the position where the p-type low-concentration impurity region reaching the n-type buried layer is formed with the element isolation insulating film for separating the emitter region, the collector region and the base region from each other. It is manufactured in an independent process regardless.

Therefore, the effective base width formed below the element isolation insulating film can be formed as designed without being affected by the formation position of the element isolation insulating film.

As a result, since the effective base width can be formed to a predetermined width as described above, it becomes possible to obtain a desired current amplification factor and to provide a high performance lateral PNP transistor.

The p-type low-concentration impurity region is BiCM.
Since it can be manufactured in the same process as the p-type well forming process in the manufacturing process of the OS transistor, the p-type low concentration impurity region can be manufactured without increasing the number of manufacturing processes.

In the emitter region or collector region, the p-type low concentration impurity region is formed so as to reach the n-type buried layer as described above.

As a result, in particular, in the collector region, the trap cross-sectional area of holes injected from the emitter region becomes large, so that the injection efficiency of the emitter current can be improved.

As a result, the current amplification factor increases and it becomes possible to provide a high performance lateral PNP transistor.

Further, in the emitter region, the side surface of the p-type low concentration impurity region is provided inside the side surface of the p-type high concentration impurity region.

As a result, the punch-through breakdown voltage between the p-type diffusion layer and the p-type low-concentration impurity region is improved, and the current amplification factor can be increased.

Therefore, this also makes it possible to provide a high performance lateral PNP transistor.

[0053]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, Embodiment 1 based on the present invention will be described with reference to the drawings.

First, the structure of the lateral PNP transistor according to the first embodiment will be described with reference to FIG. The sectional view shown in FIG. 1 corresponds to the sectional view taken along the line XX in FIG.

First, the impurity concentration is 1 × 10 ^{15 to} 9 × 10.
^On the p-type silicon substrate 1 of about ¹⁵ atom / cm ³ ,
Impurity concentration is 1 × 10 ^{16 to} 9 × 10 ¹⁶ atom / cm ³
The n-type epitaxial layer 4 is formed to some extent.

Between the p-type silicon substrate 1 and the n-type epitaxial layer 4, the impurity concentration is 1 × 10 ¹⁹ so as to extend over the p-type silicon substrate 1 and the n-type epitaxial layer 4.
The n ⁺ -type buried layer 2 having a thickness of about 9 × 10 ¹⁹ atoms / cm ³ is formed.

The n-type epitaxial layer 4 has n ⁺
The impurity concentration is 1 × 10 ¹⁷ to surround the mold burying layer 2.
9 × 10 ¹⁷ atom / cm ³ of about p-type diffusion layer 3 is formed.

At a predetermined position on the surface of the n-type epitaxial layer 4, an emitter region 30, a collector region 31 and a base region 9 are formed, thereby forming a lateral PNP transistor.

In addition, the emitter region 30 and the collector region 3
An element isolation insulating film 5 made of a silicon oxide film is formed in order to separate 1 and the base region 9 from each other.

In the emitter region 30, the impurity concentration formed in the vicinity of the surface of the n-type epitaxial layer 4 is 1 × 10 ²⁰ to.
The high-concentration p-type emitter region 7 of about 9 × 10 ²⁰ atom / cm ³ and the impurity concentration of 1 × 10 ^{17 to} 9 × 10 ¹⁷ atom / cm ³ formed in contact with the n ⁺ -type buried layer 2 are formed.
And a low concentration p-type emitter region 15 is provided.

Also in the collector region 31, a high-concentration p-type collector region 8 formed in the vicinity of the surface of the n-type epitaxial layer 4 and having an impurity concentration of about 1 × 10 ^{20 to} 9 × 10 ²⁰ atom / cm ³ . The impurity concentration formed so as to be in contact with the n ⁺ type buried layer 2 is 1 × 10 ^{17 to} 9 × 10 ¹⁷ a
and a low concentration p-type collector region 16 of about tom / cm ³ .

In the emitter region 30, the collector region 31, and the base region 9, the emitter electrode 10, the collector electrode 11, and the base electrode 12 which are made of aluminum or the like are provided, respectively.
However, it is formed in a predetermined shape on the surface of the n-type epitaxial layer 4 with an interlayer oxide film 6 made of a silicon oxide film or the like interposed.

Further, the emitter electrode 10, the collector electrode 11 and the base electrode 12 are covered with an interlayer insulating film 13 made of a silicon oxide film or the like, and a predetermined wiring layer 14 is formed on the interlayer insulating film 13. There is.

In the lateral PNP transistor having the above structure, the low-concentration p-type emitter region 15 and the low-concentration p-type collector region 16 of the emitter region 30 and the collector region 31 are formed in contact with the n ⁺ -type buried layer 2. Has been done.

As a result, the hole trapping cross-sectional area in the collector region 31 of the holes injected from the emitter region 30 to the base region is increased, and the injection efficiency of the emitter current can be improved.

As a result, the current amplification factor of the lateral PNP transistor is increased, and it becomes possible to provide a high performance lateral PNP transistor.

Next, a manufacturing process of the lateral PNP transistor having the above structure will be described with reference to FIGS.

First, referring to FIG. 2, the impurity concentration is 1 ×.
10^Fifteen~ 9 × 10^Fifteenatom / cm ^ThreeAbout p-type silicon
On the surface of the substrate 1, a silicon film having a film thickness of about 50 to 200 nm is formed.
An oxide film 20 is formed.

Next, referring to FIG. 3, the silicon oxide film 2
On 0, a resist film 21 having a predetermined pattern is formed by using a photolithography technique. After that, the silicon oxide film 20 is formed using the resist film 21 as a mask.
Is performed to expose the surface of the p-type silicon substrate 1.

Next, referring to FIG. 4, after removing resist film 21, n-type impurities are implanted into the surface of p-type silicon substrate 1 using silicon oxide film 20 as a mask, and then 1100 ° C. By performing a heat treatment for about 10 minutes, the n ⁺ type buried layer 2 having an impurity concentration of about 1 × 10 ^{19 to} 9 × 10 ¹⁹ atoms / cm ³ is formed.

Next, referring to FIG. 5, the silicon oxide film 2
After removing 0, a silicon oxide film 22 having a film thickness of 500 to 2000 Å is formed again on the p-type silicon substrate 1, and then the silicon oxide film 22 is patterned by using a photolithography technique.

Next, referring to FIG. 6, the silicon oxide film 2
2 is used as a mask, p-type impurities are implanted into the surface of the p-type silicon substrate 1, and then heat treatment is performed at about 1100 ° C. to obtain an impurity concentration of 1 × 10 ^{17 to} 9 × 1.
Forming a 0 ¹⁷ atom / cm ³ of about p-type diffusion layer 3.

Next, referring to FIG. 7, after removing oxide film 22, a film having a thickness of 1.6 to 2.5 μm and an impurity concentration of 1 is formed on the surface of p type semiconductor substrate 1 by an epitaxial growth method.
× to form a ^{10 16 ~9 × 10 16 atom /} cm 3 of about n-type epitaxial layer 4.

Next, referring to FIG. 8, after an oxide film having the same pattern as oxide film 22 shown in FIG. 5 is formed on n-type epitaxial layer 4, this oxide film is used as a mask for n. on the surface of the type epitaxial layer 4, and implanting p-type impurities, then, by performing a heat treatment of about 1100 ° C., with to complete the p-type diffusion layer 3, as shown in FIG. 9, n ⁺ -type Impurities in the buried layer 2 are diffused into the n-type epitaxial layer 4.

Next, referring to FIG. 10, the lateral PNP
Predetermination of n-type epitaxial layer 4 in the transistor formation region
P-type impurities are injected into the region of
By performing the heat treatment, the impurity concentration becomes 1 × 10¹⁷
~ 9 × 10¹⁷atom / cm ^ThreeLow concentration p-type emission
To form a collector region 15 and a low concentration p-type collector region 16
You. The low concentration p-type emitter region 15 and the low concentration p type
The type collector region 16 means p in the CMOS formation region.
The same process as that of forming the well 104 is performed.
You.

Next, referring to FIG. 11, an element isolation insulating film 5 made of a silicon oxide film having a film thickness of 500 to 700 nm is formed in a predetermined region of the n-type epitaxial layer 4 by the LOCOS method.

Then, referring to FIG. 12, a gate electrode 107 having a predetermined shape is formed on the surfaces of n well 103 and p well 104 with a gate oxide film 106 interposed in the CMOS formation region.

Next, referring to FIG. 13, the lateral PNP
In the transistor formation region, after forming a resist film having a predetermined pattern shape, n-type impurities are implanted to obtain an impurity concentration of 1 × 10 ^{21 to} 9 × 10 ²¹ atom /
An n-type base region 9 of about cm ³ is formed. The n-type base region 9 is formed in the n-channel MOS transistor n-type in the CMOS transistor formation region.
It is formed by the same step as the step of forming the ⁺ type source / drain regions 108.

Next, referring to FIG. 14, the lateral PNP
After forming a resist film having a predetermined pattern shape in the transistor formation region, p-type impurities are implanted to obtain an impurity concentration of 1 × 10 ^{20 to} 9 × 10 ²⁰ atom / c.
A high-concentration p-type emitter region 7 and a high-concentration p-type collector region 8 of about m ³ are formed. The high-concentration p-type emitter region 7 and the high-concentration p-type collector region 8 are p ⁺ channel type MO in the CMOS type transistor forming region.
It is formed by the same step as the step of forming the p ⁺ type source / drain region 109 of the S transistor.

Then, on the n-type epitaxial layer 4,
An interlayer oxide film 6 made of a silicon oxide film or the like is deposited, and contact holes communicating with the emitter region 30, the collector region 31 and the base region 9 are opened by using a photolithography technique and a fine processing technique.

Next, Al--Si or Al--Si--Cu
Is deposited by a sputtering method of 500 to 1000 nm, and predetermined patterning is performed to form an emitter electrode 10, a collector electrode 11 and a base electrode 12.

After that, an interlayer insulating film 13 made of a silicon oxide film or the like is deposited on the emitter electrode 10, the collector electrode 11 and the base electrode 12, and then the interlayer insulating film 13 is formed.
By forming a predetermined wiring layer 14 on the top of FIG.
The lateral PNP transistor shown in is completed.

In the manufacturing process of the lateral PNP transistor described above, the low-concentration p-type emitter region 15 and the low-concentration p-type collector region 16 forming the emitter region 30 and the collector region 31 are formed by forming the element isolation oxide film 5. Has also been formed in a separate manufacturing process before.

Therefore, the effective base width formed below the element isolation oxide film 5 can be formed as designed without being affected by the formation position of the element isolation oxide film 5.

As a result, since the effective base width can be formed to a predetermined width as described above, it becomes possible to obtain a desired current amplification factor and to provide a high performance lateral PNP transistor. .

Further, the low-concentration p-type emitter region 15 and the low-concentration p-type collector region 16 can be manufactured in the same process as the p-well forming process of the CMOS transistor forming region, as described with reference to FIG. Therefore, the low-concentration p-type emitter region 15 and the low-concentration p-type collector region 16 can be formed without increasing the number of manufacturing steps as compared with the conventional manufacturing process.

Therefore, it is possible to avoid an increase in cost due to an increase in the number of manufacturing steps. (Embodiment 2) Next, referring to FIG.
This will be described with reference to FIG.

Lateral PNP in Embodiment 2
The transistor is the lateral PNP in the first embodiment.
When compared with a transistor, the emitter region is composed of only the high-concentration p-type emitter region 7, and the collector region 31
The low-concentration p-type collector region 16 is formed only in.

By using such a configuration as well,
As in the first embodiment, the hole trapping cross section can be increased, so that the injection efficiency of the emitter current can be improved, and the same operational effect as the lateral PNP transistor of the first embodiment can be obtained. it can.

In the manufacturing process, the first embodiment
In the step shown in FIG. 11, the structure of the lateral PNP transistor in the present embodiment can be realized by providing the resist film so as to form only the low concentration p-type collector region 16.

(Third Embodiment) Next, a third embodiment according to the present invention will be described with reference to FIG.

Lateral PNP in the third embodiment
In the structure of the transistor, the low-concentration p-type emitter region 15 is formed only in the emitter region 30, and the collector region is constituted only by the high-concentration p-type collector region 8.

Also in this structure, as in the case of the first embodiment, the hole trapping cross-sectional area becomes large, and the injection efficiency of the emitter current can be improved.

Further, in the structure of the third embodiment, as in the second embodiment, in the step shown in FIG. 11, the resist film is formed so that only the low concentration p-type emitter region 15 is formed. The structure of the lateral PNP transistor of the third embodiment can be realized.

(Fourth Embodiment) Next, a fourth embodiment according to the present invention will be described with reference to FIG.

Lateral PNP in Embodiment 4
Compared with the lateral PNP transistor of the first embodiment, the structure of the transistor is such that the low-concentration p-type collector region 16 has a density of 0.
It is formed so as to be inside about 5 μm to 1.0 μm.

By using such a structure, the punch-through breakdown voltage between the p-type diffusion layer 3 and the low-concentration p-type collector region 16 is improved, and the current amplification factor can be increased. As a result, it is possible to provide a high performance lateral PNP transistor.

The structure according to the fourth embodiment is as follows.
Even if it is applied to the lateral PNP transistor shown in the above-described second and third embodiments, the same effect can be obtained.

As described above, the embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[Brief description of drawings]

FIG. 1 is a cross-sectional structure diagram of a lateral PNP transistor according to a first embodiment.

FIG. 2 is a sectional view of a first manufacturing process of the lateral PNP transistor according to the first embodiment.

FIG. 3 is a sectional view of a second manufacturing process of the lateral PNP transistor according to the first embodiment.

FIG. 4 is a sectional view of a third manufacturing process of the lateral PNP transistor according to the first embodiment.

FIG. 5 is a sectional view of a fourth manufacturing process of the lateral PNP transistor according to the first embodiment.

FIG. 6 is a sectional view of a fifth manufacturing process for the lateral PNP transistor according to the first embodiment.

FIG. 7 is a sectional view of a sixth manufacturing process for the lateral PNP transistor according to the first embodiment.

FIG. 8 is a sectional view of the lateral PNP transistor according to the first embodiment in a seventh manufacturing process.

FIG. 9 is an eighth manufacturing step cross-sectional view of the lateral PNP transistor in the first embodiment.

FIG. 10 is a sectional view of the lateral PNP transistor according to the first embodiment in a ninth manufacturing step.

FIG. 11 is a cross-sectional view of the lateral PNP transistor of the first embodiment during the tenth manufacturing step.

FIG. 12 is an eleventh manufacturing step cross-sectional view of the lateral PNP transistor in the first embodiment.

FIG. 13 is a sectional view of a twelfth manufacturing process of the lateral PNP transistor according to the first embodiment.

FIG. 14 is a cross-sectional view of the lateral PNP transistor of the first embodiment during the thirteenth manufacturing step.

FIG. 15 is a cross-sectional structure diagram of a lateral PNP transistor according to the second embodiment.

FIG. 16 is a sectional structural view of a lateral PNP transistor according to the third embodiment.

FIG. 17 is a sectional structural view of a lateral PNP transistor according to the fourth embodiment.

FIG. 18 is a plan view of a lateral PNP transistor according to the prior art.

FIG. 19 is a sectional view taken along line XX in FIG.

FIG. 20 is a sectional view of a first manufacturing process of a lateral PNP transistor according to the related art.

FIG. 21 is a sectional view of the second manufacturing process of the lateral PNP transistor based on the conventional technique.

FIG. 22 is a sectional view of the third manufacturing process of the lateral PNP transistor based on the conventional technique.

FIG. 23 is a cross-sectional view of the fourth manufacturing process of the lateral PNP transistor based on the conventional technique.

FIG. 24 is a sectional view of a fifth manufacturing process of the lateral PNP transistor based on the conventional technique.

FIG. 25 is a sectional view of a sixth manufacturing process for a lateral PNP transistor according to the related art.

FIG. 26 is a sectional view of a seventh manufacturing process for a lateral PNP transistor according to the related art.

FIG. 27 is a sectional view of an eighth manufacturing process of the lateral PNP transistor according to the related art.

FIG. 28 is a cross-sectional view of a ninth manufacturing process of a lateral PNP transistor according to the related art.

FIG. 29 is a cross-sectional view of a tenth manufacturing process of a lateral PNP transistor based on the conventional technique.

FIG. 30 is a cross-sectional view showing a problem of a lateral PNP transistor based on a conventional technique.

FIG. 31 is an equivalent circuit diagram of a lateral PNP transistor in the related art.

[Explanation of symbols]

1 p-type silicon substrate, 2 n ⁺ type buried layer, 3 p-type diffusion layer, 4 n-type epitaxial layer, 5 element isolation oxide film, 6 interlayer oxide film, 7 high-concentration p-type emitter region, 8
High concentration p-type collector region, 9 n-type base region, 10
Emitter electrode, 11 collector electrode, 12 base electrode, 13 interlayer insulating film, 14 wiring layer, 15 low concentration p
Type emitter region, 16 low concentration p type collector region, 30
Emitter region, 31 Collector region. The same reference numerals in the drawings denote the same or corresponding parts.

Claims (5)

[Claims] 1. A p-type semiconductor substrate, an n-type epitaxial layer formed on the p-type semiconductor substrate, and an n-type buried layer formed so as to straddle the p-type semiconductor substrate and the n-type epitaxial layer. A buried layer, a p-type diffusion layer formed between the p-type semiconductor substrate and the n-type epitaxial layer and surrounding the n-type buried layer, and surrounded by the p-type diffusion layer. And a lateral PNP transistor having a p-type emitter region, a p-type collector region and an n-type base region, wherein the p-type emitter region, the p-type collector region and the n-type base region are A p-type emitter region and / or a p-type collector region, and at least one of the p-type emitter region and the p-type collector region has an n-type buried region. A semiconductor device provided in contact with a layer. 2. The p-type emitter region and the p-type collector region have a p-type high-concentration impurity region formed near the surface of the n-type epitaxial layer, and a p-type low-concentration region that is in contact with the n-type buried layer. The semiconductor device according to claim 1, further comprising an impurity region. 3. The semiconductor device according to claim 1, wherein in the p-type collector region, the p-type low concentration impurity region is provided inside the p-type high concentration impurity region. 4. A first region in which a lateral PNP transistor is formed and a CMOS on the same p-type semiconductor substrate.
A method of manufacturing a semiconductor device, comprising: a second region in which a transistor is formed, the first region and the second region of a main surface of the p-type semiconductor substrate.
Forming an n-type impurity diffusion layer in the region; forming a p-type first impurity diffusion layer surrounding the n-type impurity diffusion layer formed in the first region; Forming an n-type epitaxial layer on the main surface of the semiconductor substrate; introducing a p-type impurity into the n-type epitaxial layer located above the p-type first impurity diffusion layer, A step of completing a p-type diffusion layer together with a first impurity diffusion layer; and heat-treating the p-type semiconductor substrate and the n-type epitaxial layer, and the n-type impurity diffusion layer, the first region and the second region. A step of completing an n-type buried layer in the region so as to extend over the p-type semiconductor substrate and the n-type epitaxial layer; Shape p-type well P-type impurities are introduced into at least one of the emitter forming region and the collector forming region of the first region by the same step as the p-type impurity introducing step for reaching the n-type buried layer. A low-concentration type impurity region, and a LOCOS method on the surface of the n-type epitaxial layer in the first region so as to separate the emitter forming region, the collector forming region, and the base forming region from each other, Forming an element isolation insulating film, and forming an n-channel MOS transistor in the second region.
By the same process as the n-type impurity introduction process for forming the source / drain regions of the type,
forming an n-type base region, and p-type of the p-channel type MOS transistor in the second region.
Forming a p-type high-concentration impurity region on the surface of the emitter forming region and the collector forming region by the same process as the p-type impurity introducing process for forming the p-type source / drain region. , Method for manufacturing semiconductor device. 5. In the step of forming a p-type low-concentration impurity region in the p-type collector formation region, the side surface of the p-type low-concentration impurity region is more than the side surface of the p-type high-concentration impurity region. The method for manufacturing a semiconductor device according to claim 4, wherein the method is formed so as to be inside.