JPH07235837A - Frequency doubler circuit - Google Patents

Abstract

PURPOSE:To provide the multiplier circuit at a low cost in which the spurious performance is maintained and improved. CONSTITUTION:A lag/lead phase shifter is adopted for a phase shifter 1 having a transfer function of (1+sT2)/(1+sT2) [where T1 and T2 are time constants] to suppress an attenuation for a high frequency to be a prescribed level, a phase shift shifting a received original signal accurately by 90 deg. is obtained and a multiplier 2 multiplies the original signal and a signal obtained by phase- shitting the original signal by 90 deg. to obtain a doubled output with a desired spurious performance regardless of simple circuit configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a SECAM type VT.
The present invention relates to a frequency doubling circuit suitable for use in an R signal processing circuit and the like.

[0002]

2. Description of the Related Art In a chroma signal processing circuit of a SECAM system VTR, the frequency of a chroma signal reproduced from a tape is 4
The signal is multiplied, converted to high frequency, and output to a TV or the like. If the spurious component generated in the frequency multiplication circuit is large, it interferes with the luminance signal when the chroma signal and the luminance signal are added and combined. Therefore, a multiplier circuit with less spurious components is required. Actually, the 4 × circuit is a 2 × circuit.
Since they are connected in stages, the spurious in each doubler circuit becomes a problem.

In order to reduce spurious as much as possible, conventionally, a doubler circuit as shown in FIG. 18 has been adopted. Input in
The original signal input to is input to the integrator 181, and the integrated output and the original signal are multiplied by the multiplier 182. The multiplied signal is a doubled frequency signal with a duty of 50%, and is output to the output out as a half-wave symmetrical and odd-symmetrical waveform. Therefore, the multiplied signal 2 × of the input signal fin
odd harmonics of fin N × 2 × fin (where N is 3
Only the above odd numbers appear in the output spectrum, and the even harmonics M × fin (M is an even number) are not generated.

The integrator 181 is realized by a circuit as shown in FIG. A capacitor C12 is connected between the output of the gm amplifier (gm: transconductance) A1 having positive and negative input terminals and the ground, and the output is fed back to the negative input of the gm amplifier A1 via the buffer B5. The positive input terminal is used as the integral input, and the output of the buffer B5 is used as the integral output. The frequency characteristics of this integrator 181 are shown in FIGS. The -3 dB frequency of the integrating circuit was set to 100 KHz. As can be seen from FIG. 22, a phase shift of about 90 degrees occurs at 1 MHz. When the original signal is sin (ωt), the integrator output is cos (ω
t), and the result of multiplication of these is sin (ωt) × cos (ωt) = (sin (2ωt)) / 2 (1) according to the double angle formula. This state is shown in FIG. The original signal is (a) and the phase-shifted output signal of the integrator 181 becomes (b). The result of multiplication is (c), and the frequency is doubled. Since the actual multiplication operation is performed as a limiter, FIG.
Each waveform of 0 becomes close to a rectangular wave, and the odd harmonics as described above appear, but the even harmonics do not occur.

As can be seen from the phase characteristic of FIG. 22,
The amount of phase shift at 1 MHz set in the description is 85 degrees, not exactly 90 degrees. For this reason, an original signal component or an intermodulation component that is an odd multiple of the original signal appears in the multiplying power,
The disadvantage is that unwanted spectra or spurs occur at those frequencies. In addition, as shown in FIG. 21, the integrated output signal is −20d at the frequency where the phase is shifted by 90 degrees.
It is attenuated near B, and a separate amplifier circuit is required. In addition, since the integrating circuit itself uses a large number of transistors, the number of elements is large, which has the disadvantage of high cost. Figure 1
Although the circuit of 8 has been described as a single input / single output, in practice, a differential input / differential output configuration is often adopted, and in this case, two integrating circuits are required, which further increases the cost. .

Further, in the case of differential signal processing, the output DC offset of the integrator becomes a problem. When integrators are inserted in the differential signal paths, the offsets generated in the integrators are different, so when input to the multiplier, the cross timing of the differential signals changes, and the differential signals themselves have even-order distortion. . Due to this effect, even harmonics are generated in the calculated power, and the spurious performance is deteriorated. There is an example in which an LPF or the like is inserted in the feedback path of FIG. 19 so that a large gain can be obtained at a desired frequency and the amount of phase shift is close to 90 degrees, to solve these problems. In this case, the amplitude characteristic rises on the low frequency side, which is equivalent to an increase in Q, and it takes a long time from the time when the input signal arrives until the output DC / AC signal operates stably. . During that time, the doubled frequency component is not output or has a waveform with a lot of distortion. Therefore, when a signal with a signal existing period and a signal with a horizontal blanking period that does not exist, such as a SECAM chroma signal, is doubled, Inconvenient results.

[0007]

In the above-mentioned conventional doubler circuit, there is a problem that spurious is generated, and the circuit scale becomes large and the cost becomes high. Two
If the multiplier circuit has a differential input / differential output configuration, spurious performance is degraded. As a countermeasure against this, LPF on the return path
Etc., gain is obtained at the desired frequency, and the amount of phase shift is 9
There are some that are close to 0 degrees. In this case, the amplitude characteristic rises on the low frequency side, which is equivalent to an increase in Q, and DC / A of the output from the time when the input signal arrives.
It takes a long time until the C signal operates stably, and during that time, the doubled frequency component is not output or has a waveform with a lot of distortion. If a signal with a blanking period is multiplied by 2, the result is very inconvenient.

It is an object of the present invention to provide a low cost doubler circuit while maintaining and improving the spurious performance of the doubler circuit.

[0009]

The doubler circuit of the present invention is (1 + ST2) / (1 + ST1) [where T1,
T2 is a time constant] and a plurality of circuits having a transfer function are connected, and a phase shifter for shifting the input original signal and the output signal of the original signal and the phase shifter are multiplied to obtain a doubled signal. And a multiplier for obtaining an output.

[0010]

[Function] By the above means, (1 + ST2) / (1+
ST1) [where T1 and T2 are time constants] If a lag lead type phase shifter is used as a phase shifter having a transfer function,
The amount of attenuation in the high range can be suppressed to a certain level,
If the 45-degree lag lead phase shifter is subordinated to two stages, the input original signal can be accurately obtained by 90 degrees, and the original signal and the original signal can be multiplied by 90 degrees. By doing so, it is possible to obtain a doubled output having a desired spurious performance with a simple circuit configuration.

Further, even in the case of the simple lag and subtraction circuit, it is possible to operate at the phase shift frequency of 45 degrees, so that the phase shifted signal level can be suppressed by the attenuation of about -3 dB.
Even in this case, it is possible to accurately shift the phase by 90 degrees, and spurious performance equal to or higher than that of the conventional case can be obtained even in consideration of variations in performance. In terms of cost, since it can be configured with passive elements, the number of transistors is drastically reduced and the cost is reduced. Differential input
In the case of output, change the passive element configuration to reduce the element scale to 2
It is possible to make it less than double.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining one embodiment of the present invention. The original signal is input from the input in to the lag lead type 90 degree phase shifter 1, and the phase shift output and the original signal are multiplied by the multiplier 2 and output to the output out. The waveform of the multiplication operation is as shown in FIG. 20 described in the conventional example, and the basic operation is unchanged. FIG. 2 shows a configuration example of this lag lead phase shifter 1. The lag lead type phase shifters 1a and 1b having a phase shift amount of 45 degrees are connected subordinately.
The lag lead phase shifter 1 referred to here is one in which the transfer function has the form of (1 + ST2) / (1 + ST1) (2). As an example of this, the circuit of FIG. 3 is used. The circuit of FIG. 3 corresponds to the 45 degree phase shifter of FIG. 2, and T1 = (R1 + R2) C1 and T2 = R2 of the equation (2).
Given by C1. R1 = 20K, R2 = 4K, C1 =
The frequency characteristics at 16p are as shown in FIGS.

In the lag lead phase shifter, the attenuation amount in the high range is R
It becomes 2 / (R1 + R2) and it does not decay to infinity. In the case of this example, it is about -15 dB at 1 MHz, and the gain can be increased by about 5 dB as compared with the conventional case. The amount of phase shift at this frequency is approximately 90 degrees, so that it is possible to suppress the leakage of the input signal to the output and the generation of the intermodulation component of an odd multiple, which have been conventionally problems. As shown in FIG. 3, since it can be realized with a very simple structure, cost merit is large. In the case of a single input, it is the simplest to realize with the configuration shown in FIG. 3, but in the case of a differential input, there is another method. This is shown in FIG. The circuit of FIG. 6 has a differential input,
The lag lead phase shifter is connected in cascade. The circuit of resistors R3 to R6 is the preceding lag lead phase shifter, and resistor R7
The circuit from R10 to R10 is the latter phase shifter. Buffers B1 and B2 are provided between the front and rear phase shifters, and buffers B3 and B4 are also provided at the output. It is preferable to use an emitter follower for the buffer circuit. In the circuit of FIG. 3, the capacitance C1 is connected to the ground, but in the case of a differential input, a virtual ground point is formed, so that the capacitance can be connected between the positive and negative signal phase shifters. The capacitance value in this connection may be half that in the case of FIG. Especially in the case of an IC, it is desirable that the capacitance area is small, so that the chip area reduction effect by this connection is large.

As is clear from the circuit of FIG. 6, the element that generates the DC offset is only the buffer, and the input / output D
The C offset is very small between the differential signals. Even if the circuit as shown in FIG. 6 is used, if the signal attenuation is large,
As described above, the amplifier 3 that amplifies the output of the phase shifter 2 is provided. In the case of differential signal processing, the amplifier 3 may be a differential amplifier having a simple structure as shown in FIG. 8 and composed of transistors Q1 and Q2, resistors R13 and R14, and a current source I1.

There are various conceivable lag lead circuits defined to have the transfer function of equation (1). Regarding another specific example of the lag lead circuit having the transfer function of Expression (2),
This will be described with reference to FIGS. 9 and 10. In the case of the circuit of FIG. 9, contrary to FIG. 6, the gain is small in the low range and large in the high range, but the transfer function is the same as that of the equation (1) and leads to a phase shift.
Similarly, the 45-degree phase shifter may be connected in two stages. Figure 1
The 0 circuit has the same gain tendency as in FIG. Since it suffices that the phase can be shifted by 90 degrees regardless of the lead / lag phase, in either case, the cost can be reduced while maintaining / improving the performance as described above.

FIG. 11 is a circuit configuration diagram for explaining another embodiment of the present invention. The original signal is input from the input in to the phase shifter 11, and the phase shifter 11 and the original signal are input to the subtractor 12. The subtraction output of the subtracter 12 and the phase shift output are multiplied, and a doubled signal is obtained from the output of the multiplier 13 at the output out. One example of the phase shifter 11 is shown in FIGS. FIG. 13 shows a simple lag type phase shifter, which is a first-order LPF.
Format. In this case, the delay phase is 45 degrees at the -3 dB frequency. FIG. 14 shows a simple lead type phase shifter, which similarly has a lead phase of 45 degrees at a -3 dB frequency. The phase shift operation of these phase shifters will be described with reference to the vector diagram 12. It is assumed that the phase shifter shown in FIG. 14 is used. When the original signal is vector a, the phase-shifted signal is vector b. When a and b are subtracted, a vector (ab) is obtained, and b and ab are at a right angle. Even if the phase shift amount of the phase shifter deviates from 45 degrees due to variations or the like, the miracle of b moves on the circumference, so a and b
The triangle formed by and a-b is inscribed in a circle, and b and a-
The right angle relationship of b does not change. Circuit of FIG. 14 (R18 = 10
K, C11 = 16p) and the output of the subtractor 12 are shown in FIGS.
7 (solid line is HPF output, dotted line is subtractor output). As can be seen from FIG. 17, the phase difference between the two signals is constant at 90 degrees regardless of frequency. Since the 45 degree phase was selected to be 1 MHz, the amplitude of the two signals is -3.
Only dB is attenuated.

In the circuit of FIG. 11, the subtractor is shown as a block independently, but in reality, the multiplier 13 is often a double-balanced mixer with a differential input, and the subtractor 12 is apparently built in the multiplier. This can be done, so this will be explained. The double balance mixer has a circuit configuration as shown in FIG. The transistors Q3 and Q4 are of the differential input type, and the upper transistors Q5 to Q8 are also of the differential input type. For example, if the phase shift signal is input to the upper differential circuit, the original signal is input to the base of the transistor Q3, and the phase shift signal is input to the base of the transistor Q4, the transistors Q3 and Q4 operate by the differential input, so subtraction is realized. Come on.

In this embodiment, since the subtracter can be omitted, only the circuit and the mixer shown in FIG. 14 are necessary in terms of the circuit. Since it is possible to perform a 90-degree phase shift accurately without a subtracter, the performance is equal to or higher than that of the conventional circuit, and in terms of the element scale, one when the HPF is a single signal processing,
Since only two are required for differential signal processing, there are very few cost advantages.

The LPF type phase shifter shown in FIG. 13 has the same effect. However, since the circuit of FIG. 14 is an HPF, it also has the advantage of being able to cancel the DC offset from the previous stage.

[0020]

As described above, according to the doubler circuit of the present invention, it is possible to provide a doubler circuit which has spurious performance and is inexpensive in cost.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for explaining an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an embodiment of the phase shifter of FIG.

3 is a circuit diagram showing a specific example of the phase shifter of FIG.

FIG. 4 is a characteristic diagram showing the relationship between frequency and gain in FIG.

FIG. 5 is a characteristic diagram showing the relationship between frequency and phase in FIG.

FIG. 6 is a circuit diagram showing a configuration when the differential signal processing of FIG. 2 is performed.

7 is a circuit diagram showing a state when an amplifier is inserted in the configuration of FIG.

8 is a circuit diagram showing a specific example of the amplifier shown in FIG.

9 is a circuit diagram showing another specific example of the phase shifter of FIG.

FIG. 10 is a circuit diagram showing another specific example of the phase shifter of FIG.

FIG. 11 is a circuit diagram for explaining another embodiment of the present invention.

FIG. 12 is a vector diagram for explaining the operation of FIG. 11.

13 is a circuit diagram showing a specific example of the phase shifter of FIG.

14 is a circuit diagram showing another specific example of the phase shifter of FIG.

FIG. 15 is a circuit diagram for explaining a specific example of the mixer in FIG.

16 is a characteristic diagram showing the relationship between frequency and gain in FIG.

FIG. 17 is a characteristic diagram showing the relationship between frequency and phase in FIG.

FIG. 18 is a circuit diagram for explaining a conventional doubler circuit.

FIG. 19 is a circuit diagram showing a specific example of the integrator in FIG.

20 is a waveform diagram showing the operation waveforms of FIG.

21 is a characteristic diagram showing the relationship between frequency and gain of the integrator in FIG.

22 is a characteristic diagram showing the relationship between frequency and phase of the integrator in FIG.

[Explanation of symbols]

1, 11 ... Phase shifter, 2, 13 ... Multiplier, 3, Amplifier, 12 ... Subtractor

Claims (9)

[Claims] 1. A phase shifter that shifts the phase of an input original signal by connecting a plurality of circuits having a transfer function of (1 + ST2) / (1 + ST1) [where T1 and T2 are time constants], And a signal for multiplying the output signal of the phase shifter to obtain a doubled output.
Multiplier circuit. 2. A doubling circuit according to claim 1, further comprising an amplifier for amplifying the output of the phase shifter, wherein the output of the amplifier and the original signal are multiplied. 3. A series resistor comprising two series-connected resistance elements and one capacitor, wherein a signal is input from one terminal of the series resistor and a capacitor is connected to the other terminal to ground, 2. The doubling circuit according to claim 1, wherein the transfer function is constructed so as to obtain the output signal from the point. 4. A doubling circuit according to claim 1, wherein the phase shift amount of the phase shifter is 90 degrees. 5. The doubler circuit according to claim 3, wherein a phase shifter having a phase shift amount of 45 degrees is used, and the phase shifters are cascade-connected to obtain a phase shift amount of 90 degrees. 6. A doubler circuit according to claim 1, further comprising a phase shifter, a subtracter and a multiplier, subtracting the phase shift signal and the original signal, and multiplying the subtraction signal and the phase shift signal. . 7. A differential input type multiplier, wherein the phase shift signal and the original signal are connected to the input of the multiplier and subtracted by the differential input stage. The described doubler circuit. 8. The doubler circuit according to claim 6 or 7, wherein the phase shifter is configured by a first-order HPF or a first-order LPF. 9. The doubling circuit according to claim 6, wherein the phase shift amount of the phase shifter is 45 degrees.