JPH0831772B2 - Phase synthesis / branch circuit - Google Patents

Phase synthesis / branch circuit

Info

Publication number
JPH0831772B2
JPH0831772B2 JP6619490A JP6619490A JPH0831772B2 JP H0831772 B2 JPH0831772 B2 JP H0831772B2 JP 6619490 A JP6619490 A JP 6619490A JP 6619490 A JP6619490 A JP 6619490A JP H0831772 B2 JPH0831772 B2 JP H0831772B2
Authority
JP
Japan
Prior art keywords
phase
collector
capacitance element
transistor
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6619490A
Other languages
Japanese (ja)
Other versions
JPH03267807A (en
Inventor
伸明 今井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Docomo Inc
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
NTT Mobile Communications Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, NTT Mobile Communications Networks Inc filed Critical Nippon Telegraph and Telephone Corp
Priority to JP6619490A priority Critical patent/JPH0831772B2/en
Publication of JPH03267807A publication Critical patent/JPH03267807A/en
Publication of JPH0831772B2 publication Critical patent/JPH0831772B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は、一定の位相差で2つの信号を合成し、又
は1つの信号を一定の位相差で分岐する位相合成分岐回
路に関し、特に高周波特性を改善しようとするものであ
る。
TECHNICAL FIELD The present invention relates to a phase combining / branching circuit for combining two signals with a constant phase difference or branching one signal with a constant phase difference, and particularly to a high frequency It is intended to improve the characteristics.

「従来の技術」 第7図に従来の90度位相分岐回路を示す。これは特願
昭61-163676号で提案したものである。入力端子11より
の入力信号は第1、第2の移相器12,13へそれぞれ供給
され、これら第1、第2の移相器12,13の各出力端子14,
15から90度の位相差の信号が分岐出力される。第1、第
2の移相器12,13はそれぞれトランジスタQ1,Q2の各コ
レクタがそれぞれ抵抗器16,17を通じて電源18の正側に
接続されて交流的に接地され、各エミッタがそれぞれ抵
抗器19,21を通じて電源18の負側に接続されて交流的に
接地され、各ベースはそれぞれ入力端子11に接続される
と共に、それぞれバイアス用抵抗器22,23を通じて電源1
8の正側に接続され、更にバイアス用抵抗器24,25をそれ
ぞれ通じて接地されている。トランジスタQ1のコレクタ
及びエミッタ間に抵抗素子26および容量素子27の直列回
路が接続され、抵抗素子26及び容量素子27の接続点は出
力端子14に接続される。トランジスタQ2のコレクタ及び
エミッタ間に抵抗素子28及び容量素子29の直列回路が接
続され、抵抗素子28及び容量素子29の接続点は出力端子
15に接続される。
"Prior Art" Fig. 7 shows a conventional 90-degree phase branch circuit. This was proposed in Japanese Patent Application No. 61-163676. The input signals from the input terminal 11 are supplied to the first and second phase shifters 12 and 13, respectively, and the output terminals 14 and 13 of the first and second phase shifters 12 and 13 are respectively supplied.
A signal with a phase difference of 15 to 90 degrees is branched and output. In the first and second phase shifters 12 and 13, the collectors of the transistors Q 1 and Q 2 are connected to the positive side of the power source 18 through resistors 16 and 17, respectively, and are grounded in an alternating current manner, and the emitters are respectively It is connected to the negative side of the power supply 18 through resistors 19 and 21 and is grounded in an alternating current manner. Each base is connected to the input terminal 11 and the power supply 1 is connected through the bias resistors 22 and 23, respectively.
It is connected to the positive side of 8, and is further grounded through biasing resistors 24 and 25, respectively. A series circuit of the resistance element 26 and the capacitance element 27 is connected between the collector and the emitter of the transistor Q 1 , and the connection point of the resistance element 26 and the capacitance element 27 is connected to the output terminal 14. A series circuit of the resistance element 28 and the capacitance element 29 is connected between the collector and the emitter of the transistor Q 2 , and the connection point of the resistance element 28 and the capacitance element 29 is the output terminal.
Connected to 15.

抵抗器16,19,17,21の各抵抗値をそれぞれR7,R8
R9,R10、抵抗素子26,28の各抵抗値をそれぞれR1,R2
容量素子27,29の各容量をそれぞれC1,C2とし、入力端
子11の入力信号の角周波数をωとし、R7=R8,R9=R10
の時は、出力端子14,15の各出力信号の位相Θ1,Θ
2は、次式で表わされる。
Set the resistances of resistors 16, 19, 17, and 21 to R 7 , R 8 , and
The resistance values of R 9 and R 10 and the resistance elements 26 and 28 are set to R 1 , R 2 , and
Let C 1 and C 2 be the capacitances of the capacitive elements 27 and 29, respectively, and let the angular frequency of the input signal at the input terminal 11 be ω, and let R 7 = R 8 and R 9 = R 10
, The phase of each output signal from output terminals 14 and 15 is Θ 1 and Θ
2 is expressed by the following equation.

Θ1=2tan-1(1/ωR1C1)(1) Θ2=2tan-1(1/ωR2C2)(2) 第8図は、上式で表わされる出力信号の位相−周波数
特性を示したもので、動作周波数帯で、Θ1とΘ2の差が
90度になるように、R1,C1およびR2,C2を設定すれば、
非常に広帯域にわたって90度の位相差が得られる。第9
図は、この時の出力端子14,15の両出力の位相差の周波
数特性を示したものである。
Θ 1 = 2tan -1 (1 / ωR 1 C 1 ) (1) Θ 2 = 2tan -1 (1 / ωR 2 C 2 ) (2) Fig. 8 shows the phase-frequency of the output signal expressed by the above equation. It shows the characteristics, the difference between Θ 1 and Θ 2 in the operating frequency band
If R 1 , C 1 and R 2 , C 2 are set to be 90 degrees,
A 90 degree phase difference can be obtained over a very wide band. Ninth
The figure shows the frequency characteristic of the phase difference between both outputs of the output terminals 14 and 15 at this time.

「発明が解決しようとする課題」 ところが、帯7図に示した従来の構成の回路では、ト
ランジスタQ1およびQ2のコレクタに付随する容量(コレ
クタ−基板間容量)により、高周波帯で振幅周波数特性
が劣化するという欠点があった。第10図は、第7図の基
本回路部である、トランジスタQ1、抵抗器16,19,22,24
からなるシングルエンド形の増幅器について(R7=R8の
場合)トランジスタQ1のコレクタ−基板間容量CSUBをパ
ラメータとして、コレクタ側への挿入損失を、シミュレ
ーション計算により求めた例である。コレクタ−基板間
容量CSUBが大きくなる程、コレクタ側の振幅周波数特性
は劣化しており、コレクタ−基板間容量CSUBが、周波数
特性に影響している様子がわかる。
"Problem to be solved by the invention" However, in the circuit having the conventional configuration shown in FIG. 7, the amplitude (frequency between the collector and the substrate) associated with the collectors of the transistors Q 1 and Q 2 causes the amplitude frequency in the high frequency band. There is a drawback that the characteristics deteriorate. FIG. 10 shows the basic circuit section of FIG. 7, including transistor Q 1 and resistors 16, 19, 22, 24.
This is an example in which the insertion loss on the collector side of the single-ended amplifier consisting of (in the case of R7 = R8) was obtained by simulation calculation with the collector-substrate capacitance C SUB of the transistor Q 1 as a parameter. As the collector-substrate capacitance C SUB increases, the amplitude frequency characteristic on the collector side deteriorates, and it can be seen that the collector-substrate capacitance C SUB affects the frequency characteristic.

この発明の目的は、上述した高周波帯における周波数
特性の劣化を抑え、高周波帯で広帯域な位相合成分岐回
路を提供することにある。
An object of the present invention is to provide a phase synthesizing / branching circuit that suppresses the above-described deterioration of frequency characteristics in the high frequency band and has a wide band in the high frequency band.

「課題を解決するための手段」 この発明は、前述した位相合成分岐回路において第
1、第2の移相回路の少くとも一方のトランジスタのコ
レクタとエミッタの間、又はFETのドレインとソースの
間に第2の容量素子を接続し、コレクタ又はドレインと
基板間の容量を、エミッタ又はソース側の逆相信号によ
り補償することにより、高周波帯における周波数特性の
劣化を抑えることを特徴とする。
"Means for Solving the Problem" The present invention relates to the above-described phase-combining branch circuit between the collector and the emitter of at least one of the first and second phase shift circuits, or between the drain and the source of the FET. Is connected to the second capacitor element, and the capacitance between the collector or drain and the substrate is compensated for by the negative phase signal on the emitter or source side, thereby suppressing deterioration of frequency characteristics in the high frequency band.

「実施例」 第1図は、この発明の実施例を示し、第7図と対応す
る部分に同一符号を付けてある。この実施例ではトラン
ジスタQ1,Q2の各コレクタとエミッタ間に第2の容量素
子31,32をそれぞれ接続する。この回路でR7=R8,およ
びR9=R10とすれば、トランジスタQ1,Q2のコレクタと
エミッタには、各々、等振幅で逆位相の信号が取り出さ
れる。従って、第2の容量素子31,32によってトランジ
スタQ1,Q2の各コレクタ−基板間容量CSUBを補償するこ
とができ、これによって高周波帯における振幅周波数特
性の劣化を抑えることができる。
[Embodiment] FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 7 are designated by the same reference numerals. In this embodiment, second capacitive elements 31 and 32 are connected between the collectors and emitters of the transistors Q 1 and Q 2 , respectively. If R 7 = R 8 and R 9 = R 10 in this circuit, signals of equal amplitude and opposite phase are extracted from the collectors and emitters of the transistors Q 1 and Q 2 , respectively. Therefore, the collector-substrate capacitance C SUB of the transistors Q 1 and Q 2 can be compensated by the second capacitance elements 31 and 32, and thus the deterioration of the amplitude frequency characteristic in the high frequency band can be suppressed.

第2図及び第3図は、容量補償による周波数特性の改
善効果を、実際にシミュレーション計算によって明らか
にしたもので、第2図は、出力端子14の振幅周波数特性
を容量素子31で補償する前と後とについて示し、第3図
は出力端子15の振幅周波数特性を容量素子32で補償する
前と後とについて示し、第4図は、出力端子14,15の両
出力の位相差を、同様に、容量素子で補償する前と後と
について示したものである。設計の中心周波数は500MHz
である。第2図、第3図から、第2の容量素子で補償す
ることにより、出力の振幅周波数特性が高周波帯で改善
されていることがわかる。また第2図の方が改善効果が
大で第3図は第2図より改善はわずかである。従って少
くとも第1の移相器12について補償すればよい。また、
第4図から、出力の位相差が90度±2度となる周波数帯
域は、350MHzから800MHzまであり、1オクターブ以上の
広帯域な特性が得られていることがわかる。位相差の広
帯域性についても、補償用の第2の容量素子を入れるこ
とによって、若干の改善効果がみられる。
2 and 3 show the improvement effect of the frequency characteristic by the capacitance compensation, which is actually clarified by the simulation calculation. In FIG. 2, before the amplitude frequency characteristic of the output terminal 14 is compensated by the capacitive element 31. Fig. 3 shows before and after compensating the amplitude frequency characteristic of the output terminal 15 with the capacitive element 32, and Fig. 4 shows the phase difference between both outputs of the output terminals 14 and 15 in the same manner. 2 shows before and after compensation by the capacitive element. Center frequency of design is 500MHz
Is. From FIGS. 2 and 3, it can be seen that the output amplitude frequency characteristic is improved in the high frequency band by compensating with the second capacitive element. The improvement effect is larger in FIG. 2, and the improvement in FIG. 3 is smaller than that in FIG. Therefore, at least the first phase shifter 12 should be compensated. Also,
From FIG. 4, it can be seen that the frequency band in which the output phase difference is 90 ° ± 2 ° is from 350 MHz to 800 MHz, and a wide band characteristic of 1 octave or more is obtained. Regarding the wide band property of the phase difference, a slight improvement effect can be seen by including the second capacitive element for compensation.

以上の説明は、固定の位相差の分岐回路について説明
したが第1図中の容量素子27,28,31,32の少くとも1つ
をトランジスタの接合容量で形成される可変容量、ある
いはそれと並列に接続される固定容量素子とで構成し、
両出力信号の位相差を可変にすることも可能である。第
5図は、その場合の回路構成例を示したものであり、第
2の移相器13においてトランジスタQ3のベース、コレク
タを接続し、その接続点をトランジスタQ2のエミッタに
接続し、エミッタを容量素子33を通じて出力端子15に接
続し、またこのエミッタを抵抗器34を通じて制御端子35
に接続し、トランジスタQ3のベース−エミッタ間の接合
容量で可変容量を形成している。制御端子22に印加する
電圧を変化してトランジスタQ3のベース−エミッタ間接
合容量を変化させる。また、トランジスタQ3のエミッ
タ、コレクタ間に容量素子36を接続し、この容量素子36
は、トランジスタQ2のエミッタ側に入る全体の容量の値
を大きくし、それにより抵抗素子28が極端に大きくなる
のを防ぎ、出力端子15の出力への振幅周波数特性の劣化
を抑えるためのものである。また、第6図は、この発明
を90度位相合成回路として適用した場合の回路構成例で
ある。第1、第2の移相器12,13にそれぞれ入力端子37,
38から2つの信号を入力し、第1、第2の移相器12,13
の各出力を一定の位相差で合成回路39で合成して出力端
子41に出力するものである。
In the above description, a branch circuit with a fixed phase difference is explained, but at least one of the capacitive elements 27, 28, 31, 32 in FIG. 1 is a variable capacitance formed by a junction capacitance of a transistor, or in parallel therewith. Consists of a fixed capacitance element connected to
It is also possible to make the phase difference between both output signals variable. FIG. 5 shows an example of the circuit configuration in that case, in which the base and collector of the transistor Q 3 are connected in the second phase shifter 13, and the connection point is connected to the emitter of the transistor Q 2 . The emitter is connected to the output terminal 15 through the capacitive element 33, and the emitter is connected through the resistor 34 to the control terminal 35.
, And the junction capacitance between the base and emitter of the transistor Q 3 forms a variable capacitance. The base-emitter junction capacitance of the transistor Q 3 is changed by changing the voltage applied to the control terminal 22. In addition, a capacitive element 36 is connected between the emitter and collector of the transistor Q 3 and the capacitive element 36
Is for increasing the value of the entire capacitance that enters the emitter side of the transistor Q 2 and thereby preventing the resistance element 28 from becoming extremely large, thereby suppressing the deterioration of the amplitude frequency characteristic of the output of the output terminal 15. Is. FIG. 6 is a circuit configuration example when the present invention is applied as a 90-degree phase synthesizing circuit. The first and second phase shifters 12 and 13 have input terminals 37,
Two signals are input from 38 and the first and second phase shifters 12 and 13 are input.
The respective outputs of the above are combined by the combining circuit 39 with a constant phase difference and output to the output terminal 41.

なお、上記においては、バイポーラトランジスタの場
合について説明したが、本発明はFET等他のデバイスを
用いても構成することができる。また、位相差について
も90度の位相差の場合だけではなく、45度位相差回路
等、任意の位相差の回路について応用できるものであ
る。
In the above description, the case of a bipolar transistor has been described, but the present invention can also be configured by using another device such as a FET. Further, the phase difference is not limited to the case of a phase difference of 90 degrees, but can be applied to a circuit of an arbitrary phase difference such as a 45 degree phase difference circuit.

「発明の効果」 以上説明したように、この発明による位相合成分岐回
路はトランジスタのコレクタ側又はFETのドレイン側の
容量を補償することにより高周波帯での振幅周波数特性
の劣化を抑えることができる利点がある。
[Advantages of the Invention] As described above, the phase synthesizing branch circuit according to the present invention can suppress the deterioration of the amplitude frequency characteristic in the high frequency band by compensating for the capacitance on the collector side of the transistor or the drain side of the FET. There is.

【図面の簡単な説明】[Brief description of drawings]

第1図は、この発明による90度位相分岐回路の実施例を
示す接続図、第2図は、出力端子14への通過特性をシミ
ュレーションによって従来構成の場合とこの発明の場合
とについて求めた図、第3図は出力端子15の通過特性の
同様の図、第4図は、同様に90度位相分岐回路の出力位
相差を、従来構成の場合と本発明の場合とについて求め
た図、第5図は本発明による90度位相分岐回路の別の構
成例を示す接続図、第6図はこの発明の90度位相合成回
路の例を示す接続図、第7図は従来の90度位相分岐回路
の構成図、第8図は従来の90度位相分岐回路の出力位相
の周波数特性図、第9図は従来の90度位相分岐回路の出
力位相差の周波数特性図、第10図はコレクタ−基板間容
量による周波数特性への影響をシミューレーションによ
って求めた例を示す図である。
FIG. 1 is a connection diagram showing an embodiment of a 90-degree phase branch circuit according to the present invention, and FIG. 2 is a diagram obtained by simulating pass characteristics to an output terminal 14 for a conventional configuration and a case of the present invention. FIG. 3 is a similar diagram of the pass characteristic of the output terminal 15, and FIG. 4 is a diagram similarly showing the output phase difference of the 90-degree phase branch circuit in the case of the conventional configuration and the case of the present invention. 5 is a connection diagram showing another configuration example of the 90-degree phase branch circuit according to the present invention, FIG. 6 is a connection diagram showing an example of the 90-degree phase synthesizing circuit of the present invention, and FIG. 7 is a conventional 90-degree phase branch circuit. Circuit configuration diagram, Fig. 8 is the frequency characteristic diagram of the output phase of the conventional 90-degree phase branch circuit, Fig. 9 is the frequency characteristic diagram of the output phase difference of the conventional 90-degree phase branch circuit, and Fig. 10 is the collector- It is a figure showing an example in which the effect on the frequency characteristics due to the capacitance between the boards was obtained by simulation. That.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】入力信号を第1、および第2の移相器へ供
給して一定の位相差で分岐し、又は第1、第2の入力信
号をそれぞれ第1、第2の移相器へ供給し、これら第
1、第2の移相器の出力を位相合成し、前記第1、第2
の移相器はそれぞれトランジスタのコレクタおよびエミ
ッタ、又はFETのドレインおよびソースがそれぞれ各別
の抵抗器を通じて直流電圧を印加できる形で交流的に接
地され、前記コレクタおよびエミッタ間、又は前記ドレ
インおよびソース間に抵抗素子および容量素子の直列回
路が接続され、前記トランジスタのベース、又はFETの
ゲートを入力端子とし、前記抵抗素子および容量素子の
接続点を出力端子とするものである位相合成・分岐回路
において、 前記第1、第2の移相器の少くとも一方の前記トランジ
スタのコレクタおよびエミッタ間又はFETのドレインお
よびソース間に第2の容量素子が接続されていることを
特徴とする位相合成・分岐回路。
1. An input signal is supplied to a first phase shifter and a second phase shifter to be branched with a constant phase difference, or first and second input signals are respectively fed to a first phase shifter and a second phase shifter. Are supplied to the first and second phase shifters, and the outputs of the first and second phase shifters are phase-synthesized,
In the phase shifter, the collector and the emitter of the transistor, or the drain and the source of the FET are AC-grounded in such a manner that a DC voltage can be applied through different resistors, respectively, and between the collector and the emitter, or the drain and the source. A phase combining / branching circuit in which a series circuit of a resistance element and a capacitance element is connected between, the base of the transistor or the gate of the FET is used as an input terminal, and the connection point of the resistance element and the capacitance element is used as an output terminal. In the phase synthesizing method, the second capacitive element is connected between the collector and the emitter of at least one of the first and second phase shifters or between the drain and the source of the FET. Branch circuit.
【請求項2】前記容量素子又は/および前記第2の容量
素子は、トランジスタ又はFETの接合容量により形成さ
れる可変容量素子、あるいはこれと並列に接続された固
定の容量素子とで構成されていることを特徴とする請求
項1記載の位相合成・分岐回路。
2. The capacitance element and / or the second capacitance element is composed of a variable capacitance element formed by a junction capacitance of a transistor or a FET, or a fixed capacitance element connected in parallel with the variable capacitance element. The phase synthesizing / branching circuit according to claim 1, wherein:
JP6619490A 1990-03-16 1990-03-16 Phase synthesis / branch circuit Expired - Lifetime JPH0831772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6619490A JPH0831772B2 (en) 1990-03-16 1990-03-16 Phase synthesis / branch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6619490A JPH0831772B2 (en) 1990-03-16 1990-03-16 Phase synthesis / branch circuit

Publications (2)

Publication Number Publication Date
JPH03267807A JPH03267807A (en) 1991-11-28
JPH0831772B2 true JPH0831772B2 (en) 1996-03-27

Family

ID=13308799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6619490A Expired - Lifetime JPH0831772B2 (en) 1990-03-16 1990-03-16 Phase synthesis / branch circuit

Country Status (1)

Country Link
JP (1) JPH0831772B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019176455A (en) * 2018-03-27 2019-10-10 パナソニック株式会社 Phase shifter and wireless communication apparatus

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111937301A (en) 2018-04-18 2020-11-13 三菱电机株式会社 Polyphase filter
WO2019202685A1 (en) 2018-04-18 2019-10-24 三菱電機株式会社 Polyphase filter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019176455A (en) * 2018-03-27 2019-10-10 パナソニック株式会社 Phase shifter and wireless communication apparatus

Also Published As

Publication number Publication date
JPH03267807A (en) 1991-11-28

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