JPS6054503A - Even-order high frequency multiplying circuit - Google Patents

Abstract

PURPOSE:To make wide-band signal multiplication possible by providing a transistor (TR) which cuts off a differential amplifier circuit of a high frequency multiplying circuit for a certain time, for this differential amplifier circuit of the high frequency multiplying circuit where a tuning circuit is a collector load. CONSTITUTION:TRs 1 and 2 have collectors connected commonly and are driven by differential inputs, and the emitter of a TR3 is connected to emitters of TRs 1 and 2 commonly. The bias potential due to resistances 4 and 5 is set to a value higher than that due to resistances 6 and 7 by a potential corresponding to an even multiplier. Then, a current is flowed to TRs 1 and 2 alternately only, for example, for periods shown in a figure, and the current is cut off for the other periods by the TR3. Since harmonic waves in multiplications other than doubling are reduced considerably in this constitution, selectivity characteristics of tuning circuits 8 and 9 are set relatively widely, and as a result, transmission characteristics having a wide group delay time characteristic are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an even-order multiplier circuit in a high frequency circuit.

Conventional configurations and their problems In recent years, there has been a high demand for high performance, high-fidelity reproduction, and high-quality reception in the field of receivers for audio equipment, and many circuit technologies and methods that previously belonged to the field of communication equipment have been adopted. , has been introduced. However, when adopting technology from the field of communication devices, there are aspects that are not suitable for receivers for audio equipment if the conventional technology is simply used as is.

A conventional even-order multiplier circuit will be explained below. FIG. 7 shows a conventional even-order multiplier circuit. When an input signal enters the bases of transistors 1 and 2, the collector side of each generates a high-order harmonic signal shown in FIG. 8, which is transmitted to a commonly connected collector load 8. In the harmonic signal, components other than the desired harmonic are attenuated due to the frequency versus amplitude characteristics of the load 8, and a multiplied signal containing the harmonic shown in FIG. 9 is output.

However, if the coupling coefficients of loads 8 and 9 are changed to improve the harmonic content as described above and a high selectivity characteristic is adopted as the load, the harmonic content is improved, but as shown in Fig. 6. As such, two elements of signal transmission, the level C of the high band characteristic and the group delay time characteristic d, deteriorate.

As described above, the conventional method has problems as it is not suitable for multiplication of signals over a wide band.

Purpose of the Invention The object of the present invention is to provide an inexpensive even-order high-frequency multiplier circuit that can realize high-band transmission characteristics by modifying the group delay time characteristics of a transmission signal when multiplying even-order high frequencies. shall be.

Configuration of the Invention Two transistors whose collectors are connected in common and driven by differential inputs, a tuning circuit connected to the collectors of the two transistors, and the two transistors and emitters are commonly connected to perform a current switch. The structure includes other transistors and a bias circuit that supplies a bias potential to each of the transistors.

With this configuration, the load is switched between the two transistors and the other transistor, and no output signal is generated when the load is on the other transistor, and
Due to the differential input to the two transistors, odd-order harmonic components are canceled.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows an even-order high frequency multiplier circuit in an embodiment of the present invention. 1, 2, and 3 are transistors, respectively. Transistors 1 and 2 have their collectors connected in common and are driven by differential inputs. The emitters of transistors 3 are commonly connected to the emitters of transistors 1.2. 4 to 7 are resistors forming a bias circuit. The base of transistor 3 is connected to resistor 4.5.

The bias potential generated by resistor 4.5 is applied to resistor 6.5.
7 is set higher than the bias potential generated by 7 by an amount corresponding to the even multiplier. As a result, the collector currents of the I transistors 1 and 2 flow only during a certain period of the input signal, and are switched to the transistor 3 at other times, as shown in FIG. FIG. 2 shows the level state of harmonic components generated by the commonly connected collector currents of transistors 1 and 2.

FIG. 3 shows the power level with other components attenuated by the frequency versus amplitude characteristics of the collector load 8 shown in FIG. Note that the load 8 and the load 9 constitute a tuned circuit. In this example, second-order even multiplication is shown, but as shown in Figure 2, the neighboring odd multiplication levels are smaller than in the conventional one, so the selectivity characteristics of the load tuning circuit are different from those in the conventional one. Compared to the circuit shown in FIG. 6, there is no need to make the frequency-to-amplitude characteristic a wide-band, as shown in FIG. 6. Additionally, the group delay time characteristics became wider, and as a result, wider transmission characteristics could be realized.

Effects of the Invention According to the present invention, it is possible to widen the selectivity characteristics of the load tuning circuit and improve the group delay time characteristics, thereby making it possible to perform signal multiplication over a wide band. Furthermore, the present invention does not require particularly expensive bandpass filters, and conventional circuit components can be used as they are, so that cost increases can be kept to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the even-order high frequency multiplier circuit of the present invention, FIG. 2 is a graph showing the generation level of harmonic components generated by transistors l and 2, and FIG. Graph showing the generation level of wave components, Figure 4 is a waveform diagram showing the switching state of the transistor, Figure 5 is a waveform diagram showing the output level appearing on the load corresponding to the switching state of Figure 4, and Figure 6 is Waveform diagrams showing frequency vs. amplitude characteristics and frequency vs. delay characteristics of the present invention and conventional examples,
7 to 9 are graphs showing conventional circuits and their characteristics. 1 to 3...transistor, 4 to 7...resistance 8.9.
...Load agent Patent attorney Oshima -Ko Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] two transistors whose collectors are commonly connected and driven by a differential input, a tuning circuit connected to the collectors of the two transistors, and another transistor whose emitters are commonly connected to the two transistors to perform current switching; an even-order high frequency multiplier circuit comprising a bias circuit that supplies a bias potential to each of the transistors.