JPH08223233A - Orthogonal modulator - Google Patents

Abstract

PURPOSE: To apply orthogonal modulation to a signal at a high frequency band such as a quasi-microwave band through a small sized and inexpensive configuration with low power consumption. CONSTITUTION: A 1/2 frequency divider circuit 4 outputs a received carrier as two signals whose frequency is half that of the carrier and whose phase difference is 90 deg.. A 1/2 frequency divider circuit 5 frequency-divides the received carrier into a signal whose frequency is half that of the carrier. Multiplier circuits 6, 7 multiply 1st and 2nd modulation signals with a frequency division signal outputted from the 1/2 frequency divider circuit 4. A synthesis amplifier 8 synthesizes and amplifies output signals of the multiplier circuits 6, 7. A multiplier circuit 9 multiplies output signals of the synthesis amplifier 8 and the 1/2 frequency divider circuit 5 and outputs the product to terminals 10a, 10b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature modulator, and more particularly to a quadrature modulator for digital communication suitable for use in modulating a signal phase in a high frequency band such as a quasi-microwave band.

[0002]

2. Description of the Related Art FIG. 6 shows a circuit diagram of an example of a conventional quadrature modulator. In the figure, the printed wiring board 50 includes a 90-degree phase shift circuit 51, a first mixer 56a including diodes 52a and 53a, high impedance lines 54a and 55a, diodes 52b and 53b, a high impedance line 54b, and the like. Second mixer 56 including 55b and the like
b, the balanced-to-unbalanced conversion circuits 57a and 57b, and circuit elements such as the signal synthesizing resistor 58, and the modulated signal input terminals 60a and 61a connected to the carrier wave input terminal 59 and the first mixer 56a. , Modulation signal input terminals 60b and 61b connected to the second mixer 56b, and a resistor 5
Output terminals 62 connected to both ends of 8 are provided.

This quadrature modulator is called a diode modulator, and the carrier wave input from the input terminal 59 is made into two kinds of carrier waves having phases different from each other by 90 degrees by the 90-degree phase shift circuit 51, and one carrier wave is the first carrier wave. The first carrier is supplied to the first mixer 56a and is multiplied by the first modulation signals of opposite phases input from the input terminals 60a and 61a, and the other carrier is supplied to the second mixer 56b and the input terminals 60b and 61a.
It is multiplied by the second modulation signals having opposite phases input from b. The first and second multiplication outputs extracted from the first and second mixers 56a and 56b are the transformers 57a,
After being combined by the resistor 58 through 57b, the output terminal 62
It is output as a quadrature modulated wave.

However, this conventional quadrature modulator is +
High carrier input level of about 20 dB _m is required, difference between leaked carrier and output signal is only about -20 dB, configuration of 90-degree phase shift circuit 51 is difficult, band is narrow, large volume is required, and device is large There is a problem such as becoming.

Therefore, conventionally, in order to solve the problem of the diode type modulator, a method of forming the quadrature modulator by a semiconductor integrated circuit has been adopted. For example, the Institute of Electrical and Electronics Engineers (IEEE) of the United States, published in 1992, Bipolar Circuits and Technology.
The paper entitled "QPSK for Digital Cellular Communications", pages 59-62 of Meeting 3.2.
Modulator "(QPSK Modulator for Digital Cellular
Communication) discloses a quadrature modulator as shown in the circuit diagram of FIG. 7.

As shown in the figure, in this conventional quadrature modulator, the local oscillation signal LO1 is converted into a first signal and a second signal whose phases are different from each other by 90 degrees by a phase shifter 65, and then the first signal is generated.
Is supplied to the mixer 66, and the in-phase signal I of the opposite phase is supplied.
And the second signal is supplied to the mixer 67 to be multiplied by the quadrature signals Q having opposite phases to each other, and the respective multiplication output signals are supplied to the combining amplifier 68 to be combined to obtain a QPSK modulated wave. This QPSK modulated wave is filtered by a filtering circuit 69 having a band-pass filter characteristic to obtain only a necessary frequency component, and then supplied to a mixer 70 to generate a local oscillation signal LO2.
Is converted to a quasi-microwave band signal by frequency conversion, and the output amplifier 71 and the balanced-unbalanced conversion circuit 72
Is output via each.

In addition, the 20th Europe in 1990
Microwave Conference Proceedings Digital Phase Shift Quadrature Frontend for Local Input Up to 6 GHz (P.We
ger et al., "DIGITAL PHASE-SHIFTQUADRATURE FRONTED FOR L
O-INPUTS UP TO 6 GHz ", pp.426) discloses a quadrature modulator as shown in the block diagram of FIG.

As shown in the figure, in this conventional quadrature modulator, a 90-degree phase shift circuit 80 is composed of a mixer 81 and a 1/2 frequency divider circuit 82. This quadrature modulator multiplies a local oscillation signal LO by a mixer 81 to take out signals whose phases are opposite to each other and whose frequency is doubled, and divides each of them by a frequency divider 82. By doing so, the carrier wave LO is different in phase by 90 degrees from each other and has the same frequency as the local oscillation signal LO.
Outputs _Q and LO _I. The mixers 84 and 85 are modulated signals R
F is multiplied by each of the carrier waves LO _Q and LO _I ,
The multiplication signals IF _Q and IF _I are output as quadrature modulated waves.

In the conventional quadrature modulator shown in FIG. 8, the 90-degree phase shift circuit 80 is made into a semiconductor integrated circuit by silicon bipolar transistors. On the other hand, a quadrature modulator integrated with a compound semiconductor such as gallium arsenide is also disclosed in, for example, IEE Journal of Solid State Circuits Vol. 28, No. 1.
A 1.9 GHz band GaAs direct quadrature modulator 1C with a phase shifter (K. Yamamoto et al., "A 1.9-GHz-Band GaAsDirect-")
Quadrature Modulator IC with a Phase Shifter ", IEEE
JOURNAL OF SOLID-STATE CIRCUITS ", VOL.28, NO.10, OCT
OBER 1993, pp.994-1000).

FIG. 9 shows a circuit diagram of a quadrature modulator which is disclosed in the above-mentioned document and which is made into an integrated circuit with a compound semiconductor. This conventional device includes a 90-degree phase shift circuit 91 and an amplifier circuit 9.
2. The mixer 93 and 94. The amplifying circuit 92 has a bias capacitor in the preceding stage, and has a configuration in which differential amplifying circuits using field effect transistors made of gallium arsenide are cascade-connected in three stages. Is input, amplified, and supplied to the mixers 93 and 94, where it is multiplied by the modulation signal.

Further, conventionally, some methods for correcting the phase error of the 90-degree phase shift circuit have been proposed (for example,
JP-A 61-238144, JP-A 2-174343
No. 4-287542, each gazette). As an example, FIG. 10 shows a block diagram of a quadrature modulator disclosed in Japanese Patent Laid-Open No. 2-174343. In this conventional quadrature modulator, in FIG. 10, a carrier signal input from an input terminal 99 is branched into two by a branch circuit 100, one of which is supplied to a mixer 103 to be multiplied by a first modulated signal from an input terminal 101. , And the other phase is shifted by 90 degrees by the variable phase shifter 105 and then supplied to the mixer 104 to be multiplied by the second modulation signal from the input terminal 102. The output signals of the mixers 103 and 104 are combined by the combining circuit 108 and output to the output terminal 109 as QP.
It is output as an SK modulated wave.

In addition to this general configuration, in the above conventional apparatus, the phase difference between the carrier waves supplied to the mixers 103 and 104 in the phase comparator 106 is deviated from the original 90 degrees. A signal corresponding to the detected phase difference is supplied as a control signal to the variable phase shifter 105 via the loop filter 107, and the phase shift amount of the variable phase shifter 105 is calculated based on the output signals of the mixers 103 and 104. Variable control is performed so that the phase difference becomes 90 degrees.

Further, conventionally, a 90-degree phase shifter usable in the quasi-microwave band is constructed by a passive circuit having no power consumption.
A quadrature modulator as shown in 1 is also known (1993 Spring Conference of the Institute of Electronics, Information and Communication Engineers C-80). In this conventional quadrature modulator, the interdigital type 9 is provided on the substrate 111.
A 0-degree phase shifter 112 is provided, and the 90-degree phase shifter 112 converts a carrier wave input through the terminal 113 into first and second carrier waves having phases different from each other by 90 degrees, thereby forming an integrated circuit 2. The signals are supplied to the phase modulators 114 and 115, respectively, where they are modulated by the modulation signals from the terminals 116 and 117. The output signals of the two-phase modulators 114 and 115 are
It is output as a four-phase phase modulated wave to the output terminal 119 via a combining circuit provided on the substrate 118.

In this conventional quadrature modulator, an interdigital 90-degree phase shifter 112 is formed as a thin film circuit on an alumina / ceramics substrate 111, and this substrate 111 and substrate 118 are integrated together with two-phase modulators 114 and 115. By incorporating it into one package, it has a wide band of 1.5 GHz band and low power consumption.

Further, a quadrature modulator used in the quasi-microwave band in which a phase shift circuit is composed of passive elements has been conventionally known (Japanese Patent Laid-Open No. 347529/1993). FIG. 12 shows a circuit diagram of an example of a phase shift circuit in this conventional quadrature modulator. In the figure, the 90-degree phase shift circuit is the first phase shift unit 1
21a and a first phase-shift circuit including a cascade connection circuit of the first differential amplifier circuit 122a, and a second phase shift circuit including a second phase-shift unit 121b and a cascade connection circuit of the second differential amplifier circuit 122b. The phase circuit and the input are connected in parallel.

Each of the phase shifters 121a and 121b is composed of a series circuit of two four-terminal phase shifters, and these are formed on a semiconductor substrate by a spiral coil as a phase advancing element and a MIM (Metal Insulator Metal) as a lag element. And a capacitor. These phase shifters 121a and 121b have high frequency input signals RF of opposite phases to their input terminals.
1 and RF2 are input, and two types of signals S2A and S2B represented by vectors which are phase-shifted and orthogonal to each other are input.
And S4A and S4B are output. Here, the signal S2
Combined vector S2 of A and S2B and signals S4A and S4
The phase shift amounts of the phase shifters 121a and 121b are set so as to be substantially orthogonal to the combined vector S4 of 4B.

The signals S2A and S2B and S4A and S4B are input to the gates of the differential pair transistors of the differential amplifier circuits 122a and 122b in the next stage, where they are differentially amplified and the in-phase output terminal and the inverted output terminal. Signal V respectively
It is output as 1A and V1B, V2A and V2B.
Here, the output signals V1A and V2A are 90 degrees out of phase with each other.
The output signals V1B and V2B are also 90 degrees out of phase with each other.

According to this conventional phase shift circuit, for example, FIG.
As shown in FIG. 3, 90 ° with respect to the high frequency input signals RF1 and RF2 in the frequency range from 700 MHz to 2 GHz.
It is possible to output signals V1A (V1B) and V2A (V2B) whose phases are matched with an accuracy of ± 2 °.

[0019]

However, in the conventional device shown in FIG. 7 among the above-mentioned conventional devices, the signal is converted into the quasi-microwave band by the mixer 70 after being modulated at a low frequency. However, there is a drawback in that two types, LO1 and LO2, are required, and the configuration becomes complicated to generate spurious noise.

Further, although the conventional device shown in FIG. 8 requires only one LO signal source, the 90 ° phase shift circuit formed into a semiconductor integrated circuit with bipolar transistors is also the configuration circuit shown by 80 in FIG. With other configurations, carrier frequency 1
It has not been put to practical use above GHz and is difficult to use in the quasi-microwave band. The reason is that, for example, when trying to quadrature-modulate a 3 GHz signal, it is technically difficult to handle twice the 6 GHz signal.

Further, in the conventional device shown in FIG. 9, since the 90-degree phase shift circuit 91 uses a filtering circuit composed of a resistor and a capacitor, the output level is corrected in order to correct the output level imbalance. However, there is a problem that the power consumption is increased because the amplifier circuit 92 is required so that the power consumption becomes constant. Also,
Since a compound semiconductor field effect transistor is more expensive than a silicon bipolar transistor, there is also a problem that the entire device is expensive.

In the conventional apparatus shown in FIG. 10, the phase shifter is composed of the variable phase shifter 105, and the phase error detected by the phase comparator 106 is fed back to the variable phase shifter 105, so that 90
The method is to increase the phase shift accuracy. However, the patent publication in which this conventional device is described does not specifically describe the variable phase shifter 105, and this conventional device cannot be used in the quasi-microwave band. This is the same in each of the above-mentioned JP-A-61-238144 and JP-A-4-287542.

Although the conventional device shown in FIG. 11 consumes less power, the pattern of the thin film circuit for forming the interdigital 90-degree phase shift circuit 112 on the substrate 111 requires high accuracy. Is expensive,
It takes time and effort to bond fine wires such as gold to the connection of fine patterns. Further, in this conventional device, the substrate 11
Since the semiconductor integrated circuit chips of the 1 and 118 and the two-phase modulators 114 and 115 are bonded to the package with the brazing material, it is troublesome, expensive and has a large volume.

Further, when the phase shift circuit of the conventional device shown in FIG. 12 is formed on a semiconductor integrated circuit, it is difficult to form the spiral coil in accordance with a desired constant, and trial and error is required. It has the drawback that it takes time. Moreover, in this conventional circuit, a spiral coil and MI are used.
Since the constant of the M-type capacitor varies greatly depending on the integrated circuit, the 90-degree phase difference to be obtained also varies widely. Furthermore, in this conventional circuit, a large area is required to form a spiral coil having a constant of several hundreds nH, which causes a problem that the volume of the entire device is large and the cost is high.

Further, in the phase shift circuit of this conventional device, as shown in FIG.
As can be seen from the characteristics shown in 3, 700 MHz to 2 G
There is an error of 2 degrees in the frequency range up to Hz, and there is also a drawback that the error is large when variations are taken into consideration. Furthermore, the bandwidth 1.3 GHz at which the desired phase shift of this phase shift circuit is obtained is a rather insufficient bandwidth when considering various applications in the quasi-microwave band.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a quadrature modulator capable of quadrature modulating a signal in a high frequency band such as a quasi-microwave band with a small size, low power consumption and an inexpensive structure.

[0027]

In order to achieve the above-mentioned object, the present invention uses an input carrier wave at a frequency of 1/2.
Further, a first frequency dividing circuit which outputs two signals having phases different from each other by 90 degrees, a second frequency dividing circuit which divides a carrier wave into a frequency of 1/2, and an output 2 of the first frequency dividing circuit. A first multiplication circuit that multiplies one of the signals and the first modulated signal; a second multiplication circuit that multiplies the other of the two output signals of the first frequency dividing circuit and the second modulated signal; It is configured to have a synthesizing circuit for synthesizing the output signals of the first and second multiplying circuits, and a third multiplying circuit for multiplying the output signal of the synthesizing circuit and the output signal of the second frequency dividing circuit. It is a thing.

[0028]

According to the present invention, the first frequency dividing circuit causes the mutual
A frequency that is 1/2 times that of the first and second carriers having different degrees of phase is generated, and the first and second frequencies are generated at these frequencies.
After the first modulated signal and the second multiplied circuit multiply the modulated signal of No. 1 by the first and second multiplying circuits, the result of the multiplication is combined by the combining circuit and multiplied by the frequency of 1/2 of the carrier by the third multiplying circuit to obtain the desired carrier. Since the modulated wave quadrature-modulated with the first and second modulated signals is output, the frequency handled by this circuit is suppressed to about the sum of the frequencies of the first and second modulated signals and the carrier frequency. be able to.

Further, in the present invention, since the first and second frequency dividing circuits, the first to third multiplying circuits and the synthesizing circuit are respectively configured by the emitter coupling circuit, they can be configured by an integrated circuit. it can.

[0030]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of a quadrature modulator according to the present invention. As shown in the figure, in this embodiment, carrier wave input terminals 1a and 1b, modulated signal input terminals 2a, 2b and 3a,
3b, and a first 1/2 divider circuit 4 for dividing the carrier waves from the input terminals 1a and 1b by 1/2 and outputting carriers having phases different from each other by 90 degrees and the input carrier wave by 1/2. The second 1/2 frequency dividing circuit 5, the first and second multiplying circuits 6 and 7, a synthesis amplifier 8 which synthesizes the output signals of these multiplying circuits 8, respectively, and the 1/2 frequency dividing circuit 5. It is composed of a third multiplication circuit 9 which multiplies each output signal of the amplifier 8 and outputs the result to the output terminals 10a and 10b.

1/2 frequency dividing circuits 4 and 5, multiplying circuits 6 and 7
, 9 and the composite amplifier 8 are respectively connected to a silicon (Si) bipolar emitter combination (ECL: Em) as described later.
It is composed of an itter-coupled logic circuit. The 1/2 divider circuits 4 and 5 are composed of master slave T flip-flops as shown in FIG. 2, and the multiplier circuits 6, 7 and 9 are Gilbert cell type multipliers as shown in FIG. 4, respectively. Further, the composite amplifier 8 is composed of a differential amplifier and a buffer emitter follower as shown in FIG. 5, which are known circuits. However, a circuit for generating a necessary direct current (DC) voltage is omitted in FIGS. 2, 4, and 5.

Next, the operation of the embodiment shown in FIG. 1 will be described. Now, let the input carrier waves at the input terminals 1a and 1b be f _LO ,
The input modulation signal of the input terminals 2a and 2b is f _M , and the input terminal 3
When the input modulation signals of a and 3b are f _M ′, these are represented by the following equation.

F _LO = cos 2ω _L t (1) f _M = cos ω _mt (2) f _M ′ = sin ω _mt (3) The 1/2 frequency divider circuit 4 has an input carrier wave from the input terminals 1 a and 1 b. The frequency of f _LO is divided by two, and signals whose phases are different from each other by 90 degrees are output. As a result, the 1/2 divider circuit 4
The output signals are represented as cos .omega _L t and sin .omega _L t.
The output signal of the 1/2 frequency divider circuit 5 is input to the input terminals 1a, 1
Since the input carrier _{f LO} than b is 1/2 frequency-divided signal, but may be either of the above cos .omega _L t and sin .omega _L t, where the cos .omega _L t.

The first 1 output from the 1/2 frequency divider circuit 4
The 1/2 frequency-divided output cos ω _L t is supplied to the multiplication circuit 6,
Here, it is multiplied by the first modulation signal f _M from the input terminals 2a and 2b. On the other hand, the second ½ frequency division output sinω _L t output from the ½ frequency division circuit 4 is supplied to the multiplication circuit 7, where the second modulation signal f _M from the input terminals 3a and 3b. ’ Co extracted from the multiplication circuit 6
a multiplication signal represented by sω _L t · cosω _m t, and the multiplied signal represented by the retrieved from the multiplying circuit _{7 sinω L t · sinω m t} , are combined amplified with synthetic amplifier 8, Table by: It is regarded as a composite signal.

[0035] _{cosω L t · cosω m t +} sinω L t · sinω m t = (1/2) · {cos (ω L + ω m) t + cos (ω L -ω m) t} + (1/2) · {cos _{(ω L -ω m) t-} cos (ω L + ω m) t} = cos (ω L -ω m) t (4) the composite signal is supplied to the multiplying circuit 9, wherein the 1/2 frequency divider 5 is multiplied by the signal represented by cos ω _L t to obtain a signal represented by the following equation, and output terminals 10a, 10
output to b.

[0036] _{cos (ω L -ω m) t} × cosω L t = (1/2) · {cos (2ω L -ω m) t + cosω m t} (5) The output terminal 10a, the output signal of 10b is Carrier wave co
Modulated wave (1/2) · {cos (2ω _L −ω _m ) t} obtained by modulating s2ω _L t with the modulation signal cosω _mt and low frequency component (1/2) · (cosω _mt ) And a low frequency component (1 /
2). (Cos ω _mt ) is removed and only the modulated wave of the desired angular frequency (2ω _L −ω _m ) is separated.

When such modulation is performed by the conventional device shown in FIG. 8, the LO carrier input frequency is 2ω _L and the multiplier 8
Since the output of 1 is 4ω _L , the frequency of twice the carrier wave is handled, and it is necessary to improve the high frequency characteristics of the semiconductor element. Further, if the high frequency characteristics are the same, it is necessary to increase current consumption. On the other hand, according to the present embodiment, the frequency to be handled is at most about the frequency of the input signal plus the frequency of the modulation signal as shown in the equation (5),
There is no need to handle high frequencies such as the second harmonic of the carrier wave,
The power consumption can be kept low.

Next, the configuration and operation of each component circuit shown in FIG. 1 will be described. FIG. 2 shows a circuit diagram of an example of the 1/2 frequency dividing circuits 4 and 5. In FIG. 2, a rectangular wave as shown in FIG. 3A is provided between the input terminals 1a and 1b (here, a rectangular wave is used for convenience of description, but a sine wave is normal in a high frequency band, and of course, a sine wave may be used. Input), the bases of the NPN transistors Q2 and Q1, the NPN transistor Q12,
Input to the base of Q13. Here, N connected to the common emitter side of the transistors Q1 and Q2
The PN transistor Q3 and the NPN transistor Q connected to the common emitter side of the transistors Q12 and Q13.
Reference numerals 14 respectively constitute constant current sources with a fixed DC voltage applied to the base from the input terminal 13.

Based on the input input to the bases of the transistors Q1 and Q2, N on the collector side of the transistor Q1
Of the PN transistors Q4 and Q5 and the NPN transistors Q6 and Q7 on the collector side of the transistor Q2,
The outputs taken out from the collectors of Q4 and Q6 are inputted to the base of an NPN transistor Q8 which constitutes an emitter follower and outputted from the emitter thereof, and further inputted to the bases of a transistor Q7 and NPN transistors Q10 and Q15, respectively, Q5 and Q7. The output taken out from the collector of the NPN is an NPN that constitutes an emitter follower.
It is input to the base of the transistor Q9 and output from its emitter, and further input to the bases of the transistor Q6 and NPN transistors Q11 and Q16.

The emitter output of the NPN transistor Q19 is the transistor Q5 and the NPN transistor Q1.
8 and Q21, and the emitter output of the NPN transistor Q20 is input to the bases of the transistors Q4 and NPN.
It is input to the bases of the transistors Q17 and Q22. The emitter output of the transistor Q8 is the transistor Q
It is output to the output terminal 11b via 10 and the emitter output of the transistor Q9 is output to the output terminal 11a via the transistor Q11.

The outputs taken from the collectors of the transistors Q15 and Q17 on the basis of the inputs inputted to the bases of the transistors Q12 and Q13 are outputted to the output terminal 12b through the transistors Q19 and Q21, respectively, and the outputs of Q16 and Q18 are outputted. The output extracted from the collector is output to the output terminal 12a via the transistors Q20 and Q22.

As a result, a rectangular wave which is inverted at each rising edge of the input rectangular wave is taken out between the output terminals 11a and 11b, and between the output terminals 12a and 12b as shown in FIG. As shown in C), a rectangular wave that is inverted every time the input rectangular wave falls is taken out. FIG. 3 (B)
The output rectangular wave shown in is half the input rectangular wave in FIG.
The divided waveform has a phase difference of 180 degrees. On the other hand, the output rectangular wave shown in FIG. 3 (C) is a waveform obtained by dividing the input rectangular wave in FIG. 3 (A) by 1/2, and has a phase difference from the output rectangular wave shown in FIG. 3 (B). It is 90 degrees. Therefore, with this circuit, a 1/2 divided output signal having a phase difference of 90 degrees can be obtained.

FIG. 4 is a circuit diagram of an example of the multiplication circuits 6, 7 and 9 shown in FIG. This multiplication circuit is a Gilbert cell type multiplication circuit and has a configuration of a double balanced differential amplifier circuit.
That is, the emitters of the NPN transistors Q31 and Q32 are commonly connected, and their bases are the input terminals 21a,
21b is a differential amplifier circuit connected to NPN transistors Q33 and Q34, the emitters of which are commonly connected, and the bases of which are connected to the input terminals 21b and 21a to form a differential amplifier circuit, which is an NPN transistor Q35. , And Q36 form a differential amplifier circuit in which the emitters are commonly connected via resistors R3 and R4, and the bases are connected to the input terminals 22a and 22b.

The collectors of the transistors Q31 and Q33 are connected to the power supply voltage Vcc terminal via the resistor R1 and to the output terminal 24a. The collectors of the transistors Q32 and Q34 are connected to the power supply voltage Vcc terminal via the resistor R2,
It is connected to the output terminal 24b. Further, the NPN transistor Q37 has a collector commonly connected to the resistors R3 and R4, and an emitter grounded via the resistor R5. A constant DC voltage is input to the base of the transistor Q37 via the input terminal 23 to form a constant current source.

Next, the operation of this multiplication circuit will be described. A 1/2 divider circuit 4 is provided between the input terminals 21a and 21b.
Alternatively, the output signal of 5 is input as the first input signal, and the modulation signal or the output signal of the synthesis amplifier 8 is input as the second input signal between the input terminals 22a and 22b. The input signals input between the input terminals 22a and 22b are differentially amplified by the transistors Q35 and Q36, and output to the collectors in the opposite phase.

Here, assuming that the potential of the input terminal 21a is higher than the potential of the input terminal 21b, the transistor Q
31 and Q34 conduct, respectively, and the transistors Q32 and Q33 are cut off. As a result, the amplified signal output from the collector of the transistor Q35 is output from the collector of the transistor Q31 to the output terminal 24a, and the amplified signal output from the collector of the transistor Q36 is output from the transistor Q34 to the output terminal 24b. Therefore, at this time, when the potential of the input terminal 22a is higher than that of the input terminal 22b, the potential of the output terminal 24a is higher than that of the output terminal 24b, and the potential of the input terminal 22a is higher than that of the input terminal 22b. When the electric potential is lower, the output terminal 24b than the output terminal 24b
The potential of a becomes lower, and the second input signal is amplified and output in the positive phase between the output terminals 24a and 24b.

On the other hand, the potential of the input terminal 21a is equal to that of the input terminal 2
When it is lower than the potential of 1b, the transistors Q31 and Q34 are cut off, respectively, and the transistor Q31 is cut off.
32 and Q33 are conductive. As a result, the amplified signal output from the collector of the transistor Q35 is output from the collector of the transistor Q32 to the output terminal 24b, and the amplified signal output from the collector of the transistor Q36 is output from the transistor Q33 to the output terminal 24a. Therefore, at this time, contrary to the above case, the second input signal between the input terminals 22a and 22b is amplified and output in the opposite phase between the output terminals 24a and 24b.

Next, the structure and operation of the composite amplifier 8 shown in FIG. 1 will be described. FIG. 5 shows a circuit diagram of an example of the synthesis amplifier. As shown in the figure, the composite amplifier 8 is composed of NPN transistors Q41 to Q47 and resistors R11 to R19. Transistors Q41 and Q42 form an emitter follower, whose base is the input terminal 3
It is connected to 1a and 31b, and the emitter of Q41 is resistor R1.
1 is grounded and connected to the base of the transistor Q43, and the emitter of Q42 is grounded via the resistor R12 and connected to the base of the transistor Q44.

Transistors Q43 and Q44 have their respective emitters commonly connected to the collector of transistor Q45 via resistors R15 and R16, and also Q43 and Q44.
Each collector of 44 is connected to the power supply voltage Vcc terminal together with each collector of transistors Q41, Q42, Q46 and Q47 via resistors R13 and R14. The transistors Q43 and Q44 and the resistors R13 to R16 form a differential amplifier circuit, and the transistor Q45 is the input terminal 33.
A constant current source is constituted by the constant voltage. Transistors Q46 and Q47 are emitter follower transistors as output buffers and resistors R18 and R19.
Is the emitter resistance.

The operation of the composite amplifier 8 will be described. The first and second input signals input to the input terminals 31 and 32 are buffered and amplified by the transistors Q41 and Q42, respectively, taken out from the respective emitters, applied to the bases of the transistors Q43 and Q44, and differentially amplified. It As a result, the first differential amplified signal of the first and second input signals is taken out from the connection point between the collector of the transistor Q43 and the resistor R13 and supplied to the base of the transistor Q46, where it is buffer-amplified and output. It is output to the terminal 34a. Further, the second differential amplified signal having a phase opposite to the first differential amplified signal is taken out from the connection point of the collector of the transistor Q44 and the resistor R14, and the transistor Q44 is taken out.
It is buffer-amplified by 47 and output to the output terminal 34b.

As is well known, the differential amplifier is characterized in that it is hardly affected by fluctuations in parameters such as the base-emitter voltage of the transistor, and that the in-phase component can be removed to some extent.

As described above, according to this embodiment, since the 90-degree phase shift circuit is constituted by the 1/2 frequency dividing circuit of the active circuit as shown in FIG. 2, it is constituted by the passive circuit. It does not require a large volume, and each constituent circuit of this embodiment is composed of an ECL circuit as shown in FIGS. 2, 4 and 5, which is a structure suitable for an integrated circuit. Furthermore,
By incorporating a 90-degree phase difference correction circuit into the circuit, it is possible to electronically correct the 90-degree phase difference.

[0053]

As described above, according to the present invention,
Since the frequency to be handled can be suppressed to about the sum of the frequencies of the first and second modulated signals and the carrier frequency, it is not necessary to handle a high frequency such as the second harmonic of the carrier unlike the conventional device. The power consumption can be kept low.

Further, in the present invention, the first and second frequency dividing circuits, the first to third multiplying circuits, and the synthesizing circuit are configured so that they can be integrated into an integrated circuit by the emitter coupling circuit. It is cheaper and smaller in volume than conventional devices using integrated circuits and spiral coils.

[Brief description of drawings]

FIG. 1 is a circuit system diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a 1/2 frequency divider circuit in FIG.

FIG. 3 is a signal waveform diagram for explaining the operation of FIG.

4 is a circuit diagram of an example of a multiplication circuit in FIG.

5 is a circuit diagram of an example of a synthesis amplifier in FIG.

FIG. 6 is a circuit diagram of an example of a conventional quadrature modulator.

FIG. 7 is a circuit diagram of another example of a conventional quadrature modulator.

FIG. 8 is a block diagram of a conventional device that is made into a semiconductor integrated circuit by using bipolar transistors.

FIG. 9 is a circuit diagram of a conventional device in which a semiconductor integrated circuit is made of a compound semiconductor.

FIG. 10 is a block diagram of an example of a conventional device having means for correcting a phase error.

FIG. 11 is a configuration diagram of an example of a conventional device in which a 90-degree phase shifter is configured by a passive circuit.

FIG. 12 is a circuit diagram of an example of a phase shift circuit including passive elements in a conventional device.

13 is a characteristic diagram of the phase shift circuit shown in FIG.

[Explanation of symbols]

1a, 1b Carrier wave input terminal 2a, 2b, 3a, 3b Modulation signal input terminal 4 First 1/2 frequency divider circuit 5 Second 1/2 frequency divider circuit 6 First multiplication circuit 7 Second multiplication circuit 8 Synthesis amplifier 9 Third multiplication circuit 10a, 10b, 11a, 11b, 12a, 12b, 2
4a, 24b, 34a, 34b Output terminals 13, 23, 33 DC constant voltage input terminals 21a, 21b Frequency division signal input terminals 22a, 22b Modulation signal or synthetic amplifier output signal input terminals 31, 32 Input terminals Q1 to Q22, Q31 to Q37, Q41 to Q47 NP
N transistor

Claims (3)

[Claims] 1. A first frequency dividing circuit which outputs an input carrier wave as a signal having a frequency of ½ times and a phase difference of 90 degrees from each other; A second frequency dividing circuit for performing frequency division; a first multiplication circuit for multiplying one of the output 2 signals of the first frequency dividing circuit by the first modulated signal; and an output 2 of the first frequency dividing circuit. A second multiplication circuit that multiplies the other of the signals by the second modulation signal, a combining circuit that combines the output signals of the first and second multiplication circuits, respectively, and an output signal of the combining circuit and the first signal. And a third multiplication circuit that multiplies the output signal of the frequency divider circuit of 2 with the quadrature modulation device. 2. The first and second frequency dividing circuits, the first frequency divider circuit.
The quadrature modulator according to claim 1, wherein each of the third to third multiplication circuits and the synthesis circuit is configured by an emitter coupling circuit. 3. The first and second frequency dividing circuits are master / slave / T flip-flop circuits, and the first and second frequency dividing circuits are provided.
3. The quadrature modulator according to claim 2, wherein the third to third multiplication circuits are Gilbert cell type multiplication circuits, and the synthesis circuit is configured by a differential amplifier circuit and a buffer emitter follower circuit. .