JPH10209813A - Unbalanced/balanced conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the deterioration of the balancing of a balanced signal even with a high frequency by using the plural balanced signal of an active balun in which a terminal for controlling the DC currents of an active element is used as an input terminal, and terminals from and to which the DC currents are flowed are used as balanced output terminals as the differential input of a differential amplifier circuit. SOLUTION: An FET Q1 being an active element, capacitors C1-C3, and resistance R1-R3 constitute an active balun 7 being an unbalanced/balanced conversion circuit. The gate of the FET Q1 being a terminal for controlling DC currents is used as an input terminal, and the drain and source being terminals from and to which the DC currents are flowed are used as balanced output terminals. Also, FET Q2 and Q3, capacitors C2-C5, and resistances R4-R9 constitute a differential amplifier circuit 8. Then, the two balanced output terminals of the active balun 7, that is, the drain and source of the FET Q1 are connected with the differential input terminal of the differential amplifier circuit 8, and the two balanced signals of the active balun 7 are used as the differential input of the differential amplifier circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an unbalanced-balanced conversion circuit, and more particularly to an unbalanced-balanced conversion circuit used for a quadrature modulator.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional unbalanced-balanced conversion circuit. In FIG. 4, the unbalanced-balanced conversion circuit 10
Is one in which one of the balanced input terminals of the differential amplifier circuit is grounded at a high frequency. The unbalanced signal input terminal 11, the balanced signal output terminals 12 and 13, the power supply terminal 14, and the bias terminal 1
5. FETs Q11, Q12 and Q1 as active elements
3, capacitors C11, C12, C13 and C14,
Resistors R11, R12, R13, R14, R15 and R
16.

The power supply terminal 14 is divided into two, and is connected to the drain, which is the first terminal into which the DC current of the FETs Q11 and Q12 flows, through the resistors R11 and R12, respectively, and the DC current of the FETs Q11 and Q12 flows out. The source, which is the second terminal, is connected to the FET Q13
Connected to the drain of The source of the FET Q13 and the gate which is the third terminal for controlling the DC current are grounded via the resistors R13 and R14, respectively. The unbalanced signal input terminal 11 is connected to the gate of the FET Q11 via a capacitor C11, and the bias terminal 15 is also connected to the gate of the FET Q11 via a resistor R15. The gate of the FET Q11 is connected to the gate of the FET Q12 via a resistor R16, and the gate of the FET Q12 is grounded via a capacitor C14. The drains of the FETs Q11 and Q12 are connected to balanced signal output terminals 12 and 13 via capacitors C12 and C13, respectively.

In the thus-configured unbalanced-balanced conversion circuit 10, the FET Q13 and the resistors R13 and R14 form a constant current circuit. Therefore, the current flowing through the FET Q13, that is, the sum of the currents flowing through the FETs Q11 and Q12 becomes constant.

When an unbalanced signal is input from the unbalanced signal input terminal 11 to the FET Q11 via the capacitor C11, a current corresponding to the amplitude of the unbalanced signal flows from the power supply terminal 14 through the resistor R11 and the FET Q11. Fet
Flow into Q13. At this time, the resistor R1
2 and FET Q12, the current is
However, since the sum of the currents flowing into the FET Q13 is constant, the currents flowing through the resistors R12 and Q12 are small when the currents flowing through the resistors R11 and Q11 are large, and large when the currents flowing through the resistors R11 and Q11 are small. As a result, the voltages at the drains of the FETs Q11 and Q12 also have an opposite phase relationship, and are output to the balanced signal output terminals 12 and 13 as balanced signals via the capacitors C12 and C13, respectively. Here, the balanced signal output from the balanced signal output terminal 12 has a phase opposite to that of the input unbalanced signal, and the balanced signal output from the balanced signal output terminal 13 has the same phase as the input unbalanced signal.

[0006]

However, in the conventional example shown in FIG. 4, the output terminal 12 is connected to the FET Q11.
Between the source of the FET Q11 and the FET Q12 or the FET Q13 from the source terminal of the FET Q11. It can be regarded as the output of the direct coupling circuit of the common gate circuit. When the frequency of the unbalanced signal is low, there is no problem because the gains of the two circuits are equal, but as the frequency of the unbalanced signal increases, the FE increases.
The influence of parasitic components such as the stray capacitance of the inside of TQ11 and Q12 and its peripheral circuit increases, and the gain of both changes.
As a result, there is a problem that the phase balance (degree of balance) of the balanced signals output from the two balanced signal output terminals is deteriorated. This is a fatal problem for an unbalanced-balanced conversion circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an unbalanced-balanced conversion circuit in which the balance of a balanced signal is hardly degraded even at a high frequency.

[0008]

In order to achieve the above object, an unbalanced-balanced conversion circuit according to the present invention comprises a first terminal into which a DC current flows, and a second terminal through which the DC current flows. An unbalanced-balanced conversion circuit using an active element having a third terminal for controlling the direct current, wherein the third terminal of the active element is an input terminal, and the first terminal and the second terminal An active balun having terminals as balanced output terminals, and an active balun having the third terminals as differential input terminals.
A differential amplifier circuit configured by connecting the second terminals of the two active elements and the first terminals of the one active element acting as a constant current source to each other; An output terminal is connected to the two differential input terminals of the differential amplifier circuit.

With this configuration, according to the unbalanced-balanced conversion circuit of the present invention, it is possible to improve the balance of the balanced signal output even at a high frequency.

[0010]

FIG. 1 shows an embodiment of an unbalanced-balanced conversion circuit according to the present invention. In FIG. 1, an unbalanced-balanced conversion circuit 1 includes an unbalanced signal input terminal 2, balanced signal output terminals 3 and 4, a power supply terminal 5, a bias terminal 6, FETs Q1, Q2 and Q3 as active elements, a capacitor C1,
C2, C3, C4 and C5, resistors R1, R2, R3,
It is composed of R4, R5, R6, R7, R8 and R9.

The power supply terminal 5 is divided into three, one of which is a first terminal into which a direct current of the FET Q1 flows via a resistor R1.
The source, which is the second terminal from which the direct current of the FET Q1 flows out, is grounded via the resistor R2. The gate, which is the third terminal for controlling the direct current of the FET Q1, is connected to the unbalanced signal input terminal 2 via the capacitor C1, and is grounded via the resistor R3. The drain and source of the FET Q1 are connected to the FE via the capacitors C2 and C3, respectively.
Connected to the gates of TQ2 and Q3.

The remaining two power supply terminals 5 divided into three are:
FETs Q2 and Q3 are connected to the drains of FETs Q2 and Q3 via resistors R6 and R7, respectively, and the sources of FETs Q2 and Q3 are both connected to the drain of FET Q4. The source and gate of FET Q4 are grounded via resistors R8 and R9, respectively. The gates of the FETs Q2 and Q3 are connected to the bias terminal 6 via the resistors R4 and R5, respectively. And FET
The drains of Q2 and Q3 are respectively connected to a capacitor C4
And C5 are connected to the balanced signal output terminals 3 and 4.

Here, the FET Q1, the capacitors C1, C
2 and C3, and resistors R1, R2 and R3 constitute an active balun 7 which is an unbalanced-balanced conversion circuit using one active element. FETs Q2 and Q2
3, capacitors C2, C3, C4 and C5, resistor R
4, R5, R6, R7, R8 and R9 constitute a differential amplifier circuit 8. Among them, C2 and C3 are shared by both.

In the unbalanced-balanced conversion circuit 1 configured as described above, the FET Q4 and the resistors R8 and R9 constitute a constant current circuit. Therefore, the current flowing through the FET Q4, that is, the sum of the currents flowing through the FETs Q2 and Q3 becomes constant.

Here, when an unbalanced signal is input from the unbalanced signal input terminal 2 to the active balun 7, a signal having a phase opposite to that of the unbalanced signal is supplied to the differential amplifier circuit 8 via the capacitor C2.
, A signal in phase with the unbalanced signal is input to the gate of the FET Q3 of the differential amplifier circuit 8 via the capacitor C3.

When a balanced signal having an opposite phase to the unbalanced signal is input to the FET Q2 of the differential amplifier circuit 8, a current corresponding to the amplitude of the balanced signal is supplied from the power supply terminal 5 to the resistor R6 and the FET Q2.
Through the FET Q4. Also, the differential amplifier circuit 8
When a balanced signal having the same phase as the unbalanced signal is input to the FET Q3, a current corresponding to the amplitude of the balanced signal similarly flows into the FET Q4 from the power supply terminal 5 through the resistor R7 and the FET Q3.

At this time, since signals having phases opposite to each other are input to the FETs Q2 and Q3, the current flowing therethrough also has an AC component having a phase relationship opposite to each other.
Since the current flows into the constant current circuit constituted by the ETQ4, the sum always becomes a constant value. As a result, FETs Q2 and Q3
Have the opposite phase relationships to each other, and are output to balanced signal output terminals 3 and 4 as balanced signals via capacitors C4 and C5, respectively. Here, the balanced signal output from the balanced signal output terminal 3 has the same phase as the input unbalanced signal, and the balanced signal output from the balanced signal output terminal 4 has the opposite phase to the input unbalanced signal.

As described above, the two FEs of the differential amplifier circuit 8
TQ2 and Q3 have the same operating conditions different from the conventional example, and signals having phases opposite to each other are always input to the gates. For this reason, even if the frequency of the unbalanced signal increases and the influence of the parasitic component increases, it is possible to stably operate as an unbalanced-balanced conversion circuit without disturbing the balance between the two.

FIGS. 2 and 3 show the frequency characteristics of the level difference and the phase difference of the balanced signal in the unbalanced-balanced conversion circuit 1 of the present invention and the conventional unbalanced-balanced conversion circuit 10, respectively.
In FIG. 2, a is a conventional unbalanced-balanced conversion circuit 10 operating at 1.5 GHz, which is the operating frequency of a digital mobile phone, and b is two balanced signals of the unbalanced-balanced conversion circuit 1 of the present invention. 2 shows the frequency characteristic of the level difference. In FIG. 3, c indicates the frequency characteristic of the conventional unbalanced-balanced conversion circuit 10, and d indicates the frequency characteristic of the phase difference between the two balanced signals of the unbalanced-balanced conversion circuit 1 of the present invention.

2 and 3, the conventional unbalanced-balanced conversion circuit 10 has a frequency of 3G which is twice the operating frequency.
While the maximum level shift of about 2 dB occurs at Hz, the level does not deviate even at 3 GHz where the shift is maximum in the unbalanced-balanced conversion circuit 1 of the present invention.
Also, regarding the phase, the conventional unbalanced-balanced conversion circuit 10
In the unbalanced-balanced conversion circuit 1 of the present invention, there is almost no shift at the same 1.7 GHz, and the shift is the largest. It can be seen that the deviation is about 3 degrees even at 3 GHz.

In the above description, an FET is used as an active element, but the same operation and effect can be obtained by using another active element such as a vacuum tube or a bipolar transistor.

[0022]

According to the unbalanced-balanced conversion circuit of the present invention, an active balun and a differential amplifier circuit are combined, and two balanced signals of the active balun are used as differential inputs of the differential amplifier circuit. Even at a high frequency, an unbalanced-balanced conversion circuit with little deterioration of the balance of the balanced signal can be configured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of an unbalanced-balanced conversion circuit according to the present invention.

2 is a diagram showing a level difference of a balanced signal of an unbalanced-balanced conversion circuit in the embodiment of FIG. 1 and the conventional example of FIG. 4;

FIG. 3 is a diagram showing a phase difference between balanced signals of an unbalanced-balanced conversion circuit in the embodiment of FIG. 1 and the conventional example of FIG. 4;

FIG. 4 is a circuit diagram showing an example of a conventional unbalanced-balanced conversion circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Unbalanced-balanced conversion circuit 2 ... Unbalanced signal input terminal 3, 4 ... Balanced signal output terminal 5 ... Power supply terminal 6 ... Bias terminal 7 ... Active balun 8 ... Differential amplifier circuit Q1, Q2, Q3, Q4 ... FET C1, C2, C3, C4, C5 ... capacitors R1, R2, R3, R4, R5, R6, R7, R8, R
9 ... resistance

Claims (1)

[Claims] 1. An unbalanced-balanced conversion using an active element having a first terminal into which a direct current flows, a second terminal through which the direct current flows, and a third terminal for controlling the direct current. In the circuit, an active balun having the third terminal of the active element as an input terminal, the first terminal and the second terminal configured as balanced output terminals, and the third terminal as a differential input terminal And a differential amplifier circuit configured by connecting the second terminals of the two active elements to each other and the first terminal of one of the active elements serving as a constant current source. An unbalanced-balanced conversion circuit, wherein the balanced output terminal is connected to two differential input terminals of the differential amplifier circuit.