JPH07235552A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a gate reverse breakdown voltage as well as to make a spring current inhibit efficiently in a semiconductor device by a method wherein the device is formed into a constitution wherein a semiconductor layer brought into a low resistance state is used as a gate layer, a high-resistance semiconductor layer and semiconductor layers, which are used as a channel layer and source/drain layers, are formed in such a way as to cover this semiconductor layer and moreover, a protective film is formed on the semiconductor layer, which is used as the source/drain layers. CONSTITUTION:An N<+> GaAs semiconductor layer 3 brought into a low resistance state is used as a gate layer and an I-type AlGaAs high-resistance semiconductor layer 4 is formed in such a way as to cover this layer 3. The form of the side parts of the layer 3 is formed into a forward tapered form. Moreover, an N-type GaAs semiconductor layer 5, which is used as a channel layer, is formed on the layer 4, an N<+> GaAs semiconductor layer 6, which is used as source/drain layers and is brought into a low resistance state, is formed on the layer 5 and on both sides of the layer 5 and an SiN protective film 9, which has the functions of a passivation film and a buffer layer, is formed on the layer 6. As a result, a band gap in the film 9 can be made high and a current between a drain electrode 7 and a source electrode 8 can be efficiently made to flow.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, it can be applied to a high frequency operation device using a compound semiconductor, and in particular, it can efficiently increase the reverse breakdown voltage of the gate. The present invention relates to a semiconductor device capable of efficiently suppressing a current flowing out and realizing a sufficiently high voltage operation.

In recent years, devices using compound semiconductors are
It has been widely used in the microwave communication field. In particular, in mobile communication in the field of microwave communication, GaAsFET is used instead of a silicon device for a partner telephone and its base station because it can obtain high linearity with low power consumption. Also, the current GaAs
The maximum operating voltage of the FET is as small as about 10V, but if it can be operated at 12V or more, which is the power supply voltage of the automobile battery, it can be used in automobile telephones. Therefore, it is necessary to operate the GaAsFET at a high voltage these days. Is increasing.

[0003]

2. Description of the Related Art FIG. 5 is a sectional view showing the structure of a conventional GaAs FET. In FIG. 5, 101 is a GaAs substrate, and 102 is an i formed on the GaAs substrate 101.
-GaAs buffer layer, 103 is i-GaAs
It is an n-GaAs channel layer formed on the buffer layer 102. Reference numerals 104 and 105 denote a drain electrode and a source electrode respectively formed on the n-GaAs channel layer 103, and a gate electrode 106 formed on the n-GaAs channel layer 103 between the drain electrode 104 and the source electrode 105. And 107 is a protective film formed so as to cover the gate electrode 106.

Here, the gate electrode 106 is a Schottky contact, and the source electrode 105 and the drain electrode 104 are ohmic contacts. In this conventional GaAs FET, a bias voltage is applied from the drain electrode 104 to the source electrode 105, and the gate electrode 10
When a voltage is applied to 6 as well to input a high frequency signal, a depletion layer is generated at the Schottky junction between the gate electrode 106 and the n-GaAs channel layer 103, and the thickness of the depletion layer is adjusted by adjusting the voltage applied to the gate electrode 106. By doing
It has the advantage that the amount of current flowing between the drain electrode 104 and the source electrode 105 can be modulated, and that it is superior to the Si-based device in high-frequency characteristics.

However, this conventional GaAs FET
Then, if the gate length is reduced, the high frequency characteristics should be improved, but the width of the depletion layer is reduced and the distance between the drain electrode 104 and the source electrode 105 is shortened, so that the electric field is strengthened. I-Ga
A current flowing out of the As buffer layer 102 causes a problem that the gain is lowered and the high frequency characteristic is deteriorated. For this reason, the desired high frequency characteristics may not be obtained despite the reduction of the gate length.

Further, this conventional GaAs FET has an n-type
Metal gate electrode 1 directly on the GaAs channel layer 103
However, since the reverse breakdown voltage of the gate electrode 106 is low, the same problem as described above occurs. Therefore, in this conventional GaAsFET, when a high voltage is applied to the drain electrode 104 to operate, a large gate current flows, and at the same time, a large current flowing out to the i-GaAs buffer layer 102, which should not flow, due to a high electric field. However, there is a problem that the high-frequency characteristics are deteriorated due to the flow.

Therefore, in order to solve the above problem, the conventional GaAs FET has an n-GaAs channel layer 103.
There is known a structure in which the upper and lower sides of the are sandwiched by i-AlGaAs layers 110 and 111. In this GaAs FET,
Since the lower part of the n-GaAs channel layer 103 is composed of the i-AlGaAs layer 110 having a wider bandgap than in the case of FIG. 5, it is possible to make it difficult for carriers to enter the i-AlGaAs layer 110 and also the n-GaAs channel layer 103.
I-AlG having a wider band gap than the case of FIG.
Since it is composed of the aAs layer 111, the reverse breakdown voltage of the gate can be reduced. Therefore, even if the gate length is reduced, the current flowing out to the buffer layer 110 can be made smaller than that in the case of FIG. 5, so that the deterioration of the high frequency characteristics can be suppressed.

[0008]

However, the conventional GaAsFET according to FIG. 6 described above has an advantage that it can operate at a higher voltage than the conventional structure shown in FIG. 1
When operated by applying a high voltage of 2 to 14 V, i-Al
The band gap of GaAs is 1.6 to 1.7 eV, and G
Since the band gap of aAs is not so large as 1.4 eV, the same problem as in FIG. 5 eventually arises, and there is a problem that it is still insufficient to perform a sufficiently high voltage operation.

Further, in this conventional GaAs FET, n
-I-AlGaAs layer 1 on -GaAs channel layer 103
Since a series resistance component is generated because 11 is formed,
To obtain a sufficiently low ohmic contact resistance, n
⁺ Implantation layer 112 must be formed, and n ⁺ implantation layer 1
There is a problem that the characteristics are easily deteriorated by high-temperature activation annealing when forming 12.

[0010] Therefore, the present invention makes it possible to increase efficiently the gate reverse breakdown voltage can be suppressed efficiently gushing Shi currents, except that it is possible to realize a sufficient high voltage operation, n ⁺ implantation An object of the present invention is to provide a semiconductor device which can obtain a sufficiently low ohmic contact resistance without forming a layer and can prevent characteristic deterioration due to high temperature activation annealing when forming an n ⁺ implantation layer. And

[0011]

The invention according to claim 1 is
A semi-insulating substrate, a first semiconductor layer formed on the semi-insulating substrate, which is non-doped or is lightly doped with impurities, and a source / source layer which is selectively formed on the first semiconductor layer The second semiconductor layer, which is formed by dividing the drain region and is highly doped with impurities, and the first semiconductor layer are joined in the source / drain region, and are joined in the gate region to the second semiconductor layer. A third semiconductor layer formed by non-doping or lightly doping with impurities;
A fourth semiconductor layer formed on the third semiconductor layer, and a fifth high-concentration impurity-doped region formed on the fourth semiconductor layer so as to be divided into source / drain regions. Formed on a semiconductor layer, a source / drain electrode formed by ohmic contact formed on the fifth semiconductor layer, and at least one of the fourth semiconductor layer and the fifth semiconductor layer It is characterized by having a protective film.

According to a second aspect of the present invention, in the first aspect of the invention, the second semiconductor layer side portion has a forward tapered shape. According to a third aspect of the invention, in the first and second aspects of the invention, the first and third semiconductor layers have a band gap higher than at least the second and fourth semiconductor layers. It is what

According to a fourth aspect of the present invention, in the first to third aspects of the present invention, the first semiconductor layer is made of undoped or n ⁻ type AlGaAs, and the second semiconductor layer is made of n ⁺ type. GaAs, the third semiconductor layer is undoped or n ⁻ type AlGaAs, the fourth semiconductor layer is n type GaAs, and the fifth semiconductor layer is n ⁺ type GaAs. It is characterized by.

According to a fifth aspect of the present invention, in the first to fourth aspects of the invention, the impurity concentration of the first semiconductor layer is 5 × 10 ¹⁶ cm ¹⁷ or less, and the second semiconductor layer has an impurity concentration of 5 × 10 ¹⁶ cm ¹⁷ or less. The impurity concentration is 1 × 10 ¹⁸ cm ¹⁸ or more, the impurity concentration of the third semiconductor layer is 5 × 10 ¹⁶ cm ¹⁷ or less, and the impurity concentration of the fourth semiconductor layer is 5 × 10 ^{18.
It is 16} or more and 1 × 10 ¹⁸ cm ¹⁸ or less, and the impurity concentration of the fifth semiconductor layer is 1 × 10 ¹⁸ cm ¹⁸ or more.

[0015]

1 and 2 are explanatory views of the principle of the present invention, FIG. 1 is a sectional view showing the structure of a semiconductor device according to the present invention, and FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. . Figure 1,
In 2, 2 is a semi-insulating substrate such as GaAs,
Is a semiconductor layer such as i-AlGaAs formed on the semi-insulating substrate 1 and doped with impurities at a low concentration, and 3 is formed on the semiconductor layer 2 and divides the source / drain regions. , A semiconductor layer of n ⁺ GaAs or the like, which is doped with a high concentration of impurities, to serve as a gate layer, and 4 is a semiconductor layer 3 which is joined to the semiconductor layer 2 in the source / drain region and serves as a gate layer in the gate region.
Is a semiconductor layer of i-AlGaAs or the like which is formed so as to be bonded so as to cover the non-doped or lightly doped impurity.

Reference numeral 5 denotes a semiconductor layer such as n-GaAs, which is a channel layer formed on the semiconductor layer 4 by doping impurities, and 6 is a channel layer which is divided into source / drain regions. Highly-concentrated impurity-doped semiconductor layers formed on the semiconductor layer 5 are semiconductor layers of n ⁺ -GaAs or the like, and 7 and 8 are source / drain layers.
A drain electrode 7 and a source electrode 8 formed by ohmic contact formed on the semiconductor layer 6 to be a drain layer, and 9 are formed on the semiconductor layer 5 to be a channel layer and the semiconductor layer 6 to be a source / drain layer. And 11 and 11 are an active region and a gate electrode, respectively. The protective film 9 may be formed on at least one of the semiconductor layer 5 and the semiconductor layer 6.

As shown in FIG. 2, in the semiconductor device of the present invention, the gate electrode in the active region 10 is formed below the channel layer here, but by removing the channel layer outside the active region 10. It is configured by taking ohmic contact with the gate electrode 11. In the present invention,
Since the low resistance n ⁺ -GaAs semiconductor layer 3 is used for the gate layer and the i-AlGaAs high resistance semiconductor layer 4 is formed so as to cover the semiconductor layer 3, the reverse breakdown voltage of the gate is efficiently improved. Can be made. Moreover, since the side portion of the n ⁺ -GaAs semiconductor layer 3 serving as the gate layer is formed in the forward taper shape, the radius of curvature can be made larger than that of the vertical shape, and the electric field is softened to improve the breakdown voltage. be able to.

Further, in the present invention, the n-GaAs semiconductor layer 5 serving as a channel layer is formed on the i-AlGaAs high resistance semiconductor layer 4, and the source / drain layers serving as the source / drain layers are formed on both sides of the n-GaAs semiconductor layer 5. The n ⁺ -GaAs semiconductor layer 6 having resistance is formed, and n-GaAs serving as a channel layer is further formed.
For example, SiN having a bandgap of about 5 eV having a function of passivation and a buffer layer on the semiconductor layer 5.
The protective film 9 is formed and configured.

Therefore, the SiN protective film 9 is formed of i-AlG.
Since the band gap can be made higher than that of aAs, even if the drain voltage is increased, the current between the drain electrode 7 and the source electrode 8 does not pass through the i-AlGaAs semiconductor layer 4 and the n ⁺ -GaAs semiconductor Layer 6 and n-GaA
It is possible to efficiently flow through only the s semiconductor layer 5.
Therefore, it is possible to efficiently improve the reverse breakdown voltage of the gate and efficiently suppress the current flowing out, so that it is possible to sufficiently suppress the leakage current due to the high voltage operation and realize a sufficiently high voltage operation. You can

Next, in the present invention, i-AlGaA is used.
It is preferable that the s semiconductor layer 2 and the i-AlGaAs semiconductor layer 4 have a band gap higher than that of at least the n ⁺ -GaAs semiconductor layer 3 and the n ⁺ -GaAs semiconductor layer 6, and in this case, the i-AlGaAs semiconductor layer. The drain electrode 7 is formed in the layer 2 and the i-AlGaAs semiconductor layer 4.
Also, it is possible to make it difficult for carriers that travel between the source electrodes 8 to enter.

Next, in the present invention, the semiconductor layer 2 is removed.
N-dope or n^-Type AlGaAs, the semiconductor layer 3
N⁺Type GaAs, the semiconductor layer 4 is non-doped or
Is n ^-Type AlGaAs, and the semiconductor layer 5 is an n-type Ga
The semiconductor layer 6 is made of As.⁺Type GaAs
Therefore, it is advantageous for high-speed operation having the effects of the present invention.
It is possible to realize an N-channel GaAs FET.

Next, in the present invention, the defect of the semiconductor layer 2 is
Considering that the pure substance concentration functions as a buffer layer
Then 5 × 10¹⁶cm¹⁷The following is preferable, and the semiconductor layer
Considering that the impurity concentration of 3 functions as a gate layer
Considering 1 x 10¹⁸cm¹⁸The above is preferable, and the semiconductor
The impurity concentration of the layer 4 should improve the reverse breakdown voltage of the gate.
Considering and¹⁶cm¹⁷The following are preferred,
The impurity concentration of the semiconductor layer 5 depends on the drain electrode 7 and the source electrode.
It functions as a channel layer that allows carriers to travel between poles 8.
5 × 10 considering that¹⁸1 x 10 or more¹⁸cm
¹⁸The following is preferable, and the impurity concentration of the semiconductor layer 6 is
Source / contact with the in electrode 7 and the source electrode 8
Considering to function as a drain layer, 1 × 1
0¹⁸cm ¹⁸The above is suitable. It will be the channel layer
The upper limit of the impurity concentration of the semiconductor layer 5 is 1 × 10¹⁸cm¹⁸
Is preferable if it is set higher than this
This is because the pressure resistance between rains deteriorates.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. 3 and 4 are views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. The illustrated example is an n-channel type GaA.
This is the case when applied to sFET. 3 and 4, the same symbols as those in FIGS. 1 and 2 indicate the same or corresponding portions. In the present embodiment, first, undoped i-AlGaAs (mixed crystal ratio 0.2) is grown to 5000 angstroms on the GaAs semi-insulating substrate 1 by the MBE method to form the i-AlGaAs semiconductor layer 2, and the i-AlGaAs semiconductor layer 2 is formed. On the AlGaAs semiconductor layer 2, n ⁺ -GaAs having an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ is added.
After the growth of 00 angstroms, n ⁺ -GaAs is etched by plasma etching using CCl ₂ F ₂ gas using the gate layer forming resist 21 as a mask to form the n ⁺ -GaAs semiconductor layer 3 to be the gate layer (Fig. 3 (a)). At this time, it goes without saying that the etching stops on the surface of the i-AlGaAs semiconductor layer 2 due to the difference in the etching selection ratio.

Next, after removing the resist 21, the non-doped i layer is formed again by the MBE method so as to cover the semiconductor layer 3.
-AlGaAs (mixed crystal ratio 0.2) is 500 angstrom and n-GaAs with an impurity concentration of 1.5 × 10 ¹⁷ cm ^-3
1500 angstrom, and impurity concentration 1 × 10
¹⁸ cm ⁻³ of n ⁺ -GaAs is sequentially grown to 5000 angstroms to form an i-AlGaAs semiconductor layer 4, an n-GaAs semiconductor layer 5 serving as a channel layer, and an n ⁺ -GaAs.
The semiconductor layer 6 is formed (FIG. 3B).

Next, the surface of the corresponding n ⁺ -GaAs semiconductor layer 6 is exposed on the n ⁺ -GaAs semiconductor layer 3 serving as the gate layer by a planarization technique using the resist 22, and the surface of the hydrofluoric acid or hydrogen peroxide system is used. Wet etching or CC
The corresponding n ⁺ -GaAs semiconductor layer 6 is etched on the semiconductor layer 3 by plasma etching using l ₂ F ₂ gas to expose the n-GaAs semiconductor layer 5 to be the channel layer (FIG. 3C). After that, patterning is performed so that the active region is protected by a resist, and C is exposed outside the active region.
I by plasma etching using Cl ₂ F ₂ gas
-Etching is performed until the AlGaAs semiconductor layer 4 is exposed.

Next, the resist 22 is removed, and SiN is plasma-enhanced to 1000 angstroms Si.
After 3000 Å of O ₂ is deposited by atmospheric pressure CVD, the source / drain and gate regions are opened. Then, using the resist 24 as a mask, SiO ₂ is wet-etched with a hydrofluoric acid aqueous solution, and SiN is dry-etched with CF ₄ : O ₂ gas to obtain SiN.
The protective film 9 is formed (FIG. 4A). At this time, SiO ₂
The film 23 is formed smaller than the width of the SiN protective film 9, and the i-AlGaAs semiconductor layer 4 in the opened gate region is removed by a hydrofluoric acid aqueous solution.

Then, the AuGe / Ni / Au is 400 /
The source / drain electrodes 7 and 8 are formed by performing 100/3000 angstrom vapor deposition, removing the resist 24 by lift-off, and then alloying at 425 ° C. to form n-channel type GaAsF as shown in FIG. 4B.
You can get ET. Thus, in this embodiment,
Since the n ⁺ -GaAs semiconductor layer 3 having a low resistance is used as the gate layer and the i-AlGaAs high resistance semiconductor layer 4 is formed so as to cover the semiconductor layer 3, it is possible to efficiently improve the reverse breakdown voltage of the gate. it can. Moreover, since the side portion of the n ⁺ -GaAs semiconductor layer 3 serving as the gate layer is formed in the forward taper shape, the radius of curvature can be made larger than that in the vertical shape, and the electric field can be softened and the breakdown voltage can be improved. .

Further, in this embodiment, the n-GaAs semiconductor layer 5 serving as the channel layer is formed in the i-AlGaAs high resistance semiconductor layer 4, and the source / drain layers serving as the source / drain layers are formed on both sides of the n-GaAs semiconductor layer 5. The n ⁺ -GaAs semiconductor layer 6 having resistance is formed, and n-GaAs serving as a channel layer is further formed.
For example, SiN having a bandgap of about 5 eV having a function of passivation and a buffer layer on the semiconductor layer 5.
A protective film 9 is formed and configured. Therefore, the SiN protective film 9 can increase the bandgap more efficiently than i-AlGaAs, so that even if the drain voltage is increased, the current between the drain electrode 7 and the source electrode 8 is i-A.
It is possible to flow through only the n ⁺ -GaAs semiconductor layer 6 and the n-GaAs semiconductor layer 5 without passing through the 1GaAs semiconductor layer 4. Therefore, the reverse breakdown voltage of the gate can be improved and the current flowing out can be efficiently suppressed, so that the leakage current due to the high voltage operation can be sufficiently suppressed, and a sufficiently high voltage operation can be realized. .

[0029]

According to the present invention, the reverse breakdown voltage of the gate can be efficiently increased, the current flowing out can be efficiently suppressed, and a sufficiently high voltage operation can be realized. ⁺ without forming the injection layer can be obtained sufficiently low ohmic contact resistance, there is an effect that it is possible to prevent the occurrence of performance deterioration due to high temperature activation annealing for forming the n ⁺ implanted layer.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating the principle of the present invention.

FIG. 3 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a sectional view showing the structure of a conventional GaAs FET.

FIG. 6 is a sectional view showing the structure of a conventional GaAs FET.

[Explanation of symbols]

1 Semi-Insulating Substrate 2, 3, 4, 5, 6 Semiconductor Layer 7 Drain Electrode 8 Source Electrode 9 Protective Film 10 Active Region 11 Gate Electrode 21, 22, 24 Resist 23 SiO ₂ Film

Claims (5)

[Claims] 1. A semi-insulating substrate (1), a non-doped or low-concentration impurity-doped first semiconductor layer (2) formed on the semi-insulating substrate (1), and the first semiconductor layer (2). Second semiconductor layer (3) selectively formed on the semiconductor layer (2), dividing the source / drain regions, and doped with a high concentration of impurities, and the first semiconductor layer (2). ) With a third semiconductor layer (4) which is formed by joining in the source / drain region and joining in the gate region to the second semiconductor layer (3) and which is non-doped or lightly doped with impurities. , A fourth semiconductor layer (5) formed on the third semiconductor layer (4) and a high layer formed on the fourth semiconductor layer (5) so as to be divided into source / drain regions. A fifth semiconductor layer (6) doped with a high concentration of impurities, and the fifth semiconductor layer (6) Comprising taking an ohmic junction formed on the source / drain electrode and (7,8), the fourth
2. A semiconductor device comprising: a semiconductor layer (5) and a protective film (9) formed on at least one of the fifth semiconductor layer (6). 2. The shape of the side portion of the second semiconductor layer (3) is
The semiconductor device according to claim 1, wherein the semiconductor device has a forward tapered shape. 3. The first and third semiconductor layers (2, 4) are
The semiconductor device according to claim 1, wherein the semiconductor device has a band gap higher than that of at least the second and fourth semiconductor layers (3, 5). 4. The first semiconductor layer (2) is made of undoped or n ⁻ type AlGaAs, the second semiconductor layer (3) is made of n ⁺ type GaAs, and the third semiconductor layer ( 4) is undoped or n ⁻ type AlGaAs, the fourth semiconductor layer (5) is n type GaAs, and the fifth semiconductor layer (6) is n ⁺ type GaAs. The semiconductor device according to any one of claims 1 to 3. 5. The impurity concentration of the first semiconductor layer (2) is 5 × 10 ¹⁶ cm ¹⁷ or less, and the impurity concentration of the second semiconductor layer (3) is 1 × 10 ¹⁸ cm ¹⁸ or more. And
The impurity concentration of the third semiconductor layer (4) is 5 × 10 ¹⁶
cm ¹⁷ or less, and the impurity concentration of the fourth semiconductor layer (5) is 5 × 10 ¹⁶ or more and 1 × 10 ¹⁸ cm ¹⁸ or less,
The impurity concentration of the fifth semiconductor layer (6) is 1 × 10 ^18.
The semiconductor device according to claim 1, wherein the semiconductor device has a cm ¹⁸ or more.