JPH07226500A - Preparation of mos transistor - Google Patents

Abstract

PURPOSE: To provide the method of manufacturing a p-type LDD-MOS transistor which employs a diffusion method utilizing an oxide film instead of an ion implantation method and can form lightly doped p<-> -type source/drain regions with very thin junctions. CONSTITUTION: A B-doped p<+> -type polysilicon film is formed an a gate oxide film 33 formed on an n-type semiconductor substrate 31. An insulating film is formed on the poly-Si film and a photoresist film is applied to the surface of the insulating film and patterned to expose the insulating film to etch the insulating film by using the patterned photoresist film as a mask. Then F ions are implanted into the p<+> -type poly-Si film. The remaining resist film is removed and a lightly doped p<-> -type source/drain regions 41 are formed by a heat treatment. The p<+> -type poly-Si film is etched by using the insulating film as a mask to form a gare 43, the insulating film is removed and an oxide film is deposited over the whole surface of the substrate and spacers 45 are formed on the side walls of the gate by anisotropic etching. P-type impurity ions are implanted into the substrate to form heavily doped p<+> -type source/drain regions 47.

Description

Detailed Description of the Invention

[0001]

The present invention relates relates to a method of manufacturing a MOS transistor, in particular a very low concentration can be applied during manufacture of the transistor of small size (or 256M grade) p ^-
LD with very shallow junction in source / drain region
The present invention relates to a method for manufacturing a DMOS transistor.

[0002]

2. Description of the Related Art In a P-type MOS transistor, a high electric field is formed at an edge portion of a gate electrode, hot carriers are generated by the high electric field, and the generated hot carriers are trapped in a gate insulating film. Charge trap or interface state (interf)
There is a problem that not only the characteristics of the MOS transistor are deteriorated due to the occurrence of the ace state) but also the life is shortened.

A P-type MOS transistor having an LDD structure has been proposed to reduce the hot carrier effect. FIG. 1 shows a manufacturing process of a conventional LDD PMOS transistor. As shown in FIG. 1A, a gate oxide film 13 is formed on the n-type semiconductor substrate 11, and the gate oxide film 13 is formed.
A p ⁺ type polysilicon film doped with a p type impurity is applied on the entire surface and patterned to form a gate 15. Using the gate 15 as a mask, B or BF ₂ is ion-implanted into the substrate at a low concentration to form a low-concentration p ⁻ source / drain region 17.

Next, as shown in FIG. 3B, an oxide film is deposited on the entire surface of the substrate and anisotropically etched to form a spacer 19 on the side wall of the gate 15. B or BF ₂ is ion-implanted at a high concentration into the substrate 11 by using the spacer 19 and the gate 15 as a mask to form a high concentration p ⁺ source / drain region 21.
To form a P-type LDD MOS transistor.

The LDD structure MOS transistor is
By reducing the high electric field applied to the drain region by the low-concentration p ⁻ source / drain region 17, deterioration of the characteristics of the device due to hot carriers was prevented, thereby improving the reliability of the device. For devices of 256M class and above,
When manufacturing an extremely small LDD MOS transistor, the p ^- source / drain region for removing the hot carrier effect is formed in a shallow junction having a depth of several hundred Å so that the short channel effect is not affected. I have to let you.

[0006]

However, it has been extremely difficult to manufacture a transistor of 256M class or higher by using the conventional LDD transistor manufacturing method utilizing the ion implantation method. That is, B or BF ₂ is mainly used as a p-type impurity to be ion-implanted for the p-type source / drain region, but since boron (B) has a very large diffusion constant, a conventional ion implantation method is used. As a result, it is difficult to form a low-concentration p ⁻ source / drain region of a shallow junction, which has a great adverse effect on the short channel effect of the device. The present invention is intended to solve the above-mentioned problems of the conventional technique. The diffusion method using an oxide film, which is not the usual ion implantation method, allows an extremely thin junction to have a low concentration p ^- source / drain region. It is an object of the present invention to provide a method for manufacturing a p-type LDD transistor capable of forming a semiconductor.

[0007]

In order to achieve the above object, according to the present invention, a step of forming a gate oxide film on an n-type semiconductor substrate, and a boron-doped p layer on the gate oxide film. forming a ⁺ -type polysilicon film, a step of exposing the step of applying an insulating film on the p ⁺ -type polysilicon film, an insulating film is patterned by applying a photoresist film on the insulating film, a photoresist Etching the insulating film using the film as a mask,
Ion implantation of fluorine ions with a p ⁺ type polysilicon film, removal of the remaining photoresist film, heat treatment to form a low concentration p ⁻ source / drain region, Etching the p ⁺ -type polysilicon film using the film as a mask to form a gate, and removing the insulating film,
A step of depositing an oxide film on the entire surface of the substrate and anisotropically etching it to form a spacer on the side wall of the gate, and ion-implanting a high concentration of p impurities into the substrate so that the source / drain regions of low concentration are adjacent to each other. Forming a high concentration p ⁺ source / drain region in the p-type LDD M
A method for manufacturing an OS transistor is provided.

[0008]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 2 to 5 show the p-type LDD MO of the present invention.
Referring to FIG. 2, which is a manufacturing process diagram of an S-transistor, an extremely thin gate oxide film 33 of 100 Å or less is formed on an n-type semiconductor substrate 31, and boron-doped p ⁺ poly is formed on the gate oxide film 33. A silicon film 35 is formed. The p ⁺ polysilicon film 35 acts as a diffusion source for forming a low concentration p ⁻ source / drain region,
A polysilicon film is applied on the gate oxide film 33, and then the polysilicon film is doped with boron.

As another method for forming the p ⁺ polysilicon film 35, there is a method using an n ⁺ polysilicon film. This is formed by forming an n ⁺ polysilicon film on the gate oxide film 33 and canceling the n-type impurities doped in the n ⁺ polysilicon film with BF ₂ to dope the remaining amount. After forming the p ⁺ polysilicon film 35, as shown in FIG. 3, applying an insulating film 37 on the p ⁺ polysilicon film 35. A photoresist film 39 is applied thereon and patterned to expose a part of the insulating film 37. A nitride film or a CVD oxide film is used as the insulating film 37. The exposed insulating film 37 is removed using the photoresist film 39 as a mask. At this time, the remaining portion is a portion where a gate is to be formed in a later process. This insulating film 37
Fluorine ions (F) are ion-implanted into the p ⁺ polysilicon film 35 using the mask as a mask. At this time, the dose amount of the fluorine ions to be ion-implanted is about twice that of the boron ions to be doped in the p ⁺ polysilicon film 35.

When the remaining photoresist film 39 is removed and a heat treatment process is performed, as shown in FIG. 4, the boron ions (B) doped in the p ⁺ polysilicon film 35 are transferred to the substrate through the gate oxide film 33. 31 to form a low concentration p ⁻ source / drain region 41. In the description, p ⁺ polysilicon film 35 to the ion implanted fluorine ions acts to facilitate the time of heat treatment process, boron ions from the p ⁺ polysilicon film 35 is diffused by intervening an oxide film.

Therefore, according to the present invention, impurities are diffused through a gate oxide film, which is not a general ion implantation method, and fluorine ions promote the diffusion of impurities, so that a shallow junction with a low junction is formed on the substrate as shown in FIG. The p ⁻ source / drain region 41 having the concentration is formed.

Further, as shown in FIG. 7, the present invention can obtain the characteristics of the limit voltage superior to the conventional one by the low concentration source / drain region of the shallow junction, thereby reducing the short channel effect. At this time, the junction depth of the low concentration p ⁻ source / drain region 41 is 500 Å or less.

Referring to FIG. 5, the p ⁺ polysilicon film 35 is patterned using the insulating film as a mask to form a gate 43. Then, the insulating film 37 is removed, and an oxide film is deposited on the entire surface of the substrate and anisotropically etched to form a spacer 45 on the side wall of the gate 43. Using the spacer 45 and the gate 43 as a mask, B or BF ₂ is ion-implanted into the substrate 31 to form a high concentration p ⁺ source / drain region 47.
To form a p-type LDD MOS transistor.

[0014]

As described above, according to the present invention, instead of the conventional ion implantation, the diffusion method through the oxide film and the fluorine ion for promoting the diffusion of boron ion are used to make the junction depth very shallow. Since a low concentration source / drain region can be formed, an excellent short channel effect can be obtained. Therefore, the reliability of the element can be improved, which is advantageous for manufacturing an element of 256M class or higher.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a conventional LDD PMOS transistor.

FIG. 2 is a manufacturing process diagram of an LDD PMOS transistor of the present invention.

FIG. 3 is a manufacturing process diagram of an LDD PMOS transistor of the present invention.

FIG. 4 is a manufacturing process diagram of an LDD PMOS transistor of the present invention.

FIG. 5 is a manufacturing process diagram of an LDD PMOS transistor of the present invention.

FIG. 6 is a doping profile of a p ⁻ impurity region at a low concentration according to the present invention.
It is a figure showing (file).

FIG. 7 is a diagram illustrating a limit voltage (Thre) according to a gate length of the present invention.
It is a figure which shows a hold voltage.

[Explanation of symbols]

31 n-type substrate 33 gate oxide film 35 p ⁺ polysilicon film 37 insulating film 39 photoresist film 41 low concentration p ^- source / drain region 43 gate 45 spacer 47 high concentration p ⁺ source / drain region

Claims (10)

[Claims] 1. A step of forming a gate oxide film (33) on an n-type semiconductor substrate (31), and boron-doped p on the gate oxide film (33).
⁺ Forming a polysilicon film (35), applying a p ⁺ -type polysilicon film (35) on the insulating film (37), a photoresist film on the insulating film (37) and (39) A step of applying and patterning to expose the insulating film (37), and the insulating film (3) using the photoresist film (39) as a mask.
7) a step of etching, a step of ion-implanting fluorine ions in the p ⁺ type polysilicon film (35) using the insulating film as a mask, a step of removing the remaining photoresist film (39), and a heat treatment step. Forming a low concentration p ^- source / drain region (41) and etching the p ⁺ -type polysilicon film (35) using the insulating film (37) as a mask to form a gate (43). Removing the insulating film (37), depositing an oxide film on the entire surface of the substrate, and performing anisotropic etching to form spacers (45) on the sidewalls of the gate (43); to form a high concentration p ⁺ source / drain regions (47) as a high concentration by ion implantation adjacent the low concentration of the source / drain regions (41) step Method for manufacturing a MOS transistor, characterized in that it comprises a and. 2. The MOS transistor according to claim 1, wherein the p ⁺ polysilicon film (35) acts as a diffusion source for forming a low concentration p ⁻ source / drain region (41). Production method. 3. The p ⁺ polysilicon film (35) is formed by applying a polysilicon film on the gate oxide film (33) and doping the polysilicon film with p-type impurities. A method of manufacturing a MOS transistor according to the item. 4. The method for manufacturing a MOS transistor according to claim 3, wherein the impurity doped in the p ⁺ polysilicon film (35) is boron ion. 5. The p ⁺ polysilicon film (35), the n ⁺ polysilicon film is coated on the gate oxide film (33), n ⁺
3. The M according to claim 2, wherein BF ₂ is formed in the polysilicon film by offsetting the n-type impurities doped in the n ⁺ polysilicon film and doping the remaining amount.
Manufacturing method of OS transistor. 6. A nitride film or C as the insulating film (37)
2. The method for manufacturing a MOS transistor according to claim 1, wherein one of the VD oxide films is used. 7. A low concentration p ⁻ source / drain region (4
1) is a p ⁺ polysilicon film (3
Impurities doped in 5) are gate oxide films (33)
The method for manufacturing a MOS transistor according to claim 1, wherein the MOS transistor is formed by being diffused through. 8. A low concentration p ⁻ source / drain region (4
Item 1) is a method for manufacturing a MOS transistor according to item 7, wherein the junction depth is 500 Å or less. 9. The dose of fluorine ions to be ion-implanted is the p-type doped in the p ⁺ polysilicon film (35).
M of the first item, which is twice as much as the type impurities.
Manufacturing method of OS transistor. 10. Fluorine ions play a role of promoting diffusion of p-type impurities doped in the p ⁺ polysilicon film (35) during a heat treatment process.
A method of manufacturing a MOS transistor according to the item.