JPH0721932B2 - Rotating body drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a rotary body drive device.

[Prior Art] In a conventional rotary body drive device, for example, a rotary body drive device such as a disk drive device in an electronic still camera, it is necessary to match the phase of a motor with a reference signal for regulating the operation timing of the entire camera. The drive control was performed. Therefore, it takes time to control the speed of the motor (phase control) using the phase, and the start-up characteristics of the camera are poor.

Further, as a method of controlling the phase, for example, π
It is possible to control the motor by synchronizing the phase of the FG (Frequency Generator) pulse with a delay. In this case, the controllable range of the phase is such that the delay of the phase of the FG pulse with respect to the reference signal is 0 or more and 2π or less. It will be limited.

However, the phase difference may exceed the controllable range due to a sudden load change on the motor.

This will be described with reference to FIG. In the figure, in order to facilitate understanding, the FG pulse is phase 0 with respect to the reference signal.
Shows a case where the motor control is performed in synchronization with each other (hereinafter, this synchronized state is also referred to as a phase lock state). That is, due to the abrupt load change described above, as shown in FIG.
The phase is shifted by (15/8) π from the above-mentioned phase locked state, and by the time of the next sample, that is, by the nth time, a further shift of (1/8) π or more ((2/8 in the example shown in the figure ) Π) occurs, the phase shift from the phase locked state is 2π
It becomes above (2π + (1/8) π). However,
In the control method as described above, in this case, it is determined that the phase shift has become small, and there is a problem that proper control becomes impossible.

[Problems to be Solved by the Invention] Therefore, an object of the present invention is to solve the above problems,
It is an object of the present invention to provide a rotating body drive device capable of performing accurate phase control of a rotating body even when a large load change occurs.

[Means for Solving the Problems] In order to achieve such an object, in the present invention, a rotation driving means for driving a rotating body and a pulse generating means for generating a predetermined pulse signal in accordance with the rotation of the rotating body. And a speed control for detecting the rotation speed of the rotating body based on the cycle of the pulse signal output from the pulse generating means, and controlling the speed of the rotation driving means so that the rotation speed becomes constant at a predetermined speed. Means, a reference signal source for generating a periodic reference pulse signal, and a phase difference between the pulse signal generated by the pulse generating means and the reference pulse signal for one cycle of the reference pulse signal, and the phase difference A phase control means for controlling the phase of the rotation drive means so that a predetermined phase difference is obtained,
Control for changing the number of times the phase difference is calculated by the phase control means in accordance with the generation interval of the pulse signal generated by the pulse generation means in a state where the rotation drive means is phase controlled by the phase control means. Means and are provided.

[Operation] According to the present invention, when detection is performed by the detection means,
That is, for example, when the calculation for the phase control by the phase control means is not in time, by performing only the minimum necessary calculation according to the detection, efficient control becomes possible.

[Examples] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an electronic still camera including a disk drive device as an embodiment of the rotating body drive device of the present invention. In the figure, 1 is a motor start switch, 2 is a system control arithmetic unit for controlling the entire apparatus and performing various arithmetic operations, etc., a CPU in the form of a microcomputer, a RAM having a work area, etc., shown in FIG. It has a ROM and a counter that store such procedures. 3 is reset at the rising edge of the input signal (RESE
T) and a timer counter circuit 4 for counting from 0 are latch circuits for holding the contents of the timer counter circuit 3 at each rising edge of the input signal, and the phase control means is constituted by the respective units 2, 3 and 4. ing. Reference numeral 5 is a system reference signal generation circuit as a synchronization signal source that generates a timing signal (synchronization signal) for the entire electronic still camera in which the motor is incorporated, and reference numeral 6 is a reference signal that generates a reference signal for phase control of the motor. A motor control reference signal generating circuit as a source, 7 is a D / A converter, 8 is a motor drive circuit for amplifying the D / A converted motor control signal, and 9 is a motor as a rotation drive means.

Reference numeral 10 denotes an FG signal pulse corresponding to the rotation phase of the motor, that is, an FG (Frequency Generator) circuit as a detection means for generating, for example, 16 pulses per one rotation of the motor 8, 1
1 is a side for setting a speed control mode (hereinafter, speed control mode) using speed deviation by the mode switching signal 14 and b side for setting a phase control mode by phase synchronization (hereinafter, phase control mode) A mode switch for switching to a phase signal generator (P) that outputs a pulse synchronized with the motor phase at H level once per motor revolution (P
G), 21 is an AND gate, 12 is an output signal from the FG circuit 10, and 13
Is RESET input to the reset input terminal of the counter circuit 3.
A signal, 15 is a READY signal output from the arithmetic unit 2 which is at the H level when the phase is synchronized and L level when the phase is asynchronous, 16 is a reference signal generation timing signal output from the arithmetic unit 2, and 17 is a control reference signal generation circuit 6 18 is the reference signal output from
An output signal from the PG 19, 20 is a one-shot circuit for generating an H-level one-shot pulse having a width of the FG cycle of the motor when the READY signal 15 changes from the L level to the H level. Reference numeral 22 is an image pickup device, 23 is a signal processing circuit, 24 is a head, and 25 is a recording medium as a rotating body to be controlled.

Next, the operation of the configuration shown in FIG. 1 will be described.

FIG. 2 shows an example of a drive control procedure of the rotating body according to the present embodiment. In this embodiment, the motor 9 is synchronized with the vertical synchronizing signal of the video signal, and at the time of phase synchronization, the FG signal 12 of the motor 9 is generated.
Is equal to the cycle of the reference signal 17 from the control reference signal generation circuit, and the phase difference between the rising edge of the FG signal pulse and the rising edge of the reference signal 17 is π.

It is assumed that the motor 9 has stopped rotating at the initial stage. At the initial stage, the switch 11 is set to the side a, that is, the speed control mode side. Here, when the motor start switch 1 is closed in step S1, the process proceeds to step S2, where the system control calculation unit 2 outputs a constant value sufficient for starting the motor 9 to the D / A converter 7.

Then proceed to step S3, where the following motor 9
After performing the speed control in step S4, the operation unit 2 determines whether the speed is stable or not in step S4. That is,
First, in step S3, the signal from the D / A converter 7 is input to the drive circuit 8, and the signal from the drive circuit 8 based on this is supplied to the motor 9. Then, the motor 9 starts to rotate and FG
FG pulse signal proportional to the rotation cycle of the motor 9 from the circuit 10
12 is output. Since the switch 11 is on the a side here,
At the rising edge of the FG pulse signal 12, the contents of the timer counter circuit 3 are held in the latch circuit 4, and the timer counter circuit 3 is reset to start time counting from 0 again. That is, the latch circuit 4 holds the cycle of the FG pulse for each rising edge of the FG pulse signal. The calculation unit 2 calculates the period of the held FG pulse and the control target period (that is, in the case of the NTSC system, for example, the vertical synchronization signal period 1/60
The operation amount is calculated with the difference from the second) as the deviation amount, and the calculation result is output to the D / A converter 7. In this way, the speed of the motor 9 is controlled.

Next, in step S4, it is determined in the arithmetic unit 2 based on the deviation amount whether the speed of the motor 9 is sufficiently stable near the target speed. If the deviation amount is equal to or larger than the predetermined value, the speed is not stable and the process returns to step S3. If the deviation amount is within the predetermined value, the speed is stable and the process proceeds to step S5.

In step S5, the arithmetic unit 2 determines whether or not the FG pulse has risen. If the determination is affirmative, the process proceeds to step S6, and the arithmetic unit 2 counts the time from the rise of the FG pulse by a built-in counter. Next, in step S7, calculate whether or not [1/2 of the FG pulse period when the FG pulse is synchronized with the control target period (for example, vertical synchronization signal period)] time, that is, π time has elapsed from the start of counting. The determination is made in the section 2, and if the determination is affirmative, the process proceeds to step S8.

In step S8, the switch 11 is switched to the phase control mode side, that is, the side b in the arithmetic unit 2, and then the reference signal generation timing signal 16 from the arithmetic unit 2 is input to the control reference signal generation circuit 6 in step S9. And computing unit 2
The output of the reference signal 17 from the generation circuit 6 is started when π time has elapsed from the rising edge of the FG pulse.

FIG. 4 shows the timing of the FG signal and the reference signal at this time. As a result, the counter circuit 3 is reset every time the output signal of the control reference signal generating circuit 6 rises in the phase control mode.

In step S10, the operation unit 2 causes the latch circuit 4 to operate.
Read the contents of. The content of the latch circuit 4 is the reference signal 17
Is a time count value of the counter circuit 3 from the rising edge of FG pulse to the rising edge of FG pulse, which indicates the phase difference between the reference signal and the FG pulse signal.

Then, in step S11, a phase difference determination routine described later is performed. By this routine, the deviation amount between the phase difference between the reference signal and the FG pulse and the target phase difference is corrected.

Then, in step S12, the operation amount is calculated by the calculation unit 2 based on the corrected deviation amount, and then the process proceeds to step S13 where the calculation result, that is, the operation amount is output from the calculation unit 2 to the D / A converter 7. To do. Thereby, the rotation phase control of the motor 9 is performed based on the operation amount. Next, in step S14, the arithmetic unit 2 determines whether the phase difference between the reference signal and the FG pulse is the target phase difference, that is, whether the phase is synchronized, based on the read contents of the latch circuit 4, Step if not in sync
Return to S10 and repeat the same procedure. On the other hand, if it is determined that they are in phase synchronization, the process proceeds to step S15, the READY signal 15 of H level is output from the calculation unit 2, and step S15 is performed.
Return to 10.

Next, the rotating body drive control unit, which is the main part of this embodiment, will be described in detail.

FIG. 3 is a detailed configuration example of the respective units 3, 4, 6 and 11, that is, the rotary body drive unit shown in the dashed line in FIG.
In the figure, 105 and 106 are timer prescalers, and 107
Numerals 110 are timer counters that perform counting with the clock signal 201 from the initial values set by the timer prescalers 105 and 106, and constitute the counter circuit 3 in FIG. 111 and 112 are timer latches that hold the values of the timer counters 107 to 110 by the strobe signal 202, and constitute the latch circuit 4 in FIG. 113 is a flag buffer that latches the outputs of flip-flops (hereinafter abbreviated as FF) 117, 118, 119 and 115, 114 is a mode setting buffer for controlling the switching of the mode changeover switch 11, 122 is the timing of the inverted signal 203 of the FG signal 12 FF that operates on the FF, 121 is an FF that latches the Q output of the FF 122 at the timing of the clock signal 201, 120 is an FF that latches the Q output of the FF 121 at the timing of the clock signal 201, and 116 is the NAND gate 15
FF that latches the output of 6 at the timing of clock signal 201
Is. 130-140 are inverter gates, 150-161 are NAND
Gates 170 to 173 are NOR gates. The reference signal generating circuit 6 is the timer counter 107 in this embodiment.
Also used for ~ 110.

101 and 102 are CPs of the system control calculation unit 2, respectively.
Data bus buffers and address bus buffers coupled to U via a data bus and address bus, and 103 and 104 are address decoders coupled to the address bus buffer 102. Also, ▲ ▼, ▲ ▼, ▲ ▼
Symbols ▲ and ▼ are a chip select signal, a read signal, a write signal, and an address line signal for operating the address bus buffer 102, which are supplied from the CPU, respectively.

Next, an operation example of the circuit shown in FIG. 3 will be described.

First, it is assumed that the mode select signals 204 and 205 are set to the L level and the signal 206 is set to the H level, and the device is in the phase control mode. At this time, the prescalers 105 and 106
The target cycle of FG is set in a two's complement representation that is an integral multiple of the cycle of the clock signal 201. Then, the signal 202 becomes L level at the rising of the signal 207 slightly delayed from the rising of the FG signal 203, the values of the timer counters 107 to 110 are latched in the timer latches 111 and 112, and the inverted signal of the signal 207 is obtained.
The output of FF115 becomes H level by 209. Further, the output of the gate 173 becomes L level by the overflow signal of the timer counters 107 to 110, and the counters 107 to 110 re-count from the values set in the prescalers 105 and 106 again. That is, the timer latches 111 and 112 hold the value obtained by measuring the time from the start of the recounting of the timer counters 107 to 110 to the rising of the FG signal 203. That is, the phase control is performed by controlling the rotation phase of the motor 9 so that this value becomes constant.

By the way, the fact that the data is latched in the timer latches 111 and 112 can be known by the Q output of the FF115 becoming the H level as described above.
Consider that the next FG signal 203 rises before reading the contents of 111 and 112. FF115 is RE of timer latch 112
Cleared by AD strobe signal 210, but if REA
If the FG signal 203 rises before the D strobe signal 210 becomes L level, the output of the NAND gate 153 becomes L level and F
The Q output of F117 becomes H level. That is, the calculation unit 2
The CPU may, for example, perform a phase control process (steps S10 to S1).
If the contents of the flag buffer 113 corresponding to this signal are referred to via the data bus in 5), the timer latches 111 and 112
It is possible to detect that the FG signal 203 has risen more than once before the content of is read.

In general, when the calculation at the time of phase control is processed by using a microcomputer or the like, the calculation may not be in time in this way. At this time, a part of the normal arithmetic processing may not be performed, and only the essential processing may be performed so as to be in time for the timing of the next FG pulse. That is,
A process of changing the number of calculation processes is performed. For example, the phase of the motor 9 is not significantly disturbed without performing the phase control calculation about once every several times. So in this case,
It is also possible to perform only the process of resetting the FF 117, that is, the process of setting the input of the gate 139 to the L level, and wait for the next data to be latched.

Next, the timer counters 107-110 overflow,
Consider a case where the FG signal 203 does not rise even once until the next overflow after the recount is started.

First, when the timer counters 107-110 overflow,
The output of the NAND gate 156 becomes H level. Therefore, FF116
Q output of is at H level. In this state, FG signal 20
When 3 rises and the signal 209 becomes L level, the output of the NAND gate 156 becomes L level and the output Q of the FF 116 becomes L level if the timer counters 107 to 110 have not overflowed at this time, but the FG signal 203 If the overflow signal 208 of the timer counters 107 to 110 becomes H level again before rising, the both inputs of the NAND gate 154 become H level and the Q output of the FF 118 is set at H level.

As a result, the CPU of the arithmetic unit 2 refers to the contents of the flag buffer 113 corresponding to this signal via the data bus during the phase control process, for example, and the timer counters 107 to 1
It can be detected that 10 has overflowed and that the FG signal did not rise until the next overflow.

At this time, the motor may be stopped because it is in an abnormal state, but it is sufficiently conceivable that the phase control will continue to be required. In this case, first, the input of the gate 139 is set to the L level to reset the FF 118, and then, based on the signal state of the flag buffer 113 referred to above, or the transition to the speed control mode is made as an interrupt signal to change the speed. When becomes stable, the phase shifts to the phase control mode again.

In the speed control mode, the mode select signals 204 to 206 are all set to L level and the prescaler is set to zero.
Then, signal 2 slightly delayed from the rising edge of FG signal 203
At the rising edge of 07, the signal 202 becomes L level, the values of the timer counters 107 to 110 are held in the timer latches 111 and 112, and at the same time, the signal 211 becomes L level and the gate 173
Becomes the L level, and the counters 107 to 110 are loaded with the values of the prescaler, that is, reset to zero and start recounting. At this time, the values of timer latches 111 and 112 are FG
Since the signal cycle is shown, speed control may be performed based on this value.

Next, consider the case where the timer counters 107 to 110 overflow and the FG signal 203 rises more than once before the next overflow occurs after the recounting is started.

First, when timer counters 107-110 overflow, NA
The output of the ND gate 156 becomes H level. Therefore, the Q output of FF116 becomes H level and the output becomes L level. In this state, when the FG signal 203 rises and the signal 209 becomes L level, the output of the NAND gate 156 becomes L level and the Q output of the FF 116 becomes L level because the timer counters 107 to 110 have not overflowed yet at this time. The output goes high. If counters 107-110 overflow here,
The output of the NAND gate 156 becomes H level, the Q output of the FF 116 becomes H level, and the Q output becomes L level, but if the FG signal 203 rises again before overflow occurs, NAND
The output of the gate 155 becomes L level and the Q output of FF119 becomes H level.

As a result, the CPU of the arithmetic unit 2 refers to the contents of the flag buffer 113 corresponding to this signal via the data bus during the phase control process, for example, and the timer counters 107 to 1
It is possible to detect that the FG signal 203 rises more than once before 10 overflows and then overflows.

At this time as well, the motor 9 may be stopped as in the case described above, but if the phase control is still required, the gate 13
After the input of 9 is set to the L level and the FF 119 is reset, based on the signal state of the flag buffer 113 referred to above, or by using this as an interrupt signal, the speed control mode is returned to after the speed becomes stable. It is sufficient to switch to the phase control mode again.

As described above, even when the FG pulse deviates from the reference signal by 2π or more, that is, in the case of FIG. 5, the phase difference between the two can be swiftly, reliably, and stably set to 0 to 2π without erroneous control. Can be in range.

In this embodiment, since the phase control is performed with the FG pulse (for example, 16 pulses per one rotation of the motor), it is possible to perform the phase synchronization with higher accuracy than that with the PG pulse (one pulse per one rotation of the motor). After phase synchronization, go to H in step S15
As the level READY signal 15 is output, the one-shot circuit 20 generates a pulse longer than the period of the reference signal 17 and shorter than two periods. Then, PG19 is an H level signal at a specific phase once every one rotation as the motor rotates.
Since 18 is output, when the output of the one-shot circuit 20 becomes H level, that is, READ indicating that the phase is synchronized
The Y signal 15 is at H level, the output signal 18 of the PG 19 is at H level, the output of the AND gate 21 is at H level, and the system reference signal generation circuit 5 is set.

Therefore, the timing of the video signal processing system including the image pickup system of the electronic still camera can be promptly obtained by the system reference signal generating circuit 5. Moreover, at this time, the recording medium 25 and the reference signal generating circuit 5 are completely synchronized.

As described above, according to the present embodiment, when the motor is started, only the speed control is performed without performing the phase control based on the synchronization signal, so that the phase error signal is not affected. Therefore, it takes a short time to stabilize the speed. Further, according to this embodiment, after the motor speed becomes stable, the motor control is switched from the speed control to the phase control, and the phase of the reference signal for the phase control is first adjusted to the phase of the motor to switch the phase control. It is possible to reduce the motor phase fluctuation during the time and synchronize the phases in a short time. Moreover, the synchronization of the phase-synchronized motor and the video signal can be promptly obtained.

In this embodiment, when controlling using the FG pulse, FG
The case where the pulse is deviated by 2π or more from the reference signal, that is, the case as shown in FIG. 5 has been described. However, even when the control is performed by using the PG pulse, it is easy to deal with it by changing the value of the timer prescaler.

Further, although the case where the present invention is applied to the electronic still camera has been described in the above-described embodiments, it is needless to say that the present invention can be extremely effectively and easily applied to various devices having a drive mechanism for a rotating body.

[Effects of the Invention] As described above, according to the present invention, the phase control range can be widened, and even when a large load change occurs, it can respond swiftly, reliably and stably. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an electronic still camera to which a rotating body driving device according to an embodiment of the present invention is applied, FIG. 2 is a flowchart showing an operation example of the device shown in FIG. 1, and FIG. Is a circuit diagram showing a detailed configuration example of a main part of this embodiment, and FIGS. 4 and 5 are timing charts showing two examples of timings of a reference signal and a PG pulse signal. 2 ... System control calculation unit, 3 ... Timer counter circuit, 4 ... Latch circuit, 6 ... Control reference signal generation circuit,
9 ... Motor, 10 ... FG, 105,106 ... Timer prescaler, 107-110 ... Timer counter, 111,112 ... Timer latch, 114 ... Mode setting buffer.

Claims (1)

[Claims] 1. A rotation driving means for driving a rotating body, a pulse generating means for generating a predetermined pulse signal in accordance with the rotation of the rotating body, and a pulse signal outputted from the pulse generating means on the basis of a cycle. A speed control means for detecting a rotation speed of the rotating body and controlling the speed of the rotation driving means so that the rotation speed becomes constant at a predetermined speed; a reference signal source for generating a periodic reference pulse signal; The phase difference between the pulse signal generated by the pulse generating means and the reference pulse signal is calculated during one cycle of the reference pulse signal, and the phase of the rotation driving means is controlled so that the phase difference becomes a predetermined phase difference. Phase control means, and in the state where the rotation driving means is phase controlled by the phase control means, depending on the generation interval of the pulse signal generated by the pulse generation means, Rotating body driving device is characterized in that comprises a control means for changing the number of operations of the phase difference by the phase control means.