JPH0591776A - Motor control circuit - Google Patents

Abstract

PURPOSE:To enable a motor control circuit to accurately control the position of a motor even when the phase difference between a phase comparing reference signal and frequency signal comes out of a prescribed range and, at the same time, to simplify the constitution of the circuit. CONSTITUTION:An up-down counter 35 selectively performs up- or down- counting operations in accordance to the advancing or delayed state of the phase difference between a phase comparing reference signal Sc and frequency signal Sf when the phase difference comes out of a prescribed range from -pito +pi and whenever the phase difference increases or decreases by a prescribed amount from the value. As a result, the count value of the counter 35 becomes its initial value '0' only when the phase difference is within the prescribed range. A signal generating means 41 continuously outputs a phase control signal SV having a fixed value during the period when the count value of the counter 35 is other than '0', namely, when the phase difference comes out of the prescribed range and changes the level of the signals SV in accordance with the phase difference during the period when the phase difference is within the prescribed range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control circuit for controlling motor synchronization.

[0002]

2. Description of the Related Art As an example of a motor control circuit used in a rotary feed mechanism using an asynchronous motor such as a DC motor, a circuit configuration as shown in FIG. 3 has been conventionally provided.

In FIG. 3, an encoder 2 composed of, for example, a frequency generator is mechanically coupled to the rotary shaft of the motor 1. The encoder 2 indicates the position and rotational speed of the rotor of the motor 1. The frequency signal Sf is output. The frequency signal Sf is converted into a speed control signal SV1 having a voltage level proportional to its frequency by an FV converter (frequency-voltage converter) 3 and a phase comparator 4
Given to. The phase comparator 4 compares the phase difference between the phase comparison reference signal Sc and the frequency signal Sf, and outputs the phase control signal SV2 corresponding to the difference as a low pass filter (LPF).
Output via 5.

The respective control signals SV1 output in this way,
SV2 is added by the adder 6 and supplied to the amplifier 7 as a motor drive circuit. The phase comparison reference signal is changed by changing the input voltage or current of the motor 1 according to the amplified output. The phase of the frequency signal Sf indicating the position of the rotor of the motor 1 is controlled to be synchronized with the phase of Sc.

[0005]

The phase comparator 4 described above is used.
Is for determining the leading and trailing states of the rising phase of the frequency signal Sf with respect to the rising phase of the phase comparison reference signal Sc, and is configured as shown in FIG. 4, for example.

In FIG. 4, the D flip-flop 8
Latches the "H" level signal (the signal given to the data terminal D from the terminal + Vcc) at the rising timing of the frequency signal Sf, and preferentially when the phase comparison reference signal Sc is at the "H" level. It is reset (unlatched). Therefore, as shown in (c) in the timing chart of FIG. 5, the D flip-flop 8 has a negative phase with respect to the rising phase of the phase comparison reference signal Sc.
Range of π to + π (one cycle of the phase comparison reference signal Sc is 2π
In a state where the rising phase of the frequency signal Sf in the range (1) is advanced, the “H” level signal is output from the terminal Q.

Further, the D flip-flop 9 latches the "H" level signal at the rising timing of the phase comparison reference signal Sc, and is preferentially reset when the frequency signal Sf is at the "H" level. is there. Therefore, as shown in FIG. 5 (d), the D flip-flop 9 has a predetermined lead phase range (the frequency signal S before the rising) based on the rising phase of the frequency signal Sf.
(where f is in the “L” level state), the phase comparison reference signal Sc rises, in other words, rises the frequency signal Sf within a predetermined delay phase range based on the rise phase of the phase comparison reference signal Sc. In this state, the terminal Q outputs an “H” level signal.

The output of the D flip-flop 8 for lead phase detection is given to the gate terminal of a three-state buffer (hereinafter simply referred to as a buffer) 11 via an OR circuit 10, and the output of the D flip-flop 9 for lag phase detection. The output is
Similarly, it is given to the gate terminal of the buffer 11 via the OR circuit 10 and also to the input terminal of the buffer 11.

As a result, the output of the buffer 11 is shown in FIG.
As shown in (e), the rising phase of the frequency signal Sf is -π to + π with respect to the rising phase of the phase comparison reference signal Sc.
, The phase of the frequency signal Sf is in the range of −π to + with respect to the phase comparison reference signal Sc.
In the range of π, the "H" level is exhibited during the period delayed and the Z level (high impedance state) is exhibited in other periods.

The output of such a phase comparator 4 is output through the low-pass filter 5 of FIG. 3, so that the phase comparison reference signal Sc and the frequency signal are output as shown by the solid line in FIG. 6 (a). The phase difference ΔF of Sf is supplied as the phase control signal SV2 showing a linear change in accordance with the phase difference ΔF in the range of −π to + π.

However, when there is an abnormality such as a sudden change in the load torque of the motor 1, the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf often falls outside the range of −π to + π. I am doing it. Specifically, as shown in FIG. 5, for example, in the seventh cycle of the phase comparison reference signal Sc, the frequency signal Sf of the seventh cycle is not input, and in the eighth cycle of the phase comparison reference signal Sc, the seventh cycle of It can be considered that the frequency signal Sf is input.

In such a state, the phase comparator 4 performs a comparison operation between the phase comparison reference signal Sc in the eighth cycle and the frequency signal Sf in the seventh cycle, and the result of the phase comparison is , Which is deviated from the originally required phase difference data by 2π. Such a phase shift may be further expanded in the advance direction or the delay direction, and as a result, FIG.
As indicated by a broken line in (a), the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf is 2 from the range of −π to + π.
Even in each range deviated by an integer multiple of π, -π to +
The phase control signal SV2 equivalent to the range of π may be obtained.

Therefore, in the case of realizing the rotary feed mechanism using the motor 1, it is necessary to perform the position control so that the rotor of the motor 1 exists at the position virtually indicated by the phase comparison reference signal Sc. However, as described above, the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf is −π˜.
Even when the range is out of the range of + π, the phase control signal SV2 equivalent to this is obtained, so that the position control of the motor 1 is performed in a state where the phase control signal SV2 is out of the original position.

To explain such a phenomenon with an actual example, FIG. 6B shows the phase comparison reference signal Sc and the frequency signal Sf when the position control of the motor 1 is ideally performed.
The change state of the phase difference ΔF is shown by a solid line. For example, as shown by the chain double-dashed line in the same figure (b), the position control of the motor 1 is performed so that the phase difference ΔF converges in the range of + 5π to + 7π In some cases, the rotor of the motor 1 cannot be controlled to a normal position.

In order to deal with such a problem, conventionally, the abnormality monitoring circuit 12 as shown in FIG. 4 is provided. That is, the abnormality monitoring circuit 12 includes counters 13 and 14 that independently count the rising edges of the phase comparison reference signal Sc and the frequency signal Sf, respectively, and the difference between the count values of the counters 13 and 14 is the phase comparison reference signal. It includes a comparator 15 that generates an abnormality monitoring signal Sa when it becomes "1" or more at the time of falling of Sc, so as to eliminate the above-mentioned abnormal state based on this abnormality monitoring signal Sa. Composed.

However, such an abnormality monitoring circuit 1
When 2 is provided, since the monitoring time is usually set to be relatively long, it is necessary to increase the capacity of the counters 13 and 14. That is, as shown in FIG. 5, when an abnormality occurs in the 7th cycle of the phase comparison reference signal Sc, the counters 13 and 14 can have a capacity of 3 bits (8 counts). If it is necessary to monitor the abnormality of the signal Sc up to the 800th cycle, the counter 1
A capacity of 10 bits (1024 counts) is required for 3 and 14, and in order to monitor a longer time, it is necessary to significantly increase the capacity of the counters 13 and 14 accordingly.

Therefore, in the conventional motor control circuit, it is inevitable that the circuit structure for accurately controlling the position of the motor 1 is increased in size, and the abnormality monitoring signal Sa fed back from the abnormality monitoring circuit 12 is inevitable. Since a circuit for eliminating the abnormal state based on the above is also required, the overall circuit configuration is further increased in scale.

The present invention has been made in view of the above circumstances, and an object thereof is to accurately control the position of a motor even when the phase difference between the phase comparison reference signal and the frequency signal is out of a predetermined range. Another object of the present invention is to provide a motor control circuit that achieves effects such as simplification of the circuit configuration.

[0019]

In order to achieve the above object, the present invention compares the phase difference between the phase comparison reference signal and the frequency signal indicating the actual rotation speed of the motor, and based on this phase comparison result. In a motor control circuit that supplies a control signal to a motor drive circuit, when the phase difference between the phase comparison reference signal and the frequency signal exceeds a predetermined range, the phase difference increases or decreases in accordance with a predetermined amount. An up / down counter that selectively performs an up-count operation and a down-count operation is provided, and while the count value of the up-down counter is at an initial value, the control signal level is changed according to the phase difference. A signal generating means for continuously outputting a control signal of a constant value is provided during a period other than the initial value.

[0020]

When the rotation speed of the motor changes, the phase difference between the phase comparison reference signal and the frequency signal changes accordingly. When the phase difference exceeds the predetermined range due to such a change, the up-down counter selectively performs the up-count operation and the down-count operation as the phase difference increases or decreases by a predetermined amount. become. Thus, the up-down counter maintains the count value other than the initial value when the phase difference between the phase comparison reference signal and the frequency signal is out of the predetermined range, but when the phase difference converges within the predetermined range. , Function to return the count value to the initial value.

The signal generating means keeps constant with respect to the motor drive circuit during the period when the count value of the up / down counter is other than the initial value, that is, during the period when the phase difference between the phase comparison reference signal and the frequency signal is out of the predetermined range. Since the value control signal is continuously output, the phase difference converges to the above-described predetermined range according to the motor control by the control signal. The signal generating means changes the control signal level given to the motor drive circuit according to the phase difference during the period when the count value of the up-down counter is at the initial value, that is, during the period when the phase difference is within the predetermined range. By doing so, the rotational position of the motor is controlled.

That is, even when the phase difference between the phase comparison reference signal and the frequency signal is out of the predetermined range, the motor control is performed so that the phase difference converges within the predetermined range.
In the state where the phase difference converges within the predetermined range, the motor control is performed according to the fluctuation of the phase difference within the range, and thus the rotational position control of the motor can be accurately performed.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In this embodiment, instead of the phase comparator 4 in FIG. 3, the phase comparator 16 shown in FIG.
Since it is characterized by the provision of the above, the description other than the phase comparator 4 in the description regarding FIG. 3 will be incorporated as it is.

In the phase comparator 16 shown in FIG. 1, the D flip-flop 17 latches the "H" level signal at the rising timing of the frequency signal Sf, and the phase comparison reference signal Sc is at the "H" level. Reset (latch release) is given priority. D flip-flop 18
Latches the "H" level signal at the rising timing of the phase comparison reference signal Sc, and
Is preferentially reset in the state of "H" level.

As a result, as shown in the timing chart of FIG. 2, a predetermined range of -π to + π with respect to the rising phase of the phase comparison reference signal Sc (one cycle of the phase comparison reference signal Sc is set to 2π). Frequency signal S in the range)
When the rising phase of f is advanced, the "H" level signal is output from the terminal Q of the D flip-flop 17 (see FIG. 2C). In addition, a state in which the phase comparison reference signal Sc rises in a predetermined lead phase range (the range in which the frequency signal Sf is in the “L” level state before the rise) based on the rise phase of the frequency signal Sf, in other words, , D flip-flop 18 when the frequency signal Sf rises in a predetermined delay phase range based on the rising phase of the phase comparison reference signal Sc.
An "H" level signal is output from the terminal Q of the (see FIG. 2 (d)).

The output of the D flip-flop 17 is given to the terminal A of the multiplexer 19, and the output of the D flip-flop 18 is given to the terminal A of the multiplexer 20. These multiplexers 19 and 20 select the input signal to the terminal A when the “H” level signal is input to the select terminal M, and input to the terminal B when the “L” level signal is input to the select terminal M. It is configured to select a signal.

An output of the multiplexer 19 is given to a gate terminal of a three-state buffer (hereinafter simply referred to as a buffer) 22 via an OR circuit 21, and an output of the multiplexer 20 is also sent to a buffer 22 of the buffer 22 via the OR circuit 21. The signal is given to the gate terminal and the input terminal of the buffer 22, and the output of the buffer 22 is given to the low-pass filter 5 shown in FIG. 3 as a phase control signal SV described later.

The RS flip-flop 23 receives the phase comparison reference signal Sc at the reset input terminal R via the inverter 24, and at the set input terminal S the frequency signal S.
connected to receive f.

The AND circuit 25, one input terminal of which is configured as an inverting input terminal, is connected so that the inverting input terminal thereof receives the phase comparison reference signal Sc and the other input terminal thereof receives the frequency signal Sf. AND circuit 26
Receives the phase comparison reference signal Sc at one input terminal and the RS flip-flop 2 at the other input terminal.
3 are connected to receive the output. The RS flip-flop 27 is connected to receive the outputs of the AND circuits 25 and 26 at the set input terminal S and the reset input terminal R, respectively.

The D flip-flop 28 receives the frequency signal Sf at its clock terminal CK and the output of the RS flip-flop 23 at its data terminal D, and its output is supplied to one of the AND circuits 29. Apply to the input terminal of. The AND circuit 29 is adapted to receive the frequency signal Sf at the other input terminal, and supplies the output thereof to the terminal A of the multiplexer 30.

The D flip-flop 31 receives the phase comparison reference signal Sc at its clock terminal CK via the inverter 32, and receives the output of the RS flip-flop 23 at the data terminal D via the inverter 33. The output is given to one input terminal of the AND circuit 34. The AND circuit 34 receives the phase comparison reference signal Sc output from the inverter 32 at the other input terminal thereof, and supplies the output to the terminal B of the multiplexer 30.

The multiplexer 30 selects the input signal to the terminal A when the "H" level signal is input to the select terminal M, and selects the input signal to the terminal A when the "L" level signal is input to the select terminal M. The input signal for B is selected.

Now, the 4-bit up / down counter 3
5 receives the output of the multiplexer 30 at its clock terminal CK and the output of the RS flip-flop 23 at the select terminal U / D.
The up-count operation is performed while the select terminal U / D receives the "H" level signal, and the select terminal U / D
Further, the down-count operation is performed in a state where the "L" level signal is received. The up / down counter 35 is initialized when a reset signal is received at the reset terminal R.

The output terminals Q1 to Q4 of the up / down counter 35 are connected to the input terminals of the multi-input NOR circuit 36. Therefore, from this NOR circuit 36,
Only when the count value of the up / down counter 35 is the initial value "0", the phase ready signal Sr which becomes "H" level is output.
Are select terminals M of the multiplexers 19 and 20.
And to one of the input terminals of the AND circuit 37.

The AND circuit 37 is adapted to receive the frequency signal Sf at the other input terminal thereof, and supplies its output to the clock terminal CK of the D flip-flop 38.
The D flip-flop 38 outputs the output of the RS flip-flop 27 to an inverter 39 at its data terminal D.
Via the output signal, and its output is used as a phase determination signal Sd described later. In this case, the phase discrimination signal Sd is given to the terminal B of the multiplexer 19 via the inverter 40 and directly to the terminal B of the multiplexer 20.

Incidentally, the above-mentioned D flip-flops 17, 1
8, 38, multiplexers 19, 20, OR circuit 21,
The buffer 22, the RS flip-flop 27, the NOR circuit 36, etc. constitute the signal generating means 41 in the present invention.

Next, the operation of the phase comparator 16 configured as described above will be described with reference to FIG. 2 and FIG. 6 used in the description of the conventional example.

When the relationship between the phase comparison reference signal Sc and the frequency signal Sf changes, for example, in the states shown in FIGS. 2 (a) and 2 (b), the lead phase detecting D flip-flop 17 and the delay are detected. D flip-flop 18 for phase detection
, The "H" level signal is output at the timings shown in FIGS. 2C and 2D, respectively. The outputs of the inverters 24 and 32 change as shown in FIG.

The RS flip-flop 23 is set at the rising edge of the frequency signal Sf, and the inverter 2
4 is reset at the rising edge of the output of 4 (falling edge of the phase comparison reference signal Sc), and its output is shown in FIG.
It changes as shown in (f).

The output of the AND circuit 25 rises to "H" level only when the phase comparison reference signal Sc is at "L" level and the frequency signal Sf is at "H" level, as shown in FIG. 2 (g). It becomes a rising waveform. Further, as shown in FIG. 2 (h), the output of the AND circuit 26 is such that both the phase comparison reference signal Sc and the output of the RS flip-flop 23 are "H".
The waveform rises to the “H” level only in the level state.

The RS flip-flop 27 is set by the rise of the output of the AND circuit 25, and
The output of the AND circuit 26 is reset by the rise of the output, the output thereof changes as shown in FIG. 2 (i), and the output of the inverter 39 changes accordingly as shown in FIG. 2 (j). ..

The D flip-flop 28 has a frequency signal S.
The output signal from the RS flip-flop 23 is latched at each rising edge of f, and its output changes as shown in FIG. 2 (k). Therefore, the output of the D flip-flop 28 and the output of the AND circuit 29 which takes the AND condition of the frequency signal Sf are in the state shown in FIG.

The D flip-flop 31 is the inverter 3
2 output rising timing (phase comparison reference signal Sc
2), the signal inverted and applied by the inverter 33 from the RS flip-flop 23 is latched, and its output changes as shown in FIG. 2 (m). Therefore, this D flip-flop 3
1 which takes the AND condition of the output of 1 and the output of the inverter 32
The output of the ND circuit 34 is in the state shown in FIG.

The multiplexer 30 outputs A when the RS flip-flop 23 outputs the "H" level signal.
When the output from the ND circuit 29 is selected and the “L” level signal is output from the RS flip-flop 23, the AN
The output from the D circuit 34 is selected, and the count pulse Pc is output from the output terminal Q thereof at the timing shown in FIG.
To the clock terminal CK.

That is, the count pulse Pc is output when the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf is out of the predetermined range −π to + π, and from this state, the phase difference ΔF is 2π. It is output each time it exceeds or increases.

Therefore, the up / down counter 35 counts the rising of the count pulse Pc, and the output from the RS flip-flop 23 is "H".
The up-count operation is performed at the level, and the down-count operation is performed at the "L" level.

Specifically, in the example of FIG. 2, each rising timing of the first and second count pulses Pc (the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf is in the range of + π to + 3π). When the phase difference ΔF increases to + 3π to + 5π), the output of the RS flip-flop 23 is at the “L” level, so the down count operation is performed and the third and fourth shots are performed. At each rising timing of the eye count pulse Pc (when the phase difference ΔF decreases in the range of + π to + 3π and when the phase difference ΔF decreases in the range of −π to + π), the RS flip-flop 23 operates. Since the output is at "H" level, the up-count operation is performed. Therefore, in this case, the count value of the up / down counter 35 changes as shown in FIG.

As a result, the phase ready signal Sr output from the NOR circuit 36, as shown in FIG. 2 (q), is in the state where the count value of the up / down counter 35 is "0" which is the initial value, that is, the phase. Only when the phase difference ΔF between the comparison reference signal Sc and the frequency signal Sf is within the predetermined range of −π to + π, the level becomes “H” level, and when the count value is other than the initial value, that is, the phase difference. When ΔF is out of the range of −π to + π, the level becomes “L”.

As a result, the output of the AND circuit 37 which takes the AND condition of the phase ready signal Sr and the frequency signal Sf changes as shown in FIG. 2 (r), and the inverter is output at every rising timing of the output of the AND circuit 37. From the D flip-flop 38 which latches the output signal from 39, the phase discrimination signal Sd which rises at the timing as shown in FIG. 2 (s) is output.

The multiplexer 19 receives the phase ready signal S
When r is at the “H” level (the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf is in the range of −π to + π), the output from the D flip-flop 17 is selected and the phase ready In the state where the signal Sr is at the “L” level (the above-mentioned phase difference ΔF is out of the range of −π to + π), the phase determination signal Sd inverted and given by the inverter 40 is selected, and its output Is in a state as shown in FIG.

The multiplexer 20 receives the phase ready signal S
The output from the D flip-flop 18 is selected when r is at "H" level, and the phase determination signal Sd is selected when the phase ready signal Sr is at "L" level. The state is as shown in FIG.

As a result, the phase control signal SV output from the buffer 22 is, as shown in FIG. 2 (v), the period during which the "H" level signal is output from only the multiplexer 19, that is, the phase of the frequency signal Sf. Phase comparison reference signal S
“L” level during the period leading to c, and a period when the “H” level signal is output only from the multiplexer 20, that is, during the period when the phase of the frequency signal Sf leads the phase comparison reference signal Sc. The Z level (high impedance state) is exhibited during the level and other periods.

In summary, according to the configuration of the present embodiment described above, in the state where the phase difference ΔF is generated between the phase comparison reference signal Sc and the frequency signal Sf, the content of the phase difference ΔF (advance or delay). Phase control signal S of a level according to
V will be output. In this case, since the phase control signal SV having a constant value is continuously output during the period in which the phase difference ΔF is outside the predetermined range −π to + π, the motor 1 is controlled based on the signal SV. The phase difference ΔF
Will converge in the range of -π to + π. Further, during the period in which the phase difference is within the predetermined range −π to + π, the level of the phase control signal SV is changed according to the phase difference ΔF, whereby the rotational position control of the motor 1 is performed.

Therefore, for example, as shown by the solid line in FIG. 6B, even when the phase difference ΔF between the phase comparison reference signal Sc and the frequency signal Sf expands to + 5π or more, the phase difference ΔF falls within the predetermined range. It becomes possible to surely perform the control for making the convergence, and it is possible to accurately perform the position control of the rotor of the motor 1 in the predetermined range −π to + π.

Further, the up / down counter 35, which plays an important role in performing the above control, performs the counting operation only in the abnormal state where the phase difference ΔF is out of the predetermined range of −π to + π. Since it has a configuration, a small-capacity one is sufficient, and there is no possibility of causing a large-scale circuit configuration as in the conventional case.

In addition, when the motor 1 has an abnormality such as a sudden load change, the phase comparison reference signal Sc and the frequency signal Sf are generated.
When the phase difference ΔF is out of the predetermined range, the abnormal state can be detected by the phase ready signal Sr, and the direction in which the phase shift has occurred (lead or lag) can be detected by the phase determination signal Sd, and further up. Since the amount of phase shift can be detected based on the count value of the down counter 35, there is also an advantage that it is possible to analyze the abnormal state based on the detection results.

In the above embodiment, since the 4-bit up / down counter 35 is used, the phase comparison reference signal S
Although it is possible to cope with an abnormal state in which the phase difference ΔF between the frequency c and the frequency signal Sf is expanded to a range corresponding to ± 15 counts, by increasing the number of bits of the counter 35,
Further, it becomes possible to deal with a wide range of abnormal states, and conversely, when the variation range of the phase difference ΔF is small, the number of bits of the up / down counter 35 can be reduced to further simplify the circuit configuration. ..

Further, in the above-described embodiment, the phase comparator 16 has the structure using the flip-flop for the main part as an example, but the same applies to the phase comparator using other structure for the main part. It is possible.

[0059]

According to the present invention, as apparent from the above description, the motor control is performed based on the comparison result between the phase comparison reference signal indicating the actual rotation speed of the motor and the frequency signal. In the circuit, an up-down counter is used as an element for detecting a state where the phase difference between the phase comparison reference signal and the frequency signal exceeds a predetermined range, and when the detected phase difference is within the predetermined range, a motor drive circuit The control signal level given to the motor is changed according to the phase difference, and the signal generating means for continuously outputting the control signal of a constant value is provided during the period when the detected phase difference is outside the predetermined range. Even if the phase difference between the phase comparison reference signal and the frequency signal deviates from the specified range due to load torque fluctuations, etc. And it is possible to converge, it becomes capable of performing precise position control of the motor, yet because the need to increase the capacity of the up-down counter eliminated, it becomes possible to realize also the simplification of the circuit configuration.

[Brief description of drawings]

FIG. 1 is a functional block diagram of essential parts showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation

FIG. 3 is a functional block diagram for explaining a conventional configuration.

FIG. 4 is a functional block diagram of essential parts.

FIG. 5 is a timing chart for explaining the operation.

FIG. 6 is a signal waveform diagram for explaining the operation.

[Explanation of symbols]

In the figure, 1 is a motor, 2 is an encoder, 7 is an amplifier, 16
Is a phase comparator, 17, 18, 28, 31, 38 are D flip-flops, 19, 20, 30 are multiplexers, 2
3 and 27 are RS flip-flops, 35 is an up / down counter, 36 is a NOR circuit, and 41 is a signal generating means.

Claims (1)

[Claims] 1. A motor control that compares a phase difference between a phase comparison reference signal and a frequency signal that changes according to the rotation speed of a motor, and supplies a control signal based on the result of the phase comparison to a drive circuit for the motor. In the circuit, when the phase difference between the phase comparison reference signal and the frequency signal exceeds a predetermined range, the up-count operation and the down-count operation are selectively performed according to the increase or decrease of the phase difference by a predetermined amount. An up-down counter and the control signal level is changed according to the phase difference during the period when the count value of the up-down counter is at the initial value, and a constant value is maintained during the period when the count value is outside the initial value. A motor control circuit, comprising: a signal generating unit that continuously outputs a control signal.