JPS62188059A - Generating device for index signal of disk - Google Patents

Abstract

PURPOSE:To stably generate an index signal by setting the phase relation between an encoder Z phase pulse obtained in advance and a (phi) sector in a register, and generating a (phi) sector mark based on the encoder Z pulse. CONSTITUTION:The counting operation of a counter 9 in a measurement mode continues until the output of a monostable multivibrator 5 goes to L, and an FF-7 is reset, and counting values counted for plural number of times are added and averaged, to obtain a required clock number. A value in which the number of clocks are subtracted from the overflown values in the counter is set at a register 10 using the number of clocks. A measurement mode signal goes to H in an automatic (phi) sector generating mode, and it is supplied to an OR gate 11, and a Q output keeps an H state without clearing the FF-7. Consequently, a reference clock is impressed on the counter 9 continually, and when a counting is performed to a requested number of counts, a carry signal is outputted. The carry signal is outputted as a logical index signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a device that generates an index signal that serves as a reference for an optical disk, a magnetic disk, a magneto-optical disk, or the like.

(Prior Art) Conventionally, when accessing a disk of this type, such as an optical disk, a magnetic disk, or a magneto-optical disk, it is necessary to know the physical initial position (index) of the disk.

If there is a physical index such as an index ball, the index is detected by an index detection hinter and an index signal is generated. However, in the case of a disk that does not have a physical index, the read address The index is generated by demodulating the data and detecting the sector.

However, when dealing with a disk that does not have a physical index like this, if address demodulation fails, the index signal becomes 1! The problem was that I couldn't do it.

In view of these points, an object of the present invention is to provide an index signal generation device that can stably generate an index signal for an optical disk or the like that does not have a physical index such as an index hole. .

(Means for Solving the Problem) In order to achieve such an object, the present invention detects a phase shift between the encoder Z-phase pulse of the spindle motor that rotates the disk and the sector of the disk in the measurement mode. is obtained by counting the reference clock, and by setting the value obtained from the clock count value in the register in auto sector generation mode, the overflow signal generated by the counter is generated as an index pulse at the timing of the sector. It is characterized by being configured as follows.

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is a block diagram of main parts showing an embodiment of an index signal generation device according to the present invention. In the figure, 1 is a latch which latches sector iI@ (sector N06) of the demodulated address in response to a separately provided address confirmation signal. 2 is a comparator that compares the values of latch 1 and register 3, and if they match, a match signal (HIGH level signal).
(referred to as H) is an edge-triggered flip-flop (hereinafter referred to as D
-FF) is added to the clock input of 4.

This latch 1. A portion consisting of comparator 2 and register 3 is a final sector detection circuit that detects the final sector.

The first D-FF4 is set by a sector pattern match signal (signal indicating sector mark detection) applied via the inverter 12 (output Q becomes 1-11 GH), and the D input is connected to the common line ( (hereinafter, LOW level is simply abbreviated as LOW), and when there is a clock input, the output Q becomes LOW.

5 is a mono multi vibrator (hereinafter simply referred to as mono multi), and 6 is a second D-FF.

The monomulti 5 is triggered by the output of the first D-FF 4 and generates a pulse with a constant time width. The second D-FF6 is c
pu <central processing unit, not shown here. ) is reset by the measurement completion reset signal output from the boat when trying to start measurement (Q output is LO
Also, if the D input is fixed at HIGH and the output of the first D-FF4 led as a clock input changes from 14 IGH to LOW, its Q output becomes HIGH, which is the same as the D input. It becomes H.

7 is the third D-FF, the D input is fixed at HIGH, and the encoder Z-phase pulse of the spindle motor (this pulse is output once per rotation of the disk) is used as the clock. Also, as a reset signal,
OR gate 1 which takes the logical sum of the measurement mode signal (measurement mode) which is the port output from the monomulti 5 and the CPU.
1 output signal is used. The Q output of the third D-FF 7 is ANDed with the reference clock serving as a reference for timing measurement at the gate 8 and becomes the clock input of the counter 9 .

The above inverter 12. D-FF4 and 7° mono multi5. Orgate 11. The part consisting of the AND gate 8 is a gate means for allowing the reference clock to pass only for a predetermined period.The counter 9 counts the clock supplied from the gate 8, but immediately before the clock is supplied, the encoder 2-phase pulse is The value of register 10 is loaded (preset).

Further, an overflow of the count value is output as a carry signal. A value is set in the register 10 by the CPU via the data bus 12.

Further, the setting data to the register 3 and the count value of the counter 9 are transferred to the data bus 134! Sent via

The output pulse of the encoder is used as the reference clock, and in particular, a clock that generates a large number of pulses (for example, 1024 pulses) per one revolution of the disk is used, and the pulses are further divided into known clocks. Through a phase-locked loop (PLL), the influence of uneven rotation is suppressed, and the clock is output as a reference clock with virtually no fluctuation in frequency.

CPU, D-FF6. The part consisting of registers 10, etc. is υj that performs various controls such as mode switching, preset value selection, reading of clock count values, and calculations as necessary.
There are four circuits.

The operation in such a configuration will now be described with reference to the timing charts of FIGS. 2 and 3. First, the signals obtained from the disk drive device will be explained.

Generally, one track of an optical disc is divided into several sectors, and each sector has a format as shown in FIG. 2(a). When accessing one sector, the first sector mark is detected and timing is determined, and the address (track number and sector number) written in the next field is read to find the target sector. The sector mark is a specific pattern, and the optical disk drive detects a sector mark by an identification method based on pattern matching, and generates a sector pattern match signal as shown in Figure 2 (b). It's starting to happen.

Since the address data read from the disk is modulated data, as shown in (c) of Figure 2, it is subjected to v1 address demodulation) and then undergoes the necessary internal processing, as shown in Figure 2. The address determination signal shown in (d) is raised, and the detected sector number is established as an output as shown in FIG. 2 (c).

When the target sector is detected, the data section mark (the shaded area in Figure 2 (a)) in front of the data section is detected,
The data portion to be read after that is wi'd (it is modulated data, so it is m-toned).

When synchronizing using PLL, the sector
Since there is a synchronization pull-in pattern (clock pulse train) before the mark or the data part mark, it can be detected and used.

Note that the address confirmation signal is generated before the data section mark appears.

As described above, sector pattern match, sector NO, and address confirmation signals are obtained from the disk drive apparatus.Next, the operation of the configuration shown in FIG. 1 will be described. FIG. 3 is a timing chart for explaining the operation. Here, an example is shown in which one track has 22 sectors. Register 3 has the maximum sector N
Set "21" which is O. address is l1jl
Then, the sector number is latched in latch 1 by the address confirmation signal (FIG. 3(d)). Sector number is 2
When the signal is 1, a match signal is output from the comparator 2, and as a result, the Q output of the first D-FF 4, that is, the sector pattern match becomes OW (FIG. 4(E)). This signal is set (high) by the sector pattern match ((b) in the figure) of the next sector (sector), and this rising signal causes the monomulti 5 and the second D-
Start FF6.

The encoder Z-phase pulse shown in FIG.
-FF7 is turned on and also serves as a load signal for the preset value of the counter 9 (the set value of the register 1o).

The counting operation of counter 9 is performed in “measurement mode” (CPU
When the measurement mode signal is LOW), the output of the mono multi 5 becomes LOW and continues until the third D-FF 7 is reset, and in the case of "auto sector generation mode", the output of the mono multi 5 becomes LOW until the third D-FF7 is reset. The process continues until the counter 9 is again preset by a two-phase pulse after one revolution. A more detailed explanation is as follows.

■Measurement mode CPU is LOW from boat to OR gate 11.
In addition to outputting the measurement mode signal of register 10,
Clear (all of them).

Next, after resetting the second D-FF6 by giving a measurement completion reset signal, wait for the Q output of the second D-FF6, that is, the measurement completion signal, to become HIGH due to the rise of the sector pattern match. have

During this time, the Q output of the third D-FF7 is HIGH,
Since the reference clock (FIG. 3) is applied to the counter 9 through the gate 8, the counter 9 is counting the clock.

With the rise of the sector mark pattern match signal, the output of the monomulti 5 ((h) in the figure) becomes LOW, the third D-FF 7 is reset, and the clock input to the counter 9 is stopped.

At the same time, the Q output (measurement completion signal) of the second D-FF6 becomes HIGH, so the CPU confirms this, knows that the counter 9 is in the hold state, and goes to read the count value of the counter 9. . This count value indicates the number of reference clocks from the encoder Z-phase pulse to the sector pattern match of the sector.

After repeating the above measurements several times and confirming that the counted values are almost the same, the average is taken and used as the desired number of clocks. This calculation is performed on the CPkJ side.

(2) Auto sector generation mode Set in the register 10 using the number of clocks determined by the above measurement mode. That is, a value obtained by subtracting the number of clocks from the value at which the counter 9 overflows is set in the register 10.

If set in this way, the carry of the counter 9 will appear at the timing when the sector mark pattern match rises.

In auto sector generation mode, the measurement mode signal is
1 and is given to the OR gate 11, so the third D-
FF7 is not cleared and the Q output continues to be in the HIGH state after the encoder two-phase pulse. For this reason, the reference clock is continuously applied to the counter 9 without interruption, and when the counter 9 counts up to the determined number of clocks, a carry signal is output ((S) in FIG. 3). This carry signal is output as a logical index signal.

Note that the CPU is not limited to being placed inside the device of the present invention, but may be placed outside the device without any problem.

(Effects of the Invention) As explained above, according to the present invention, the phase relationship between the encoder two-phase pulse obtained in advance and the sector is set in the register, and a stable signal called the encoder two-phase pulse is generated. Since the sector mark is generated, the sector mark can always be obtained even if sector pattern matching or address #li alignment fails. Furthermore, since the count value is obtained by measuring several times in the measurement mode and using the average value of the probable count values, a highly reliable index signal can be obtained in terms of timing.

[Brief explanation of drawings]

FIG. 1 is a main part configuration diagram showing an embodiment of an index signal generation device according to the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation. 1...Latch, 2...Comparator, 3.10...
・Register, 4...First D-FF, 5...Mono multi, 6...Second D-FF, 7...Third D-FF
F, 8...and gate, 9...counter, 11.
...OR gate, 12...inverter, 13...data bus.

Claims (2)

[Claims] (1) The final sector number of the target disk is set in advance,
It has a final sector detection circuit that detects that the sector number given from the disk is the final sector, and a gate that passes a reference clock corresponding to the disk rotation given from the disk.In the measurement mode, the encoder Z phase from the disk is passed. The gate is opened from when the pulse is applied until the first sector pattern match signal is applied after the final sector detection circuit detects the final sector, and in the auto sector generation mode, the encoder Z
gate means for opening the gate after a phase pulse is applied; a counter to which a preset value is set and which counts the reference clock output from the gate means and generates a carry signal when an overflow occurs; and a measurement mode. In this case, the reference clock count value of the counter is read after presetting the counter to zero, and in the auto φ sector generation mode, the preset value is set to a number of clocks less than the overflow value by the number of reference clocks obtained in the measurement mode. After counting the reference clock in the measurement mode, the control circuit switches to the auto φ sector generation mode, and when a carry signal is output from the counter, it is generated as an index signal corresponding to the timing of φ sector detection. A disk index signal generation device characterized by: (2) The control circuit selects, as the preset value to be set in the auto φ sector generation mode, only a count value suitable for adoption from among the reference clock count values obtained by measuring multiple times in the measurement mode, and 2. The disk index signal generating device according to claim 1, wherein an average value is used.