JPS63267005A - Fm signal demodulator - Google Patents

Abstract

PURPOSE:To attain the input of a rectangular wave FM signal by applying AD conversion of phase information of the rectangular wave FM signal and using the AD conversion value as the input to a FM demodulator. CONSTITUTION:The titled demodulator is provided with plural stages of delay devices connected in series to an input terminal 1 of the 1st stage delay device of which an analog FM signal is inputted, a hold device 3 receiving outputs of each delay device and holding and outputting the input value according to a control signal S synchronously with the sampling period, and an encoder 4 synthesizing output values according to all combinations of output values of the hold device 3. That is, since the time of an amplitude-limited FM signal changed from a high to a low level (or from a low to a high level) is stored in the delay devices 2 as their internal data, the AD conversion of the phase information is attained by reading the internal information of the delay devices at each sampling period. Thus, even when amplitude limit is applied to the FM signal, the signal is inputted to a signal processing circuit while being converted into a digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an FM signal demodulator for demodulating an amplitude-limited FM signal.

2. Description of the Related Art In recent years, there has been a demand for demodulating frequency modulated signals by digital signal processing, and demodulators having a circuit for calculating inverse trigonometric functions have been used. The above-described conventional single-signal demodulation device will be described below with reference to the drawings.

FIG. 4 is a block diagram showing the configuration of a conventional FM signal demodulator. In Fig. 4, 20 is an input terminal, 21 and 2
2 is a digital filter, 23 is a divider, 24 is an arctangent calculator for calculating an arctangent, 26 is a differentiator, and 26 is an output terminal.

Using the FM signal demodulator configured as described above,
The operation of demodulating the M signal will be described below.

A sampled signal is input to an input terminal 20 and applied to digital filters 21 and 22.

The output Xr of the digital filter 21 and the output E=1/{C1 of the digital filter 22 are input to the divider 23, and X1/Xr is calculated. The output of the divider 23 is added to an arctangent calculator 24 which calculates the arctangent, t & n −'
(IE 1/N z ) is output. If the amplitude characteristics of the digital filters 21 and 22 are the same and the phase equality is shifted by 90° within the band where the FM signal exists, then X1=
It can be expressed as mu sin θ, Nr=mu CO 8 θ, and the output of the arctangent calculator 24 becomes the phase θ of the FM signal.

The output of the arctangent calculator 24 is added to the differentiator 25,
The rate of variation of the phase is available at the output 26 of the differentiator 26. A sample value of the phase fluctuation rate of the frequency modulation signal, that is, a sample value of the demodulated signal is obtained at the output terminal 26 of the knob.

Problems to be Solved by the Invention However, in the above-mentioned device, in order to obtain a good demodulated output even when the level of the FM signal increases or decreases from the reference level, it is necessary to The processing word length must be increased.

Normally, measures against amplitude fluctuations in FM signals are taken by suppressing the amplitude using an amplitude limiting circuit. However, since the signal subjected to such suppression becomes a rectangular waveform, a normal FM converter can only obtain a 1-bit converted value, and as a result, the quality of the FM signal deteriorates. It is not possible to obtain a good demodulated output with such a device.

In view of the above problems, the present invention provides an FM signal demodulation device using a digital signal processing method that can input a rectangular wave FM signal.

Means for Solving the Problems In order to solve the above-mentioned problems, the FM signal demodulation device of the present invention includes a delay device connected in series in a plurality of stages to which an analog signal is input to the input terminal of the first stage, and a delay device in the plurality of stages. The output of each delay device is inputted, and a number of holders equal to the number of stages of the delay device holds and outputs the input value according to a control signal S synchronized with the sampling period, and the outputs of all the holders are inputted, an encoder that synthesizes an output value M1 according to a combination of output values of all the holders; a fourth register into which the output of the encoder is input; and an output A1 of the fourth register.
a first register to which is input, a second register to which output B1 of the first register is input, a third register to which output A2 of the second register is input; an exclusive OR circuit to which the sign bit of the output B1 of the register and the sign bit of the output A1 of the holder are input; and an exclusive OR circuit to which the output of the exclusive OR circuit is input to a clear terminal and is counted up by the control signal S. , the output C of the counter, the output A1 of the fourth register, the output B1 of the first register, the output A2 of the second register, and the output B2 of the third register are input. It is equipped with a calculator.

Effect of the Invention With the above-described configuration, the present invention delays the input FM signal by a plurality of stages of delay devices connected in series, and detects the change point from high to low of the signal appearing at the output terminal of each delay device. Detects axial variation information. The detected time axis direction fluctuation information is sampled, and this is the FM
This is the D-converted output of the signal. In this way, the square wave FM
The phase information of the signal is converted into a five-fold conversion value, and the D conversion value of F is
Digital signal processing method FM that can input a rectangular wave FM signal by using it as an input value of an M demodulator
A signal demodulator can be obtained. Also, the input signal is F
The present invention can be applied not only to the M signal but also to transmission methods such as pie-phase modulation and phase encoding, which transmit information by changing the period of the signal.

Embodiment Hereinafter, an FM signal demodulator according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an FM signal demodulator according to an embodiment of the present invention.

In Figure 1, 1 is an analog FM signal input terminal, 2
is a non-inverting buffer with multiple stages of logic elements connected in series,
3 is a D flip-flop to which the outputs of all the non-inverting buffers 2 are respectively input; 4 is an encoder to which the outputs of all the D flip-flops 3 are input; 6 is an input terminal for the sampling timing signal S; 6 is an input terminal for the sampling timing signal S; A counter, 7 is an exclusive OR circuit, 8 is a fourth register and the sampling timing signal S
is input as a clock. 9, 10.11 are the 1st. Second. The third register receives the output of the exclusive OR circuit 7 as a clock. 12 is a calculator, and 13 is an output terminal for a demodulated signal.

FIG. 2 shows the configuration of the encoder 4 in this embodiment.

In Fig. 2, 3o to 46 are input terminals to which the outputs of each holder are input, 46 is an exclusive OR circuit, and 47 is a priority encoder, which is the number of the lowest numbered input terminal that is high. Output. 48 is a negative circuit, and 49 is an output terminal.

FIG. 3 shows operating waveforms of each part in this embodiment. In FIG. 3, S is the sampling timing signal, F
is an analog FM signal, and P is the output of the encoder 4.

When a rectangular-wave analog FM signal is applied to the input terminal 1, the output terminal of each non-inverting buffer 2 has the following value: τ×(number of non-inverting buffer stages counted from the input terminal), where τ is the delay time of the logic element. A delayed signal with a time delay is output.

As an initial state, consider a state in which the input signal is low and the outputs of all non-inverting buffers 12 are low. From this state, the output of the first-stage non-inverting buffer 2 goes high one hour after the input signal goes high.
After time τ, the outputs of the first and second stage non-inverting buffers 2 become high. Similarly, after N7 hours, the outputs of the N non-inverting buffers 2 become high.

The output terminals of the non-inverting buffers 12 are each input to a holder constituted by a D flip-flop 3, and a latch timing signal is applied to the D flip-flop 3 in synchronization with the sampling period.

l) The output of the non-inverting buffer 2 is held in the D flip-flop 3 in synchronization with the sampling period and is input to the encoder 4. In the encoder 4, the outputs of the matching D flip-flops 3 are input to an exclusive OR circuit 46. As a result, only the output of the exclusive logic clever W&46, which is input so that one is high and the other is low, becomes high, so from N7 hours after the input signal a becomes high (H+1) When the latch timing signal is applied to the D flip-flop 3 in a period immediately before time τ, N is output to the output terminal of the priority encoder 47. The most significant bit of the output of the priority encoder 47 is inverted by the NOT circuit 4B, and an output value P in two's complement representation is obtained at the output terminal 49.

The output value P of the encoder 4 is input to the fourth register 8 in synchronization with the sampling timing signal S.

The sign bit of the fourth register 8 and the sign bit of the first register 9 are input to the exclusive OR circuit 7. When the output of the fourth register 8 and the sign bit of the first register 9 are different, , the output of the exclusive OR circuit 7 becomes high. The output of the exclusive OR circuit 7 instructs the calculator 12 to start calculation, and the output of the exclusive OR circuit 7 instructs the calculator 12 to start calculation. Third register 9, 10.11
is supplied as a data input clock to

On the other hand, the output of the exclusive OR circuit 7 is also connected to the initialization terminal of the counter 6. Furthermore, since the sampling timing signal S is input to the clock input of the counter 6, immediately before being initialized by the output of the exclusive OR circuit 7, there is a period when the sign of the output of the encoder 4 changes. This means that the time is outputted with the sampling period as one unit.

The sampling timing signal S is also input to the fourth register 8 as a clock.

As a result of this configuration, the output C of the counter 6 and the first
．． 2, 3.4 registers 9, 10, 11°8 output A1
．． B1. Mu2. From B2, the signal period T is T = C-1 MU 1V (1 person November B11) Published MU 21/(l
A2++1821) (Figure 3).

Therefore, the calculator 12 takes the calculated value X as X=|A
1|/(|A1|+|B1|)+lmu21/(112 countries B2+)) or an approximate value thereof, the frequency of the signal has been determined.

As described above, according to this embodiment, there are delay devices connected in series in multiple stages to which an analog signal is input to the input terminal 1 of the first stage, and the outputs of each of the delay devices in the multiple stages are input and the sampling period is A number of D flip-flops 3 equal to the number of stages of the delay device hold and output an input value according to a control signal synchronized with the control signal, and the outputs of all the D flip-flops 3 are inputted, and all the D flip-flops 3 of the retainer an encoder 4 that synthesizes an output value M1 according to a combination of output values; a first register 9 to which the output of the encoder 4 is input;
A second register 1o to which the output B1 of the first register 9 is input, a third register 11 to which the output A2 of the second register 1° is input, and a code pit of the output B1 of the first register 9. and an exclusive OR circuit 46 to which the code pit of the output A1 of the D flip-flop 3 is input, and a counter 6 to which the output of the exclusive OR circuit 46 is input to a clear terminal and is counted up by the control signal. It includes a calculator to which the output C of the counter 6, the output A1 of the encoder 4, the output B1 of the first register 9, the output A2 of the second register 1o, and the output B2 of the third register 11 are input. In particular, multiple amplitude-limited FM signals can be demodulated by digital signal processing.

In this embodiment, the delay device is the non-inverting buffer 2, but it may be an inverting buffer or other logic element. Furthermore, the input signal is not limited to the FM signal, but may be any signal that transmits information by changing the signal cycle, and it goes without saying that the present invention can also be applied to transmission methods such as pi-phase modulation and phase encoding.

Effects of the Invention As described above, the present invention has delay devices connected in series in multiple stages to which an analog signal is input to the input terminal of the first stage, and outputs of each delay device in the multiple stages are input to synchronize with the sampling period. The number of holders equal to the number of stages of the delay device that holds and outputs the input value according to the control signal S, and the code that receives the outputs of all the holders and synthesizes the output value according to the combination of the output values of all the holders. amplitude-limited FM signal changes from high to low (or from low to high)
Focusing on the fact that the time is stored as internal data of the delay device, it is possible to perform five-way conversion of phase information by reading the internal information of the delay device every sampling period.

By using such a FM D conversion technique, even if the FM signal is amplitude limited, it becomes possible to convert it into a digital signal and input it to the signal processing circuit.

Moreover, the MuD conversion can use logic gates as delay elements, and can be applied to high-speed signal processing. Furthermore, a fourth register to which the output of the encoder is input, a first register to which the output A1 of the fourth register is input, and a second register to which the output B1 of the first register is input; a third register to which the output A2 of the second register is input; an exclusive OR circuit to which the sign bit of the output B1 of the first register and the sign bit of the output A1 of the fourth register are input; A counter to which the output of the logical OR circuit is input to the clear terminal and is counted up by the control signal, the output C of the counter, the output A1 of the encoder, the output B1 of the first register, and the output A2 of the second register.
and a calculator to which the output B2 of the third register is input, and calculates the internal state of the delay device M1. before and after the FM signal changes from high to low (or from low to high). Mu2. B1゜B
2, and the output C obtained by counting the change period of the FM signal in the sampling period, E=1/(C-IAI +/(1mu11+IB11))
-IA21/(1121+1821)), the frequency of the signal can be detected accurately. In particular, here, the delay device detects time change points finer than the sampling period, and the internal information of the delay device is read out every sampling period, so low-speed signal processing is sufficient for the demodulator. Also, for frequency detection calculation, 1mu11/(1mu11+1
B11) and 1mu2+/(1mu21+1B21)
Since the proportional equation is used, the delay device only needs to ensure relative accuracy. E = high relative accuracy and low absolute accuracy
1/{Can also be applied to C process. As described above, the present invention can realize an FM demodulator using a digital signal processing method that is highly accurate and easy to implement.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an FM demodulator in an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an encoder in an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of an FM demodulator in an embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a conventional FM demodulator. 1...Input terminal, 2...Non-inverting buffer, 3...D flip-flop (retainer), 4
... Encoder, 5 ... Input terminal for sampling timing signal, 6 ... Counter, 7 ...
...Exclusive OR circuit, 8,9°10.11...
...Register, 12...Calculator, 13...
...Output terminal, 20...Input terminal, 21.22
...Digital filter, 23...Divider, 24...Arcade tangent calculator, 25...
・Differentiator, 26...Output terminal, 30-46...
...Input terminal, 46...Exclusive OR circuit, 47...Priority encoder, 48.
...Negation circuit, 49...Output terminal.

Claims (5)

[Claims] (1) A delay device connected in series with multiple stages to which an analog signal F is input to the input terminal of the first stage, and the output of each delay device in the multiple stages is input and input according to a control signal S synchronized with the sampling period. a number of holders equal to the number of stages of the delay device that holds and outputs a value; and an encoder that receives the outputs of all the holders and synthesizes an output value according to a combination of the output values of all the holders. , a fourth register into which the output of the encoder is input, and an output A of the fourth register.
1, a second register to which the output B1 of the first register is input, a third register to which the output A2 of the second register is input, and a third register to which the output A2 of the second register is input; an exclusive OR circuit to which the sign bit of the output B1 of the register and the sign bit of the output A1 of the fourth register are input; and the output of the exclusive OR circuit is input to a clear terminal, and the control signal an output C of the counter, an output A1 of the encoder, an output B1 of the first register, an output A2 of the second register, and an output B of the third register.
1. An FM signal demodulation device characterized by comprising a calculator into which the number 2 is input. (2) The FM signal demodulator according to claim 1, wherein the delay device is composed of a logic element. (3) The FM signal demodulator according to claim 1, wherein the holder is composed of a D flip-flop. (4) the encoder has one less logic circuit than the number of holders that performs exclusive OR of the output values of adjacent holders;
2. The FM signal demodulation device according to claim 1, further comprising a priority encoder to which the outputs of all the logic circuits are input, and a NOT circuit that inverts the most significant bit of the priority encoder. (5) The calculator considers the output A1 of the fourth register, the output B1 of the first register, the output A2 of the second register, and the output B2 of the third register to be binary numbers in two's complement representation,
Considering the output C of the counter as a positive value, the calculated value E=1/{C-|A1|/(|A1|+|B1|)+|
The FM signal demodulator according to claim 1, wherein the FM signal demodulator outputs an approximate value of A2|/(|A2|+|B2|)} or E.