JPH05103023A - Data synchronization detection method - Google Patents

Abstract

PURPOSE:To detect a preamble early in digital communication by comparing preceding and the newest coding data latched so as to detect the presence of autocorrelation of a reception signal. CONSTITUTION:A timing when a reception signal g2 is fetched by a CPU 3 is controlled by an interruption interval control means 4 connected to an interruption control terminal and two kinds of synchronizing interruption intervals are set to the interruption interval control means 4. In this case, a period of a sampling clock period t1 is a period dividing a time required for representing one symbol into 1/12. A reception preamble signal is binary-sampled at a period resulting from dividing a time slot of the preamble signal into 1/12. Then the preamble signal subjected to binary sampling is coded for each 8-bit and the arrival of the preamble signal is detected based on the autocorrelation of a code string of the preamble signal coded for each 8-bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting data synchronization in digital communication.

[0002]

2. Description of the Related Art In digital communication using a digital frequency modulation method, a predetermined bit pattern is formed prior to transmission data so that the reception side can prepare a reception condition and surely demodulate a modulated signal. A digital communication procedure is adopted in which a signal for adjustment is transmitted from the transmitting side.

In the adjustment signal in such a digital communication procedure, the adjustment period is called a bit synchronization frame, and the signal between the bit synchronization frames is called a preamble or a preamble signal.

As an example of this digital communication procedure,
There is a frame in which a frame for transmitting a bit synchronization signal (preamble signal), a frame synchronization signal, and a data signal is sequentially provided.

[0005]

In digital communication as described above, the only bits in the data frame that carry data communication are the bits that have been effectively used to convey information, and the bits before the data frame have been used. The bits in the bit sync signal and the frame sync signal are extra bits that reduce the information transmission efficiency.

On the other hand, if bit synchronization and frame synchronization are not accurately obtained on the receiving side, the error rate of demodulated data obtained in the subsequent data frame increases and the error rate due to noise also increases. In order to perform this bit synchronization and frame synchronization accurately, it is natural to increase the number of bits in each adjustment frame to increase the opportunity for adjustment, but on the other hand, the extra bits that are not involved in the transmission of information. Therefore, the conventional method has a problem that it is difficult to satisfy both the improvement of the error rate and the improvement of the transmission efficiency and the transmission rate.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an excellent data synchronization detection method capable of improving the error rate, the transmission efficiency and the transmission rate. To do.

[0008]

In order to achieve the above object, the present invention generates a sampling signal which divides a time slot as an information unit of a received signal into 12 and binarizes the received signal to digitally receive the signal. Is generated, the digital received signal is sampled by a sampling signal, coded every 8 bits in the sampling order to generate coded data, a past value of the coded data is held by a predetermined number, and the held coded data The presence or absence of autocorrelation of the received signal is detected by comparing the past value with the latest value.

[0009]

In the present invention, when the preamble signal arrives, the presence or absence of autocorrelation of the sampled preamble signal is detected and compared for the coincidence between the presently received signal and the previously received signal. It is possible to predict and detect the interrogation time between the two signals as a predetermined time by the bit pattern of the preamble signal.
The separation time at which the autocorrelation is obtained is set as the minimum discovery time of arrival of the preamble signal, and the preamble signal can be detected quickly.

Thus, by adopting a bit pattern having a short autocorrelation time as the preamble signal, the communication procedure is the quickest and the autocorrelation is checked for confirmation. Error rate is low,
Moreover, a high noise removal effect can be obtained.

[0011]

1 is a schematic block diagram of an embodiment of a data synchronization detecting apparatus according to the present invention. In FIG. 1, reference numeral 1 is a high-frequency circuit that outputs the received modulated wave (g1).
This modulated wave (g1) is a modulated wave by a frequency modulation (hereinafter abbreviated as FSK) system, and in particular, M with a modulation index of 0.5.
This is a modulation method called SK (MINIMUM SHIFT KEYING), and is a frequency modulation of a mark (hereinafter referred to as symbol 1) and a space (hereinafter referred to as symbol 0) which are basic information of a digital information signal.

Modulated wave (g1) output from the high frequency circuit 1
Is an analog waveform as shown in FIG. This modulated wave (g1) is a rectangular waveform received signal (g
2) That is, it is converted into a digital received signal.

Generally, a communication device for digital communication is divided into a transceiver type having a transmission / reception function and a reception-only type such as a pager or a radio receiver. Can also be applied to.

Further, a microprocessor (hereinafter abbreviated as CPU) by an integrated circuit is mounted in the communication device, and various data processing and control are centrally controlled by a microprogram. In FIG. 1, reference numeral 3 is a CPU in the above digital communication device.

The received signal (g2) is input to the interrupt control input port of the CPU 3.

The timing at which the received signal (g2) is taken in by the CPU 3 is controlled by the interrupt interval control means 4 connected to the interrupt control terminal.

The interrupt interval control circuit 4 has two
Types of periodic interrupt intervals (T1) and (T
2) is set.

This periodic interrupt interval corresponds to a sampling clock of the reception signal (g2) described later, and signals having the periods (T1) and (T2) will be referred to as the first sampling signal or sampling clock ( t1) and the second sampling signal or sampling clock (t2).

Cycle of sampling clock (t1) (T
1) is a period (T0) that divides the time required to represent one symbol (hereinafter referred to as a time slot) (T0) into 12 (T
0/12). The other sampling clock (t2) has a cycle (T0 / 8) that divides the time slot (T0) into eight.

As a communication procedure, at least a data synchronization frame, a frame synchronization frame, and a data frame are arranged in this order, and an adjustment frame is included at the beginning of the data frame. The data bit to be transmitted is taken in and demodulated. ing.

The sampling clock (t1)
Is used during the data synchronization frame, and the sampling clock (t2) is used during the period after the frame synchronization frame.

In the data synchronization frame, a data synchronization signal for adjustment (hereinafter referred to as a preamble signal) from the transmitter side.
(GP) is sent.

The preamble signal (GP) is shown in FIG.
The signal of the bit pattern shown by the repetition of the symbol 1 and the symbol 0 shown as the received signal (g2) of 1. has a strong autocorrelation and a short phase difference (time) for obtaining the autocorrelation. Has been done.

The preamble signal (GP) is used as the reception signal (g1) in the reception standby state and the data synchronization frame.
In addition to the noise component, it is difficult to detect the preamble signal on a symbol-by-symbol basis. Therefore, the CPU 3 receives the reception signal (g2) sampled by dividing the time slot (T0) into 12 by the sampling clock (t1).

As the CPU 3, an 8-bit internal processing is generally used. Therefore, the signals taken in the internal registers of the CPU 3 by the sampling clock (t1) of the interrupt are stored in the internal registers in the order in which they are taken. When the number of transmitted bits becomes 8 bits, 8-bit unit encoding is performed to generate encoded data, which is transferred to the A register 5 and held.

The A register 5 outputs coded data in units of 8 bits. The data (D) is
The data is sequentially transferred to the B register 6 and the C register 7 in the next stage.

The above-mentioned three 8-bit registers 5, 6, 7 are data holding means, and the form thereof is (a) a serial data transfer circuit having a bit number of 24 bits or more and capable of taking out a bit parallel output, (B) By hardware using three 8-bit register ICs,
(C) The memory controlled by the CPU 3 may be of any memory type, such as that of software allocated in the program variable area.

The preamble signal (GP) of FIG.
As shown by the waveform of the modulated wave (g1) of the symbol 0, the symbol 0 has a constant frequency time slot (T0) and a low frequency signal representing the symbol 1 and a frequency 1.5 times the frequency of the low frequency signal. The high frequency that represents the waveform appears alternately in the waveform.

The same symbols sandwiching different symbols have waveforms in which the phases are inverted by 180 degrees. This preamble signal (GP) received signal (g
The phase inversion relationship in 2) corresponds to the negative signal (NOT or positive / negative inversion) of the digital logic signal. Therefore, in a bit pattern obtained by encoding data obtained by finely dividing one symbol and sampling, the bit patterns having phase-inverted waveforms have a complementary relationship with each other.

From the above, symbol 1 and symbol 2
In the received signal (g2) of the preamble signal (GP) which is alternately repeated, an autocorrelation is obtained with a phase difference of 4 slot time (4T0) and 2 slot time (2T
0) Delayed inverted waveform and autocorrelation are obtained.

Therefore, in the present invention, the symbol 1,
Zero-cross division number 2 of symbol 0 and least common multiple 6 of 3
And the least common multiple of 24, which is convenient for data processing by the CPU 3, is 24, so that the minimum phase difference 2 time slot (2T0) period in which autocorrelation is obtained is 2
It is divided into four signal units.

That is, one time slot (T0) of the received signal (g2) is set to 1 by the first sampling signal.
The data is supplied to the CPU 3 by dividing into two. CPU
3, the data is sequentially encoded in units of 8 bits, and data (D0), (D1), (D2), (D3),
... are output in sequence.

Each sampling signal (S0) in FIG.
(S8) shows the 8-bit encoded data shifted by 1 bit. Sampling signal (S
0), D0 = FC, D1 = 0F, D2 = 0F,
D3 = 03, ... If this is expressed in a binary system, D0 = 11111100 and D3 = 00111111, and D0 and D3 are in a complementary relationship with each other, that is, inverted data. If the inverted data of the data (D) is expressed as data (-D), then D3 = -D0. That is, when the received signal (g2) is the preamble signal (GP), the arbitrary 8-bit encoded data (Dn) is 3
Data (-Dn-3) that is the inverted data (Dn-3)
-3), and the relationship of Dn = -Dn-3 is established. On the other hand, when the received signal (g2) is a noise component, the above relationship does not hold and the data does not match the inverted data.

The timing of sampling varies depending on the time of reception.
There are 48 ways obtained during the slot time (4T0). But considering the inverted signal, in effect,
24 patterns of sampling signals (S0) to (S0)
24), the data (Dn) and the inverted data (-Dn-3) three data before are the same in any pattern as long as they are the preamble signal (GP).

The A register 5, the B register 6, and the C register 7 in FIG. 1 are respectively composed of three 8-bit data (Dn-
1), (Dn-2), and (Dn-3) are sequentially reserved in the order of arrival from the CPU 3.

The CPU 3 then updates the latest data (Dn).
When is output, the pending contents of each register 5, 6, 7
The output data (Dn-3) of the C register 7 is inverted by the bit pattern inverting means 8 while being sequentially transferred to the next stage, and the data (-Dn-3) and the latest data (Dn-3).
n) is compared by the bit pattern comparison means 9.

When the pattern of the two input data (Dn) and the inverted data (-Dn-3) is obtained, the bit pattern comparison means 9 gives a coincidence signal to the counting means 10 and outputs the counted value. Is incremented by 1 and the count value is decremented by 1 if no match is obtained. The counting means 10 has a count value of 3
If it is above, the sampling signal (Sn) at that time will be
A preamble signal (GP) is determined and an autocorrelation flag is set, or an autocorrelation detection signal is set to C.
Supply to PU3. That is, the comparing means and the counting means constitute an autocorrelation detecting means.

In this way, the sampling signal (S
n) is determined to be a preamble signal (GP),
After that, the state is maintained as if the data synchronization is established until the end of the data frame.

However, when the data synchronization frame ends, the data processing of the CPU 3 shifts to the frame synchronization frame, so that the amount of data processing increases in the sampling of the sampling clock (t1). Therefore, the sampling clock of the interrupt interval control circuit 4 is switched to (t2). Sampling clock (t2)
Is a cycle (T0 /
8), the sampling signal (Sn) after the data synchronization frame encodes one symbol with 8 bits,
The load on the CPU 3 is reduced.

In each subsequent frame, demodulation processing of the modulated wave is performed such as the determination of the symbol position, the capture of the synchronization word signal, the capture of information data, etc. When the capture of the final information data is completed, the first preamble signal ( GP)
It will be in a waiting state.

[0041]

The present invention has the following effects, as is apparent from the above-described embodiments.

(A) Since the preamble signal can be detected early, the preparation for the subsequent processing can be taken early, and the speed of signal processing can be increased.

(B) Even with a preamble-length signal having a small number of bits, the preamble can be accurately captured, so that the information transmission efficiency can be improved and the information transmission speed can be increased.

(C) Since the processing cycle for determining the preamble is small, the load on the microprocessor used for the determination processing can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of a receiver using a data synchronization detection method according to the present invention.

FIG. 2 is a time chart of main waveforms in FIG.

[Description of Reference Signs] 1 high frequency circuit 2 analog comparator 3 microprocessor (CPU) 4 interrupt interval control means 5 A register 6 B register 7 C register 8 inverting means 9 comparing means 10 counting means

Claims (4)

[Claims] 1. A sampling signal for dividing a time slot as an information unit of a received signal into 12 is generated, the received signal is binarized to generate a digital received signal, and the digital received signal is sampled by the sampling signal. , Encoding every 8 bits in the sampling order to generate encoded data, hold a predetermined number of past values of the encoded data, compare the past value of the held encoded data with the latest value, and receive the received data. A data synchronization detection method characterized by detecting the presence or absence of signal autocorrelation. 2. The autocorrelation is detected by generating a coincidence signal when the oldest value of the past value and the latest value are in a complementary relationship with each other, and when the coincidence signal reaches a predetermined number, the autocorrelation is generated. The method for detecting data synchronization according to claim 1, wherein a detection signal is issued. 3. A data synchronization detection method for a reception signal having a data synchronization frame at the beginning of one frame, wherein 12 time slots are used as an information unit of the reception signal.
A first sampling signal to be divided and a second sampling signal to divide the time slot into eight are generated, and the period of the data synchronization frame of the reception signal is sampled by the first sampling signal to obtain the reception signal. After the period of the data synchronization frame, the second sampling signal is used for sampling, the data is encoded in the order of 8 bits to generate encoded data, and the past value of the encoded data is reserved by a predetermined number. A method for detecting data synchronization, comprising comparing the past value and the latest value of the encoded data to detect the presence or absence of autocorrelation of the received signal. 4. The detection of the autocorrelation generates a coincidence signal when the oldest value of the past values and the latest value are in a complementary relationship with each other, and when the coincidence signal reaches a predetermined number, the autocorrelation is generated. The method for detecting data synchronization according to claim 3, wherein a detection signal is issued.