JPH08223231A - Digital data transmitter, receiver and digital data communication system - Google Patents

Abstract

PURPOSE: To improve a reception threshold level and to reduce a multi-path fault by providing an output of preamble data comprising specific code data synchronously with a timing pulse. CONSTITUTION: A clock frequency divider 202 frequency-divides a inputted reference clock signal and outputs a timing pulse specifying a bit timing of transmission data. A timing pulse outputted from the clock frequency divider 202 is also fed to a preamble data generating circuit 204, which outputs a PN code in a timing specified by the timing pulse. The correlation is detected with high accuracy by adopting the PN code having a steep autocorrelation characteristic as the preamble data and each bit in the received data signal is accurately separated. Thus, high data decoding performance is obtained even when noise due to deteriorated S/N or multi-path is intruded in the received bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data transmission device, a reception device and a digital data communication system, and more particularly to a high speed data wireless transmission device such as a wireless LAN,
It is suitable for use in highly reliable wireless transmission devices such as industrial telecontrols and wireless transmission devices for bad environment transmission lines.

[0002]

2. Description of the Related Art Various digital data communication systems are known, such as a system for transmitting a baseband signal as it is, a system for transmitting a digitally modulated signal, and a system for transmitting a modulated signal on a carrier wave. Has been. Also, the digital modulation method is ASK (Amplitude shift keyin).
g, amplitude shift keying, FSK (Frequency shift k)
eying, frequency shift keying), PSK (Phase shift)
Various methods such as keying and phase shift keying) are known, and wire transmission lines, wireless transmission lines, optical transmission lines, etc. are used as transmission lines.

As described above, various systems are adopted for digital data communication, and as an example, a configuration example of a wireless digital data communication system adopting the FSK system as a modulation system will be described with reference to FIGS. 8 and 9. explain. FIG.
In 801 to 805, a wireless digital data transmission device is configured. 801 is digital data to be transmitted, 802 is an FSK modulator, 803 is a carrier wave generator, 804 is a high frequency amplifier, and 805 is a transmitting antenna. A wireless digital data receiving device is configured by 806 to 809, and 806 is a receiving antenna,
Reference numeral 807 is a high frequency circuit, 808 is an FSK demodulator, and 809 is an output digital signal.

FIG. 9 is a diagram showing an internal configuration of the FSK demodulator 808, and 901 is a terminal to which a received signal converted to an intermediate frequency in the high frequency circuit 807 is input,
2 is a buffer amplifier. Reference numeral 903 is a detection circuit for demodulating the FSK modulated signal, and a ratio detector, a Foster-Siley detector, a quadrature detector or a delay detector is used. 904 is a low-pass filter, 90
Reference numeral 5 is a buffer amplifier, and 906 is a comparator for comparing an input signal with a predetermined reference voltage to binarize it and outputting a digital signal.

In the wireless digital data transmitting apparatus constituted by 801 to 805, the digital data 801 to be transmitted and the carrier signal generated in the carrier generator 803 are input to the FSK modulator 802 and transmitted in the FSK modulator 802. FS by shifting the frequency of the carrier wave supplied from the carrier wave generator 803 according to "0" or "1" of the digital data 801 that is
K modulation is performed. The FSK-modulated signal output from the FSK modulator 802 is amplified by the high frequency amplifier 804 and then transmitted from the transmitting antenna 805.

On the other hand, in the wireless digital data receiving apparatus constituted by 806 to 809, the receiving antenna 8
The reception signal received by 06 is converted into an intermediate frequency by the high frequency circuit 807 and input to the FSK demodulator 808. The intermediate frequency received signal input to the FSK demodulator 808 is amplified by the buffer amplifier 902, and then input to the detection circuit 903 and demodulated. The demodulated signal is noise-removed by a low-pass filter (LPF) 904 and then input to a comparator 906 via a buffer amplifier 905. In the comparator 906,
The demodulated signal is compared with the reference voltage and binarized, and the digital signal 809 is output. This digital signal 80
9 is led to a data processing circuit at a subsequent stage (not shown) and used for desired processing.

[0007]

Generally, the receiving device is
Since the SN ratio decreases as the received signal level decreases,
If the received signal strength falls below a certain level, demodulation cannot be performed. This level is called a threshold level (minimum receiving sensitivity), and the demodulated waveform of the received signal having a signal strength near this threshold level is a superposition of noise. Depending on the application of the communication system, how much signal strength becomes the threshold level differs from each other, but generally when digital data is communicated, it is impossible to receive when a bit error starts to occur due to noise. Therefore, the reception signal strength higher than that in the case of communicating analog data becomes the threshold level.

This will be described in detail with reference to FIGS. 10 and 11 in the case of the FSK type wireless digital data communication system described above. FIG. 10 is a diagram showing an FSK-modulated signal vector, and FIG. 11 is a diagram showing waveforms of a demodulated signal containing noise and a digital signal obtained by binarizing the demodulated signal. FS input to the detection circuit 904
The K-modulated signal is a composite vector V of the signal component vector Vs and the noise component vector Vn as shown in A of FIG. Here, the magnitude of the signal component vector Vs changes according to the strength of the received signal, but the magnitude of the noise component vector Vn is constant and its vector phase is irrelevant to the signal component. It has been forgotten.

Here, when the signal component vector Vs is sufficiently larger than the noise component vector Vn as shown in FIG. 10B, the vector amount of the signal component becomes dominant in the composite vector V. No noise signal appears at the output. However, when the received signal strength decreases as shown in C of FIG. 10, the combined vector V
The influence of the noise component in becomes large, and the noise component appears in the output. When a signal containing such noise is detected, the demodulated signal output from the detection circuit 903 contains noise as shown in FIG. Then, when the signal is binarized by the comparator 906, a signal including a so-called mustache pulse as shown in FIG. 11B is output as a digital signal. If this output signal is directly input to the subsequent data processing circuit, incorrect data will be generated.

In particular, in the case of a wireless data communication system, a transmitted signal may reach a receiving device through a plurality of routes, that is, multipath may occur. In such a case, The signals propagating through a plurality of paths have different time delays. 12
FIG. 4 is a diagram conceptually showing each signal waveform when multipath occurs. In FIG. 12, 1201 to 1203
Indicates a relationship between received signals propagated through a plurality of paths, 1201 is a direct wave, 1202 is a first multipath signal propagated in a path different from the direct wave, 1202
Reference numeral 3 is a second multipath signal that has propagated through another path. The first multipath signal 1202 and the second multipath signal 1203 respectively have delay times τ1 and τ2 corresponding to the difference in signal path length with respect to the direct wave 1201.
It is received after the elapse. Therefore, the received signal is the direct wave and the first and second multipath signals superimposed, and the demodulated signal waveform thereof is the direct wave 1 as shown by 1204.
201 and the first and second multipath signals 1202 and 1203 are superimposed. In the digital signal 1205 obtained by binarizing such a demodulated signal, the first half of each bit becomes indefinite, and again erroneous data is generated.

As described above, in the digital data communication system, since a bit error occurs due to noise, there is a characteristic that a relatively high received signal strength becomes a threshold level. In addition, the multipath problem that occurs in wireless digital data communication is a fatal problem that reception becomes impossible regardless of the received signal strength. In particular, when a system with a high modulation speed such as a wireless LAN is used indoors where the multipath is highly likely to occur, the bit rate is high even if the delay due to the multipath is small, so the symbol Interference (between bits) is likely to occur, which is a big problem.

Therefore, the present invention provides a digital data transmitting apparatus, a receiving apparatus and a digital data communication system capable of improving the receiving threshold level (minimum receiving sensitivity) and reducing multipath interference. Is intended.

[0013]

In order to achieve the above object, the present invention uses a clock generator with a small frequency deviation in a digital data transmitting apparatus and a digital data receiving apparatus, and the digital data transmitting apparatus uses The preamble data composed of specific code data is inserted and the data is transmitted. In addition, the digital data receiving device detects the bit timing of the received data with high accuracy by sampling the received signal at a rate that is at least twice the bit rate of the transmitted data and correlating the preamble data from the sampled signal. Then, by determining each bit data of the received data signal received after the preamble data for each bit,
It is designed to reproduce a digital signal.

[0014]

By using a PN code (Pseudo Noise Code) having a sharp autocorrelation characteristic as the preamble data, correlation detection can be performed with high accuracy and each bit in the received data signal can be separated. Can be done accurately. Further, since the received data is sampled at a sampling rate twice or more the bit rate to make the determination, the influence of noise can be eliminated. Therefore, it is possible to reduce the minimum reception sensitivity and reduce multipath interference.

[0015]

FIG. 1 is a diagram showing an example of a transmission data packet transmitted from a digital data transmitting apparatus of the present invention. In FIG. 1, A is a preamble part, which is, for example, a PN code having a 11-bit length. B is an actual data section in which n-bit digital data to be transmitted is arranged, and C
Is a CRC (Cyclic Redundancy Check) code part.
A transmission data packet is composed of these three parts A, B and C.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the digital data transmitting apparatus of the present invention. In FIG. 2, 201 is a reference clock generator, 202 is a clock frequency divider, and 203 is a digital data output circuit for outputting digital data to be transmitted and generating and outputting the CRC code. Reference numeral 204 is a preamble data creating circuit for creating a PN code, 205 is a changeover switch, 20
6 is a modulation / transmission circuit for digitally modulating / amplifying transmission data, and 207 is a transmission antenna.

In the digital data transmitting apparatus thus constructed, the reference clock signal having a stable frequency generated by the reference clock generator 201 is input to the clock frequency divider 202. The clock divider 202 divides the input reference clock signal and outputs a timing pulse that defines the bit timing of the transmission data.
The timing pulse output from the clock frequency dividing circuit 202 is supplied to the digital data output circuit 203, and the digital data output circuit 203 outputs the data to be transmitted and the CRC code at the timing defined by the timing pulse. The timing pulse output from the clock divider circuit 202 is also supplied to the preamble data creation circuit 204, and the preamble data creation circuit 2
04 outputs a PN code at the timing defined by the timing pulse.

The changeover switch 205 is connected to the side of the preamble data forming circuit 204 during the preamble data transmission timing of the front part of the transmission packet and outputs the PN code output from the preamble data forming circuit 204 to the modulation / transmission circuit 206. However, after the preamble data transmission period ends, switching control is performed by a control unit (not shown) so as to connect to the digital data output circuit 203 side and output the transmission data and the CRC code from the digital data output circuit 203 to the modulation / transmission circuit 206. It By controlling in this way, it is possible to output a transmission data packet in which preamble data is combined with transmission data. The transmission data packet output from the changeover switch 205 is supplied to the modulation / transmission circuit and transmitted from the transmission antenna 207 toward the digital data receiving device.

3 to 5 are diagrams showing circuit configurations in an embodiment of the digital data receiving apparatus of the present invention. FIG.
In the figure, 301 is a receiving antenna, 302 is a high frequency circuit, and 303 is an FSK demodulator. These are the same as the receiving antenna 806, the high frequency circuit 807 and the FSK demodulator 808 in the conventional example shown in FIG. .
Reference numeral 304 denotes a reference clock generator, which has a small frequency deviation with respect to the reference clock generator 201 of the digital data transmitting apparatus. Reference numeral 305 is a frequency divider that divides the reference clock signal from the reference clock generator 304 so as to generate a sampling pulse having a frequency twice or more the bit rate of the transmission data. Generally, the frequency of the sampling pulse is preferably several times to several tens times the bit rate of the transmission data, and in this embodiment, 10 sampling pulses are generated for 1 bit. 306 is a sampling circuit, 307 is a correlation detection circuit, 308 is a data reproducing circuit, and 309 is a reproduced digital signal.

FIG. 4 is a diagram showing a detailed circuit configuration of the correlation detection circuit 307. In FIG. 4, b0 to b10 are each bit of the 11-bit PN code having the same content as the preamble data stored in the storage unit (not shown).
Reference numeral 400 denotes a terminal connected to the output of the sampling circuit 304, and the reception data sampled by the sampling circuit 306 is input from this terminal. 401
Numerals to 411 are bit correlation circuits provided corresponding to the respective bits b0 to b10 of the PN code and for obtaining the correlation between the binarized demodulated signal input from the terminal 400 and the PN code for each bit. Each of the bit correlation circuits 401 to 411 has therein 10 latch circuits L connected in series,
10 comparison circuits C for comparing the output of each latch circuit and the bit of the PN code corresponding to the bit correlation circuit,
And one adder A connected to the output of each comparison circuit C
Have DD. Here, each bit correlation circuit 401 to 4
Since 11 are connected in series, 110 latch circuits L in total form a shift register. Although not shown, the sampling pulse output from the frequency divider 305 is supplied to each latch circuit as a shift pulse. Reference numeral 420 denotes 11 of the bit correlation circuits 401 to 411.
An adder for adding the outputs of the adders ADD, 430 is a peak detection circuit for detecting the peak of the output value of the adder 420, and 440 is a correlation for generating a correlation timing signal based on the peak detection signal from the peak detection circuit 430. A timing signal generation circuit, and reference numeral 450 is a correlation timing signal output terminal.

FIG. 5 is a diagram showing the internal structure of the data reproducing circuit 308. In FIG. 5, 450 is a terminal to which the correlation timing signal from the correlation detection circuit 307 is supplied, and 5
00 is a terminal to which the sampling pulse from the frequency divider 305 is supplied, and 400 is a terminal to which the output of the sampling circuit 306 is supplied. Reference numeral 510 denotes a reference timing signal generation circuit which receives the correlation timing signal supplied from the terminal 450 and the sampling pulse supplied from the terminal 500 and outputs the reference timing signal every 10 sampling clocks from the time when the correlation timing signal is generated. L is a latch circuit, and ten latch circuits L are connected in series to form a shift register. And terminal 5
The sampling pulse supplied from 00 is supplied to each latch circuit L as a shift pulse. Reference numeral 520 is a determination circuit to which the output of each latch circuit L is input, and is, for example, a circuit for making a majority determination. 530 is a determination circuit 5
It is a switch circuit that connects the output of 20 to the output terminal 307 according to the timing signal from the reference timing signal generation circuit 510.

In the digital data receiving apparatus thus configured, the signal received by the receiving antenna 301 is amplified by the high frequency circuit 302, converted into an intermediate frequency, and input to the FSK demodulator 303. In the FSK demodulator 303, the received intermediate frequency received signal is demodulated and binarized. The processing up to this point is the same as in the case of the conventional technique described with reference to FIG. The received digital data output from the FSK demodulator 303 is supplied to the sampling circuit 306 and is sampled 10 times per bit by the sampling pulse supplied from the frequency divider 305. The received digital data sampled at a rate 10 times the bit rate is supplied to the correlation detection circuit 307 and the data reproduction circuit 308.

In the correlation detection circuit 307, the input terminal 4
Data input from the sampling circuit 306 to the latch circuit L in each bit correlation circuit 401 to 411.
Are sequentially input to the shift register constituted by. In each of the bit correlation circuits 401 to 411, the output of each latch circuit L is also supplied to the matching circuit C provided corresponding to each latch circuit, and in each matching circuit C, P
It is determined whether or not the contents of the bit corresponding to the bit correlation circuit of the N code match. The coincidence output from each coincidence circuit C is counted in the adder ADD, and the number of coincidence detections in the bit is counted. The count outputs from the adders ADD in the bit correlation circuits 401 to 411 are added in the adder 420, and the correlation between the PN code and the received digital data is output. FIG. 6 is a diagram showing an example of the correlation output output from the adder 420. The correlation output shows the maximum value when the sampling data is most correlated with the PN code as shown in FIG. The peak detection circuit 430 outputs a peak detection signal when the maximum value of the correlation output output from the adder 420 is detected, and the correlation timing signal generation circuit 440 receives the correlation timing signal when the peak detection signal is input. Is output to the terminal 450. In the present embodiment, sampling is performed 10 times per bit, so it is necessary to provide 10 coincidence circuits C per bit, but the correlation timing is detected with a resolution of 1/10 of 1 bit time. can do.

The correlation timing signal output from the correlation detection circuit 307 is supplied to the reference timing signal generation circuit 510 in the data reproduction circuit 308. A sampling pulse is also input from the terminal 500 to the reference timing signal generation circuit 510, and 1
The reference timing signal is output every 0 sampling pulse. FIG. 7 shows the relationship between the correlation timing signal 701 and the reference timing signal 702. In addition, the sampling circuit 30
The sampled received data string from 6 is input from the input terminal 400 to a shift register in which 10 latch circuits L are connected in series. The output of each latch circuit L of the shift register is input to the determination circuit 520, and the determination circuit 5
At 20, for example, a majority decision is made, and when the number of "1" output from each latch circuit L is more than half, "1" is output to the switch circuit 530 as a determination output as "0". Is output. Switch circuit 530
Outputs the determination output from the determination circuit 520 to the output terminal 307 as reproduction data according to the reference timing signal 702 from the reference timing signal generation circuit 510.

With this configuration, each bit of the data string of the actual data part B and the CRC code part C received after the time when the correlation timing signal 701 is generated is sampled by the reference timing pulse 702 for 10 samplings. It is separated into a pulse width window and a majority decision is made. Since the transmitter and the receiver use the clock generators 201 and 304 with small frequency deviation, each bit is separated by the reference timing signal 702 until the end of the packet after detecting the correlation timing signal. be able to. When the frequency deviation between the clock generators of the transmitter and the receiver is very small, or when the number of bits in each packet is small, one preamble is not inserted for each packet and one preamble is inserted for each packet. May be inserted.

In the above embodiment, the PN code is used as the preamble, but this is because the PN code has an excellent autocorrelation characteristic and has a steep correlation peak. If not necessarily P
It need not be N-coded. Further, although the above embodiment is an example in which the CRC code is added to the data to be transmitted, it is clear that any error correction code may be used without being limited to the CRC code, and an error may occur. Whether or not the correction code is added is also optional.

Further, although the FSK modulation system is adopted in the above-mentioned embodiment, it is obvious that any modulation system such as ASK, PSK, QAM can be applied similarly. Furthermore, although the case of the wireless transmission method has been described in the above embodiments, it is apparent that the same can be applied to the case of adopting another transmission method such as a wired transmission method. Furthermore, the present invention can be applied as it is when digital data is not modulated and is transferred as a baseband signal.

[0028]

According to the present invention, preamble data having a sharp autocorrelation characteristic such as a PN code is used to generate a reference timing pulse for subsequent bit data, so that it is possible to easily separate bits. In addition, by sampling the received signal a plurality of times with this signal as a reference, and further digitally integrating the input bit data by the majority decision,
Even in the case where the SN ratio is deteriorated or noise due to multipath is mixed in the input bits, high data recoverability can be ensured. Therefore, it is possible to reduce the minimum receiving sensitivity and reduce multipath interference.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a transmission data packet transmitted by a digital data transmission device of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of a digital data transmission device of the present invention.

FIG. 3 is a diagram showing a circuit configuration of an embodiment of a digital data receiving apparatus of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a correlation detection circuit in an embodiment of the digital data receiving apparatus of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a data reproducing circuit in an embodiment of the digital data receiving apparatus of the present invention.

FIG. 6 is a diagram showing an example of a correlation output.

FIG. 7 is a diagram showing a correlation timing signal and a reference timing signal.

FIG. 8 is a diagram showing a configuration of a conventional wireless digital data communication device.

FIG. 9 is an F in a conventional wireless digital data receiving device.
It is a figure which shows the internal structure of a SK demodulator.

FIG. 10 is a diagram showing an FSK-modulated signal vector.

FIG. 11 is a diagram showing waveforms of a demodulated signal including noise and a digital signal obtained by binarizing the demodulated signal.

FIG. 12 is a diagram showing each signal waveform when multipath occurs.

[Explanation of symbols]

 201, 304 Reference clock generator 202 Clock divider 203 Digital data output circuit 204 Preamble data creation circuit 205 Changeover switch 206 Modulation / transmission circuit 207, 805 Transmission antenna 301, 806 Reception antenna 302, 807 High frequency circuit 303, 808 FSK demodulator 305 Frequency divider 306 Sampling circuit 307 Correlation detection circuit 308 Data reproduction circuit 309 Regenerated digital signal 400, 450, 500, 901 Terminals 401-411 Bit correlation circuit 420 Adder 430 Peak detection circuit 440 Correlation timing signal generation Circuit 510 Reference timing signal generation circuit 520 Judgment circuit 530 Switch circuit 701 Correlation timing signal 702 Reference timing signal 801 Digital data 802 FSK Modulator 803 carrier generator 804 high frequency amplifier 809 digital signal 902,905 buffer amplifier 903 detection circuit 904 low-pass filter 906 comparator 1201 to 1205 signal waveform

Claims (7)

[Claims] 1. A digital data transmitting apparatus for transmitting digital data, comprising: a reference clock generator for generating a reference clock signal having a stable frequency; and dividing the reference clock signal to generate a timing pulse having a predetermined bit rate. Clock divider, a digital data output circuit for outputting digital data transmitted in synchronization with the timing pulse, and a preamble data generation circuit for outputting preamble data composed of specific code data in synchronization with the timing pulse And a changeover switch for coupling the preamble data and the digital data. 2. The digital data transmission device according to claim 1, wherein the preamble data is a PN code. 3. A digital data receiving apparatus for reproducing digital data from a received signal, a reference clock generator for generating a reference clock signal having a stable frequency, and a bit rate included in the transmitted data by dividing the reference clock signal. A frequency divider that generates a sampling pulse having a frequency that is at least twice the frequency, a demodulator that demodulates the received signal and binarizes the received digital data, and samples the received digital data by the sampling pulse, A sampling circuit that outputs sampled reception data, and a correlation detection circuit that detects the timing at which the correlation between the sampled reception data and preamble data that is composed of specific code data has a peak value, and outputs a correlation timing signal And a reference based on the correlation timing signal A digital data receiving apparatus, comprising: a data reproduction circuit that reproduces digital data by generating a timing signal and determining the sampled received data based on the reference timing signal. 4. The digital data receiving apparatus according to claim 3, wherein the preamble data is a PN code. 5. A digital data communication system comprising the digital data transmitting device according to claim 1 or 2 and the digital data receiving device according to claim 3 or 4. 6. The digital data communication system according to claim 5, wherein a wireless communication path is used as the transmission path. 7. The digital data communication system according to claim 6, wherein a wire transmission line is used as the transmission line.