JP2000068972A - Ofdm modulation/demodulation method and ofdm modulation/demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease mis-detection of timing and to reflect the timing mis- detection on timing control by detecting mis-detection of timing quickly in the orthogonal frequency division multiplex(OFDM) modulation/demodulation method and the OFDM modulation/demodulation circuit. SOLUTION: In the OFDM modulation method that generates an orthogonal frequency multiplex signal where a specific synchronizing signal SS is repetitively added to a signal part before signals that is differentially coded by information to be sent and information appearing precedingly to the information, a guard interval GI is formed between the synchronizing signals SS appearing repetitively and a repeating period Tss for the synchronizing signal is selected longer than a length Tw of each synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to orthogonal frequency division multiplexing (OFDM) used in digital radio communication.
The present invention relates to an OFDM modulation / demodulation method and an OFDM modulation / demodulation circuit used for processing a frequency division multiplexing signal, and more particularly to symbol timing synchronization.

[0002]

2. Description of the Related Art In digital radio communication, the burst format of an OFDM signal transmitted from a transmitter to a receiver generally has a configuration as shown in FIG. That is, at the head of the burst format, the same two start symbols SS used for timing synchronization, frequency deviation compensation, and differential coding initial value are repeatedly arranged, and thereafter, the guard interval GI and the data DA are used.
It is configured so that TA and TA appear alternately and repeatedly.

Each start symbol SS and data D
The length of the ATA on the time axis is determined to be the same as a predetermined Fourier transform window time Tw. That is, the entire data DATA having the length of the window time Tw is subjected to one Fourier transform as one symbol signal. For data to be transmitted, encoding is performed on the difference between the data and data that appears, for example, one symbol before. A start symbol is used as an initial value for such differential encoding. That is, when encoding the first data, the difference between the start symbol and the data is encoded.

In order to reduce the effects of delayed waves, O
In the guard interval GI of the FDM signal, the same signal as the data DATA repeatedly appears. That is, the guard interval GI includes the following data DATA.
The same content as the back part of the appears cyclically. Therefore, even if the synchronization with the reception is slightly shifted due to the delayed wave, the missing information can be supplemented by the signal component appearing in the guard interval GI. Therefore, the signal of one entire symbol of the data DATA is input to the Fourier transform processing and received. The signal can be demodulated.

[0005] The start symbol added to the head of the burst format is not differentially encoded.
It is encoded as it is. In order to generate an OFDM signal modulated in a burst format as shown in FIG.
The M modulation circuit generally includes a differential encoding circuit, a start symbol memory circuit, a start symbol addition circuit, an inverse Fourier transform circuit, a guard interval insertion circuit, and a digital-analog conversion circuit.

FIG. 9 shows a configuration example of a conventional OFDM demodulation circuit provided in a receiver for demodulating an OFDM signal as shown in FIG. The reception signal input to the OFDM demodulation circuit shown in FIG. 9 is input to a synchronization circuit and a delay circuit after analog-to-digital conversion. The synchronous circuit detects a carrier frequency error between the transmitting and receiving apparatuses and an optimal timing by detecting a continuous start symbol SS in the received signal.

For the specific configuration and operation of this type of synchronous circuit, see, for example, Reference 1 “Onizawa, Mizoguchi, Kumagaya, Takanashi,
Morikura, “Study on Synchronous System of OFDM Modulation System for High-Speed Wireless LAN”, IEICE Technical Report, RCS97-210, and Reference 2 “TMSchmid and DCCox,“ Low-Overhead, Low ”
−Complexity [Burst] Synchronization for OFD
M ", ICC'96, pp. 1301-1306".

The delay circuit shown in FIG. 9 delays a received signal until a frequency deviation and an optimum timing are detected by a synchronous circuit. The frequency correction circuit corrects the received signal with a correction phase signal that is the detected frequency deviation. The received signal corrected by the frequency correction circuit is subjected to fast Fourier transform by a Fourier transform (FFT or DFT) circuit after removing the guard interval GI based on the optimum symbol timing detected by the synchronous circuit.

The received signal output from the Fourier transform circuit is subjected to delay detection for each subcarrier by a delay detection circuit and demodulated into transmitted data. Actually, the signal output from the delay detection circuit is sent to an error correction unit (not shown). Then, after detecting the burst timing based on the signal obtained as a result of the error correction and the known unique word UW, the transmission data is extracted.

[0010]

As described above, in an OFDM demodulation circuit of a receiver, a start symbol SS repeatedly appearing at the beginning of a burst format of a received signal is conventionally detected by frequency deviation detection, timing synchronization, and delay detection. Used for value. When such a method is used, even if erroneous detection of timing occurs on the receiver side, it is difficult to immediately determine the erroneous detection.

As a countermeasure, the addition of a unique word (UW) to the burst format can be considered, but they reduce transmission efficiency as redundant bits. In addition, on the premise of using CRC (Cyclic Redundancy Check), a method of detecting erroneous timing detection as a CRC error at the CRC check timing can be considered. However, if a correct burst arrives during the time span of the length of the transmitted burst, the burst is not detected, and the problem of an increased probability of non-detection arises.

The present invention relates to an OFDM modulation / demodulation method and OFD
It is an object of the present invention to reduce the occurrence of erroneous detection of timing in an M modulation / demodulation circuit, and to quickly detect the occurrence of erroneous detection of timing and reflect it in timing control.

[0013]

A first aspect of the present invention is an orthogonal frequency multiplexing method in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before that. In the OFDM modulation method for generating a signal, a guard interval is formed between the repeatedly appearing synchronization signals, and a repetition period of the synchronization signal is made longer than a length of each synchronization signal.

When receiving and processing an OFDM signal in a burst format as shown in FIG. 8, a start symbol (synchronization signal) S at the head of the burst format is used.
The start symbol SS can be detected from the correlation between two received signals having a time difference matching the window time Tw, which is the repetition period of S. That is, 2
When the correlation value between two received signals is large, it is considered that the first start symbol SS is referred to from the delayed preceding received signal and the second start symbol SS is referred to from the undelayed received signal. Therefore, the timing can be regarded as the timing at which the start symbol SS appears.

However, in the case of the burst format OFDM signal shown in FIG. 8, the guard interval GI
The same signal is repeated at a period that coincides with the window time Tw in a region composed of the data DATA following the data, so that not only the timing of the start symbol SS but also the guard interval GI and the subsequent data DATA appear. Also in timing, a large correlation occurs between two received signals having a time difference matching the window time Tw. Therefore, there is a high probability that an error occurs in the timing detection of the start symbol SS.

According to the first aspect of the present invention, a guard interval GI is provided between synchronization signals (SS) repeatedly appearing.
Is formed, the repetition period of the synchronization signal becomes larger than the length (Tw) of each synchronization signal.
The OFDM signal is transmitted in a format as shown in FIG. When the receiving side receives and demodulates such an OFDM signal, the time period Tss for detecting the correlation between two repeatedly appearing synchronization signals is larger than the length Tw of the synchronization signal. In this case, at the timing when the guard interval GI and the subsequent data DATA appear, the repetition period (Tw) of the same signal is different from the time period Tss for detecting the correlation.
And the correlation value detected for the region constituted by the data DATA becomes smaller.

Therefore, the probability of erroneously detecting the guard interval GI and the data DATA instead of the synchronization signal is reduced. Claim 2 is a reception signal obtained by receiving an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before that. In the OFDM demodulation method, the timing at which the synchronization signal repeatedly appears is detected from a received signal, and the signal components of each of a plurality of subcarriers included in the received signal and a predetermined value corresponding to an ideal transmission path state are detected. Finding the degree of coincidence with, and adding the degree of coincidence for a plurality of subcarriers included in the received signal, and reflecting the result of comparing the result of adding the degree of coincidence with a predetermined threshold value to the demodulation control of the received signal. It is characterized by.

An OFDM signal contains many subcarrier components having different frequencies from each other. When an OFDM signal is transmitted using an ideal communication path, at the timing when the synchronization signal repeatedly appears, the components of each subcarrier appearing in the detection output of the received signal have the same value. However, at the timing when a signal other than the synchronization signal appears, values independent of each other appear in the components of each subcarrier.

According to a second aspect of the present invention, a degree of coincidence between each signal component of the plurality of subcarriers and a predetermined value corresponding to an ideal transmission path state is obtained, and the degree of coincidence is added for a plurality of subcarriers. Since the result of adding the coincidence is compared with a predetermined threshold value, the result of the comparison corresponds to whether or not the timing at which the synchronization signal is detected is correct. Therefore, immediately after detecting the timing of the synchronization signal, it can be determined whether or not the timing is correct.

A third aspect of the invention is an OFDM modulation for generating an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before that. A start symbol memory circuit for storing a start symbol that is an initial value of differential encoding, and a differential encoding for differentially encoding an input signal with the start symbol stored in the start symbol memory circuit as an initial value. Circuit, a start symbol addition circuit that arranges a start symbol output by the start symbol memory circuit before a signal output by the differential encoding circuit, a signal output by the differential encoding circuit, and a signal added thereto. An inverse fast Fourier transform circuit for performing an inverse fast Fourier transform of the signal of the start symbol, and an output from the inverse fast Fourier transform circuit. A guard interval adding circuit for adding a guard interval between the plurality of start symbols repeatedly appearing to each of the OFDM symbols and a digital-analog converting circuit for processing a signal output by the guard interval adding circuit. Is provided.

The start symbol memory circuit stores a start symbol. The differential encoding circuit differentially encodes the input signal using the start symbol as an initial value. The start symbol adding circuit arranges the start symbol before a signal output from the differential encoding circuit. Also,
The inverse fast Fourier transform circuit performs an inverse fast Fourier transform on the signal output from the differential encoding circuit and the added start symbol. The guard interval adding circuit applies each OF to the signal output from the inverse fast Fourier transform circuit.
A guard interval is added between a plurality of start symbols that appear repeatedly as well as a DM symbol. The digital-analog conversion circuit processes the signal output from the guard interval addition circuit.

Since the guard interval adding circuit adds a guard interval between a plurality of start symbols that appear repeatedly, the repetition period of the start symbol can be made longer than the length of each start symbol. . Therefore, the probability of erroneously detecting the guard interval GI and the data DATA instead of the synchronization signal is reduced.

According to a fourth aspect of the present invention, a signal obtained by receiving an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before that is obtained. In an OFDM demodulation circuit for demodulating a received signal to be received, an analog-to-digital conversion circuit for analog-to-digital conversion of the received signal, and a reception signal output from the analog-to-digital conversion circuit are inputted to detect a frequency deviation and timing synchronization. A delay circuit that outputs a signal obtained by delaying a reception signal output by the analog-digital conversion circuit, and corrects a frequency deviation of a signal output by the delay circuit with a correction phase signal output by the synchronization circuit. A frequency correction circuit, and an optimal synth detected by the synchronization circuit from a frequency-corrected reception signal output from the frequency correction circuit. In synchronism with the Le timing, a guard interval removing circuit for removing a component of the guard interval, a Fast Fourier transform circuit for fast Fourier converting the received signal the guard interval removing circuit outputs,
A delay detection circuit for delay-detecting a signal output from the fast Fourier transform circuit; and a predetermined signal corresponding to an ideal transmission path state for each signal component of a plurality of subcarriers included in the reception signal output from the delay detection circuit. A coincidence detection circuit that calculates a degree of coincidence with a value and adds the degree of coincidence to a plurality of subcarriers included in the received signal.
A comparison circuit that compares an addition result of the coincidence detection circuit with a predetermined threshold value and outputs a reset signal for resetting the synchronization circuit when the addition result does not exceed the threshold value. Features.

The analog-to-digital converter converts the received signal from analog to digital. The synchronization circuit receives the reception signal output from the analog-digital conversion circuit and detects a frequency deviation and timing synchronization. The delay circuit outputs a signal obtained by delaying the reception signal output from the analog-digital conversion circuit. The frequency correction circuit corrects a frequency deviation of a signal output from the delay circuit with a correction phase signal output from the synchronization circuit. The guard interval removing circuit removes a guard interval component from the frequency-corrected received signal output from the frequency correcting circuit in synchronization with the optimum symbol timing detected by the synchronizing circuit.

The fast Fourier transform circuit performs a fast Fourier transform on the received signal output from the guard interval removing circuit. The delay detection circuit performs delay detection on a signal output from the fast Fourier transform circuit. The coincidence detection circuit obtains a degree of coincidence with a predetermined value corresponding to an ideal transmission path state for each signal component of a plurality of subcarriers included in the received signal output by the differential detection circuit, and determines the degree of coincidence with the received signal. The addition is performed for a plurality of subcarriers included in the signal.

The comparison circuit compares the addition result of the coincidence detection circuit with a predetermined threshold value, and outputs a reset signal for resetting the synchronization circuit if the addition result does not exceed the threshold value. Since the reset signal output from the comparison circuit corresponds to whether or not the timing at which the synchronization signal is detected is correct, the timing is correct immediately after detecting the timing of the synchronization signal, as in the second aspect. Can be determined.

According to a fifth aspect of the present invention, in the OFDM demodulation circuit according to the fourth aspect, the synchronization circuit calculates a squared circuit for calculating the power of the received signal and a first average for calculating a moving average with respect to time of the signal output from the squared circuit. A moving average circuit, a delay circuit that outputs a signal obtained by delaying a received signal, a phase rotation angle detection circuit that performs complex multiplication of the reception signal and the reception signal delayed by the delay circuit, and the phase rotation angle detection circuit A second moving average circuit that calculates a moving average of a signal to be output with respect to time, based on a signal output by the first moving average circuit and a signal output by the second moving average circuit,
A timing detection circuit for outputting a timing signal indicating an optimal timing, and a frequency error of the received signal detected based on a signal output from the second moving average circuit, and a corrected phase signal having an opposite phase to the frequency error is output. And a reset signal output from the comparison circuit is applied to the timing detection circuit and the frequency error estimation circuit.

The squaring circuit calculates the power of the received signal.
The first moving average circuit calculates a moving average of a signal output from the square circuit with respect to time. The delay circuit outputs a signal obtained by delaying the received signal. The phase rotation angle detection circuit
A complex multiplication of the reception signal and the reception signal delayed by the delay circuit is performed. The second moving average circuit calculates a moving average of the signal output from the phase rotation angle detection circuit with respect to time. The timing detection circuit outputs a timing signal indicating an optimal timing based on a signal output from the first moving average circuit and a signal output from the second moving average circuit.

The frequency error estimating circuit detects a frequency error of the received signal based on the signal output from the second moving average circuit, and outputs a corrected phase signal having a phase opposite to the frequency error. The reset signal output from the comparison circuit is applied to the timing detection circuit and the frequency error estimation circuit. Therefore, when the timing of the signal for synchronization is erroneously detected, the timing detection circuit and the frequency error estimating circuit are initialized immediately thereafter, so that the timing synchronization is released.

[0030]

1 to 7 show an embodiment of an OFDM modulation circuit and an OFDM demodulation circuit embodying the present invention. This form corresponds to all claims. FIG. 1 is a block diagram showing an OFDM modulation circuit of this embodiment. FIG. 2 is a time chart showing the burst format of this embodiment. FIG. 3 is a block diagram showing an OFDM demodulation circuit of this embodiment. FIG. 4 is a block diagram showing a synchronous circuit of this embodiment. FIG. 5 is a block diagram showing a match detection circuit of this embodiment. FIG. 6 is a time chart showing signal timings of the OFDM demodulation circuit of this embodiment. FIG. 7 is a graph showing the result of a simulation of the false detection rate.

In this embodiment, the synchronizing signal and the guard interval of the first aspect each include the start symbol SS
And the guard interval GI. The start symbol memory circuit, the differential encoding circuit, the start symbol adding circuit, the inverse fast Fourier transform circuit, the guard interval adding circuit, and the digital-analog converting circuit according to the third aspect of the present invention are the SS memory circuit 11, the differential encoding It corresponds to the circuit 10, the SS addition circuit 12, the inverse FFT circuit 13, the GI insertion circuit 14, and the D / A conversion circuit 15.

The analog-to-digital conversion circuit, the synchronization circuit, the delay circuit, the frequency correction circuit, the guard interval elimination circuit, the fast Fourier conversion circuit, the delay detection circuit, the coincidence detection circuit, and the comparison circuit according to claim 4 are each an A / D converter. It corresponds to the circuit 20, the synchronization circuit 22, the delay circuit 21, the frequency correction circuit 23, the GI removal circuit 24, the FFT circuit 25, the delay detection circuit 26, the coincidence detection circuit 27, and the comparison circuit 28.

The squaring circuit, the first moving average circuit, the delay circuit, the phase rotation angle detecting circuit, the second moving average circuit, the timing detecting circuit, and the frequency error estimating circuit according to claim 5 are respectively composed of the square circuit 30, the first Moving average circuit 33, delay circuit 32, phase rotation angle detection circuit 31, second moving average circuit 3
4. Timing detection circuit 35 and frequency error estimation circuit 3
Corresponds to 6.

The burst format of the OFDM signal generated by the OFDM modulation circuit shown in FIG. 1 as a transmission signal and the burst format of the OFDM signal input as a reception signal to the OFDM demodulation circuit shown in FIG. 3 are as shown in FIG. As shown in FIG. 2, the burst of the OFDM signal does not include a unique word (UW). At the beginning of the burst, a guard interval GI and a start symbol SS are arranged so as to be repeated twice. The start symbol SS arranged before and the start symbol SS arranged after are the same signal.

After these start symbols SS,
Guard interval GI and transmission data DA of one symbol
TA appears alternately and repeatedly. The transmission data DATA is a differentially encoded signal. The length of each of the start symbol SS and the transmission data DATA is set to be the same as the window time Tw of the Fourier transform. The cycle Tss in which the start symbol SS repeatedly appears is a length obtained by adding the window time Tw and the length of the guard interval GI, and is sufficiently larger than the window time Tw.

In the period of the guard interval GI arranged before the transmission data DATA, the same signal as the content of the rear part of the subsequent transmission data DATA appears. In the range T0 up to the rear end of the transmission data DATA,
The same signal appears repeatedly in the cycle of the window time Tw.

The OFDM modulation circuit shown in FIG. 1 includes a differential encoding circuit 10, an SS memory circuit 11, an SS adding circuit 12,
It comprises an inverse FFT circuit 13, a GI insertion circuit 14, and a D / A conversion circuit 15. Input data input to the OFDM modulation circuit shown in FIG. 1 is differentially encoded for each subcarrier. The input data and the signal handled by the OFDM modulation circuit are complex signals composed of two signals, an in-phase component (Ich) and a quadrature component (Qch).

The data of the start symbol SS stored in the SS memory circuit 11 is applied to the differential encoding circuit 10 as an initial value. Differentially encoded data DATA
, Two start symbols SS read from the SS memory circuit 11 are repeatedly added by the SS adding circuit 12. A signal composed of two start symbols SS and differentially encoded data DATA is inverted F
The signal is input to the FT circuit 13 and subjected to inverse fast Fourier transform.
A guard interval GI is added to the signal output from the inverse FFT circuit 13 by the GI insertion circuit 14 before all data including the start symbol SS.

The signal output from the GI insertion circuit 14 is
The signal is converted into an analog signal by the D / A conversion circuit 15 and output as a transmission signal. The OFDM demodulation circuit shown in FIG.
A / D conversion circuit 20, delay circuit 21, synchronization circuit 22, frequency correction circuit 23, GI removal circuit 24, FFT circuit 2
5, a delay detection circuit 26, a coincidence detection circuit 27, and a comparison circuit 28.

The received signal input to the OFDM demodulation circuit shown in FIG. 3 and the signal handled by the OFDM demodulation circuit are complex signals composed of two signals of an in-phase component (Ich) and a quadrature component (Qch). . The received signal is converted into a digital signal by the A / D conversion circuit 20 and input to the delay circuit 21 and the synchronization circuit 22.

The synchronization circuit 22 detects the start symbol SS that repeatedly appears at a cycle Tss at the beginning of the burst of the received signal, thereby detecting the frequency error of the carrier between the transmitter and the receiver and the optimum symbol timing. That is, when the correlation between the received signal and the signal delayed by the same time as the period Tss is detected, a large correlation is detected at the timing when the start symbol SS repeats. Therefore, the start position of the burst of the received signal and the OFDM demodulation circuit Timing can be adjusted.

As shown in FIG. 4, the actual synchronization circuit 22 includes a square circuit 30, a phase rotation angle detection circuit 31, a delay circuit 32, a first moving average circuit 33, a second moving average circuit 34,
It comprises a timing detection circuit 35 and a frequency error estimation circuit 36. The squaring circuit 30 calculates the square of the received signal input thereto and obtains the magnitude of the signal power. The first moving average circuit 33 calculates a moving average value of the signal output from the square circuit 30.

The phase rotation angle detection circuit 31 calculates the phase rotation angle based on the input received signal and the signal delayed by the delay circuit 32. The second moving average circuit 34 calculates a moving average of the signal output from the phase rotation angle detection circuit 31. The timing detection circuit 35 includes a first moving average circuit 33
And the signal output from the second moving average circuit 34, and detects the optimal symbol timing. The frequency error estimating circuit 36 detects a frequency error based on the signal output from the second moving average circuit 34.

The description will be continued with reference to FIG. The delay circuit 21 delays the received signal until the frequency deviation and the timing are detected by the synchronization circuit 22. The frequency correction circuit 23 corrects the received signal using a correction phase signal corresponding to the frequency error detected by the synchronization circuit 22.

The reception signal whose frequency has been corrected by the frequency correction circuit 23 is sent to the GI removal circuit 24 by the synchronization circuit 22.
All guard interval GI components are removed according to the optimal symbol timing output from. GI
The signal output from the removal circuit 24 is input to the FFT circuit 25 and is subjected to fast Fourier transform. The signal output from the FFT circuit 25 is input to the delay detection circuit 26 for each subcarrier and subjected to delay detection.

The signal output from the delay detection circuit 26 is output as a demodulated output signal. A part of this signal is input to the coincidence detection circuit 27 as a signal D1. Actually, the signal D1 input to the coincidence detection circuit 27 is the in-phase component (Ic) of the signal output from the delay detection circuit 26.
h) and the most significant bit (MSB) of the quadrature component (Qch signal). The specific configuration of the coincidence detection circuit 27 is shown in FIG.

In the signal subjected to delay detection in the start symbol SS repetition section at the head of the burst of the received signal, all the subcarriers have the same value if the channel state is ideal. Therefore, the coincidence detection circuit 27 obtains a likelihood value indicating the degree of coincidence between the value obtained when the communication path state is in an ideal state and the actual differential detection output, and adds the likelihood value for all subcarriers. Find the sum.

In FIG. 5, reference signal (0,0) 42
Corresponds to a value obtained when the communication channel state is an ideal state. In this embodiment, the signal components of the 48 subcarriers appear in the output of the delay detection circuit 26 in a time-series manner.
Using the serial-parallel conversion circuit 41, signal components (two bits of Ich and Qch, respectively) of 48 subcarriers are extracted from the 48 output terminals P1 to P48.

Forty-eight exclusive OR circuits (Exnor)
43 (1) to 43 (48) output signals indicating coincidence / mismatch with respect to the signal components of the respective subcarriers. 48
The sum of the signals output from the exclusive-OR circuits 43 (1) to 43 (48) is calculated by the adder circuit 44, and the result is output as the signal D
Output as 2.

In the OFDM demodulation circuit shown in FIG.
The signal D2 output from the coincidence detection circuit 27 is input to the comparison circuit. The comparison circuit 28 compares the signal D2 with a predetermined threshold D3. Here, if the value of the signal D2 exceeds the value of the threshold D3, it is regarded as normal synchronization, and if not, it is regarded as erroneous synchronization and the reset signal RST is output. This reset signal is sent to the synchronization circuit 22 by the timing detection circuit 35.
And to initialize the operation of the frequency error estimating circuit 36.

When the operation is initialized by the reset signal RST, the synchronization circuit 22 estimates the frequency error and detects the timing again. FIG. 6 shows the signal timing of each part of the OFDM demodulation circuit in FIG. In FIG. 6, each data (DAT) included in the burst of the received signal is shown.
The area A) is indicated by X1, X2, X3, X4, and X5. As shown in FIG. 6, immediately after the start symbol SS included in the burst of the received signal appears, it is determined whether or not a synchronization error has occurred. If a synchronization error is detected, the reset signal RST is activated. become.

The OFDM demodulation circuit shown in FIG.
With respect to the FDM demodulation circuit, the false detection probability of timing synchronization was examined by simulation. The result is shown in FIG. Referring to FIG. 7, it can be seen that the present invention improves the probability of false detection of timing synchronization.

[0053]

The OFDM modulation method and OFDM of the present invention
According to the modulation circuit, as shown in FIG. 2, a guard interval GI is inserted between a plurality of start symbols SS repeatedly added to the head of the burst, and the start symbols S
By making the repetition period Tss of S larger than the repetition period (Tw) of the region of the data DATA, the influence of the correlation of the Tw period due to the repetition of the signal of the region of the data DATA in the correlation detection for detecting the start symbol SS. Is suppressed. For this reason, the probability of occurrence of erroneous detection of the synchronization timing is reduced.

The OFDM demodulation method and OFD of the present invention
In the M demodulation circuit, for each of the signal components of the plurality of subcarriers included in the received signal, the degree of coincidence between the signal after delay detection and a predetermined value corresponding to an ideal transmission path state is obtained. By adding the degree of coincidence and comparing the result with a predetermined threshold value, it is possible to judge erroneous detection of timing synchronization without delay.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an OFDM modulation circuit according to an embodiment.

FIG. 2 is a time chart showing a burst format according to the embodiment.

FIG. 3 is a block diagram illustrating an OFDM demodulation circuit according to the embodiment;

FIG. 4 is a block diagram illustrating a synchronization circuit according to the embodiment;

FIG. 5 is a block diagram illustrating a match detection circuit according to the embodiment;

FIG. 6 is a time chart illustrating signal timings of the OFDM demodulation circuit according to the embodiment;

FIG. 7 is a graph showing a result of a simulation of an erroneous detection rate.

FIG. 8 is a time chart showing a conventional burst format.

FIG. 9 is a block diagram showing a conventional OFDM demodulation circuit.

[Explanation of symbols]

 Reference Signs List 10 differential encoding circuit 11 SS memory circuit 12 SS addition circuit 13 inverse FFT circuit 14 GI insertion circuit 15 D / A conversion circuit 20 A / D conversion circuit 21 delay circuit 22 synchronization circuit 23 frequency correction circuit 24 GI removal circuit 25 FFT Circuit 26 Delay detection circuit 27 Match detection circuit 28 Comparison circuit 30 Square circuit 31 Phase rotation angle detection circuit 32 Delay circuit 33 First moving average circuit 34 Second moving average circuit 35 Timing detection circuit 36 Frequency error estimation circuit 41 Serial-parallel conversion Circuit 42 Reference signal 43 Exclusive OR circuit 44 Adder circuit SS Start symbol GI Guard interval

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masahiro Umehira 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo F-term within Nippon Telegraph and Telephone Corporation 5K004 AA01 BA02 BB06 5K022 DD13 DD17 DD23 DD33 DD42 5K047 AA02 AA04 BB01 CC01 EE00 HH01 HH11 HH43 HH55 JJ04 MM12 MM24

Claims (5)

[Claims] An OFD for generating an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before the information.
In the M modulation method, a guard interval is formed between the repeatedly appearing synchronization signals, and a repetition period of the synchronization signal is made longer than a length of each synchronization signal.
FDM modulation method. 2. A received signal obtained by receiving an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before the signal. In the OFDM demodulation method, a timing at which the synchronization signal repeatedly appears is detected from a received signal, and a signal component of each of a plurality of subcarriers included in the received signal and a predetermined value corresponding to an ideal transmission path state Calculating the degree of coincidence with the received signal, adding the degree of coincidence for a plurality of subcarriers included in the received signal, and reflecting the result of comparing the result of addition of the degree of coincidence with a predetermined threshold value on the demodulation control of the received signal. OF characterized by
DM demodulation method. 3. An OFD that generates an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal that is differentially encoded with information to be transmitted and information that appears before the signal.
In the M modulation circuit, a start symbol memory circuit that stores a start symbol that is an initial value of differential encoding, and a differential symbol that differentially encodes an input signal using the start symbol stored in the start symbol memory circuit as an initial value. An encoding circuit; a start symbol addition circuit for arranging a start symbol output by the start symbol memory circuit before a signal output by the differential encoding circuit; a signal output by the differential encoding circuit; An inverse fast Fourier transform circuit for performing an inverse fast Fourier transform on the signal of the generated start symbol, and for a signal output from the inverse fast Fourier transform circuit, between a plurality of the start symbols repeatedly appearing and for each OFDM symbol. A guard interval adding circuit for adding a guard interval; OFDM modulation circuit, characterized in that a analog converter - digital-de interval adding circuit for processing the signal output. 4. A received signal obtained by receiving an orthogonal frequency multiplexed signal in which a specific synchronization signal is repeatedly added before a signal differentially encoded with information to be transmitted and information appearing before the information. An OFDM demodulation circuit for demodulating the received signal; an analog-to-digital conversion circuit for performing an analog-to-digital conversion of the reception signal; and a synchronization circuit for receiving the reception signal output from the analog-to-digital conversion circuit and detecting frequency deviation and timing synchronization. A delay circuit that outputs a signal obtained by delaying a reception signal output by the analog-digital conversion circuit; and a frequency correction circuit that corrects a frequency deviation of a signal output by the delay circuit with a correction phase signal output by the synchronization circuit. An optimal symbol type detected by the synchronization circuit from a frequency-corrected reception signal output by the frequency correction circuit. A guard interval removing circuit that removes a guard interval component in synchronization with the ringing, a fast Fourier transform circuit that performs a fast Fourier transform on a received signal output by the guard interval removing circuit, and a signal that is output by the fast Fourier transform circuit. A delay detection circuit that performs delay detection, and obtains a degree of coincidence with a predetermined value corresponding to an ideal transmission path state for each signal component of a plurality of subcarriers included in a received signal output by the delay detection circuit, A coincidence detection circuit that adds the degree of coincidence for a plurality of subcarriers included in the received signal, and compares an addition result of the coincidence detection circuit with a predetermined threshold, and when the addition result does not exceed the threshold, A comparison circuit for outputting a reset signal for resetting the synchronization circuit. M demodulation circuit. 5. The OFDM demodulation circuit according to claim 4,
A squaring circuit for calculating the power of a received signal; a first moving average circuit for calculating a moving average of a signal output by the squaring circuit with respect to time; and a delay circuit for outputting a signal obtained by delaying a received signal A phase rotation angle detection circuit that performs complex multiplication of a reception signal and a reception signal delayed by the delay circuit; and a second moving average circuit that calculates a moving average of a signal output by the phase rotation angle detection circuit with respect to time. A timing detection circuit that outputs a timing signal indicating an optimal timing based on a signal output by the first moving average circuit and a signal output by the second moving average circuit; A frequency error estimating circuit for detecting a frequency error of the received signal based on a signal output from the circuit and outputting a corrected phase signal having an opposite phase to the frequency error, An OFDM demodulation circuit, wherein a reset signal output from the comparison circuit is applied to the timing detection circuit and the frequency error estimation circuit.