JP4503796B2 - Synchronization signal generating method, receiving apparatus, and recording medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronization signal generating method for receiving a packet signal having a repeated signal added a plurality of times at the beginning and generating a synchronization signal from the received signal, a receiving apparatus including a synchronization signal generating unit, and synchronization The present invention relates to a computer-readable recording medium that records a program for causing a computer to generate a signal. In particular, the present invention is preferably applied to a communication system that performs packet communication in bursts. Note that “performing packet communication in a burst” means that packet communication is performed in a non-continuous manner with incomplete synchronization.
[0002]
[Prior art]
In a communication system that performs packet communication in bursts, the arrival of a packet signal cannot be predicted. Therefore, the receiving side needs to perform independent demodulation and synchronization processing for each packet. For this reason, a technique has been proposed in which a known N number of repeated signals are added to the beginning of the packet as a preamble, and the receiving side discriminates the repeated signal attached to the beginning of the packet to generate a synchronization signal. For example, the 1999 IEICE Communication Society Conference B-5-61 “Characteristics of Symbol Timing Detection Circuit for OFDM Wireless LAN System” is a peak integration process using a digital filter for the correlator output (correlation peak signal) of the received signal. By doing so, what generates a synchronization signal is described.
[0003]
[Problems to be solved by the invention]
The synchronization signal generator that generates this synchronization signal is configured as shown in FIG. The synchronization signal generation unit includes a delay unit 101, a matched filter (MF) 102, an absolute value unit 103, a power detection unit 104, a division unit 105, a preamble interval integration unit 106, and a maximum value detection unit 107. It is composed of
[0004]
When the repetition signal in the preamble is 10 times and each repetition signal has a 16 sample period (T in the figure represents a sample period), the received signal is delayed by 16 sample periods in the delay unit 101. Then, the matched filter 102 correlates the received signal X with the received signal Y delayed by the delay unit 101.
[0005]
The matched filter 102 is configured as shown in FIG. The reception signal (signal represented by a complex number) X is complex-conjugated by the complex conjugate unit 1021, and the output signal is sequentially delayed by the delay unit 1022. Coefficients c15, c14, c13, c12,..., C2, c1, c0 are generated from the reception signal Y delayed by the delay unit 101 and a signal obtained by sequentially delaying the received signal Y by the delay unit 1023. The output signal of the complex conjugate device 1021 and the output signal of each delay unit 1022 are multiplied by coefficients c15, c14, c13, c12,..., C2, c1, c0, respectively, in a multiplier 1024, and each multiplication result is added in an adder unit 1025. Is added. Then, the correlation value signal of the received signal is output from the adder 1025.
[0006]
The power detection unit 104 is configured as shown in FIG. The received signal is sequentially delayed by the delay unit 1041. The reception signal and the output signal of each delay section 1041 are multiplied by the output signal of the complex conjugate section 1042 that takes the complex conjugate of the respective signals in the multiplier 1043, and each multiplication result is added in the addition section 1044. Then, a signal indicating the power of the received signal is output from the adder 1044.
[0007]
The correlation value signal output from the matched filter 102 is converted into an absolute value by the absolute value unit 103, and the output of the absolute value unit 103 is divided by the output of the power detection unit 104 by the division unit 105. As a result, a normalized correlation value signal is output from the division unit 105.
[0008]
The normalized correlation value signal is integrated by a preamble interval (that is, 16 × 10T) in the preamble interval integrator 106. An integrated value is output from the preamble interval integrating unit 106 every sample synchronization T. The timing at which the integral value is equal to or greater than a predetermined threshold and becomes the maximum value is detected by the maximum value detection unit 107, and a synchronization signal is output.
[0009]
However, when the synchronous signal generation unit configured as described above has been studied from the viewpoint of hardware configuration, when the multiplication unit and the addition unit are configured by a circuit, the scale becomes large. It was found that there were problems such as errors.
[0010]
The present invention has been made in view of the above problems, and an object of the present invention is to generate a synchronization signal without using a matched filter or the like.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention focuses on the fact that each repeated signal in the preamble is the same signal, and its value becomes extremely small when the difference between the repeated signals is taken. That is, the synchronization signal can be generated by using the difference between the received signals in units of cycles of each repetitive signal without using the correlation value as described above.
[0012]
The present invention has been made on the basis of the above-described studies. In the invention according to claim 1, a packet signal having a plurality of known repeated signals added to the head is received, and a synchronization signal is generated from the received signal. In the synchronizing signal generation method, the difference between two received signals differing by a predetermined period of the repetitive signal is taken, the absolute value thereof is integrated, and the synchronizing signal is output at a timing at which the integrated value is minimized. It is said.
[0013]
According to the present invention, it is possible to generate a synchronization signal without using a matched filter or the like.
[0014]
The invention according to claim 2 is a more specific embodiment of the invention according to claim 1, wherein the I component and the Q component of the received signal are two signals different from each other by a predetermined period of the repetitive signal. The absolute value is obtained by taking the difference, the respective absolute values are added, the added values are integrated, and the synchronization signal is output at a timing at which the integrated value is minimized.
[0015]
As described in the third aspect of the present invention, the integration described above includes the first integration for integrating the period of the repetitive signal, and the integration for the length of the plurality of repetitive signals from the integration value. The second integration can be performed. In this case, the synchronization signal can be output at a timing at which the integration value of the second integration becomes a minimum equal to or less than a predetermined threshold.
[0016]
Further, the integration described above may be equal to or longer than the length of the plurality of repeated signals, and conversely, as in the invention according to claim 4, is performed in a section shorter than the length of the plurality of repeated signals. You may do it. In this case, the synchronization signal can be obtained at an early timing.
[0017]
The invention according to claim 5 is a receiving device that receives a packet signal having a plurality of known repeated signals added to the head, and the receiving device generates a synchronization signal from the received signal. Department,
The synchronization signal generator is
Means (211 to 217) for taking a difference between two received signals different by a predetermined period of the repetitive signal and obtaining an absolute value thereof;
Means (218, 219) for integrating the absolute value;
And a means (220) for outputting the synchronization signal at a timing at which the integrated value is minimized.
[0018]
In a sixth aspect of the present invention, the absolute value is obtained by taking the difference between two received signals that differ by a predetermined period of the repetitive signal for a packet signal having a known repetitive signal added a plurality of times at the beginning. Means (211 to 217);
Means (218, 219) for integrating the absolute value;
It is characterized by a computer-readable recording medium recording a program for causing a computer to execute means (220) for outputting a synchronization signal at a timing at which the integrated value is minimized.
[0019]
In the fifth and sixth aspects of the invention, means (211 to 217) for obtaining a difference between two received signals that differ by a predetermined period of the repetitive signal and obtaining an absolute value thereof is an I component of the received signal. For the Q component and Q component, a difference between two signals that differ by a predetermined period of the repetitive signal is obtained to obtain an absolute value, and further, the respective absolute values are added. More specifically, means (211 and 212) for taking the difference between two signals that differ by a predetermined period of the repetitive signal with respect to the I component of the received signal, and means (213) for converting the difference into an absolute value The means (214, 215) for taking a difference between two signals that differ by a predetermined period of the repetitive signal with respect to the Q component of the received signal, a means (216) for converting the difference into an absolute value, It can be configured as a means for adding (217).
[0020]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. This embodiment is applied to a communication system using an Orthogonal Frequency Division Multiplexing (OFDM) system. FIG. 1 shows a conceptual diagram of the communication system.
[0022]
A transmitter (TX) as a transmitting apparatus transmits a preamble (P) composed of known N repetition signals and a packet signal composed of data in a burst manner. A receiver (RX) as a receiving device receives the transmitted signal, generates a synchronization signal from the preamble repeat signal, and demodulates the transmitted data.
[0023]
FIG. 2 shows an image configuration of a transmission signal (I component signal) and a packet. The packet has a configuration conforming to the IEEE802.11a specification, and includes a preamble composed of a known N (= 10) repetition signal (a signal repeated every 16 samples) and data as a transmission information signal.
[0024]
FIG. 3A shows the configuration of the baseband unit in the transmitter (TX). Data to be transmitted is encoded by the encoding unit 11, converted to a parallel signal by the serial / parallel conversion unit (S / P conversion unit) 12, subcarrier modulated (for example, QPSK) by the modulation unit 13, and IFFT (inversely) A fast Fourier transform unit 14 performs IFFT processing, a parallel / serial conversion unit (P / S conversion unit) 15 converts the signal into a serial signal, and a guard interval (GI) adding unit 15 adds a guard interval.
[0025]
FIG. 3B shows the configuration of the baseband unit in the receiver (RX). The received signal is input to a time / frequency synchronization unit 21 that performs time and frequency synchronization processing, and a synchronization signal is output from the time / frequency synchronization unit 21. Each part (each part 22-28 etc. demonstrated below) in a receiver (RX) performs each process based on the synchronizing signal.
[0026]
Specifically, the received signal is input to the GI removal unit 22 to remove the guard interval, converted into a parallel signal by the S / P conversion unit 23, and subjected to FFT processing in the FFT (Fast Fourier Transform) unit 24, and equalized. An equalization process is performed in the unit 25, a subcarrier demodulation process is performed in the demodulation unit 26, a serial signal is converted in the P / S conversion unit 27, and a decoding process is performed in the decoding unit 28.
[0027]
The transmitter (TX) and the receiver (RX) described above are provided in the mobile terminal and the base station, respectively, and communicate with each other between the terminal and the terminal and between the terminal and the base station.
[0028]
In this embodiment, the time & frequency synchronization unit 21 of the receiver described above includes a synchronization signal generation unit that generates a time synchronization signal. This synchronization signal generator is configured as shown in FIG. The synchronization signal generation unit receives the I component and Q component signals of the reception signal, which is obtained by converting the reception signal represented by a complex number into an I component and a Q component signal having orthogonal phases by a conversion unit (not shown). Is done.
[0029]
The I component of the received signal is delayed in the delay unit 211 by the period (16T) of each repeated signal of the preamble. Then, in a subtracting unit (adding unit for subtracting one signal and adding) 212, a difference between a signal obtained by delaying the I component of the received signal by 16T and a signal not delayed is obtained. The signal indicating this difference is converted into an absolute value signal in the absolute value portion 213, and a signal indicating the magnitude of the difference between the signal obtained by delaying the I component of the received signal by 16T and the signal not delayed from the absolute value portion 213. Is output.
[0030]
Similarly, the Q component of the received signal is subjected to signal processing by the delay unit 214, the subtraction unit 215, and the absolute value unit 216. Then, a signal indicating the magnitude of the difference between the signal obtained by delaying the Q component of the received signal by 16T and the signal not delayed is output from the absolute value unit 216.
[0031]
The signals output from the absolute value units 213 and 216 are added by the adder 217 and integrated by the correlation interval integrator 218. The correlation interval integrator 218 performs integration for the correlation interval (16T).
[0032]
Here, when the received signal is data, for each of the I component and Q component of the received signal, the signal delayed by 16T and the signal not delayed are often greatly different. A value obtained by adding the output values by the adding unit 217 and integrating by the correlation interval integrating unit 218 is a large value.
[0033]
If the received signal is a repetitive signal in the preamble, the signal delayed by 16T and the signal not delayed are the same for each of the I component and Q component of the received signal, and the difference between the two signals is small. For this reason, a value obtained by adding the values output from the absolute value units 213 and 216 by the adding unit 217 and integrating by the correlation interval integrating unit 218 becomes a small value.
[0034]
FIG. 6A shows a graph of the waveform of the signal obtained by the integration of the correlation interval integrator 218 (the waveform at point a in FIG. 4). This graph is a simulation result when there is no noise and multipath fading. The horizontal axis indicates the number of samples (corresponding to the time axis), and the vertical axis indicates the signal level. In the graph, a portion that is extremely small compared to other signal levels (that is, a peak occurs on the lower side) is a preamble section. FIG. 6B shows an enlarged view near one of the peaks. In the preamble section, the output of the correlation section integrator 218 is almost zero.
[0035]
For comparison, the same simulation result of the waveform of the normalized correlation value (the waveform at the point b in FIG. 11) obtained by the configuration shown in FIG. 11 is associated with FIGS. 6 (a) and 6 (b). 6 (c) and 6 (d). According to the configuration shown in FIG. 11, the normalized correlation value output has a peak on the upper side in each preamble section.
[0036]
FIG. 7 shows the simulation result when the CNR (the ratio of carrier signal power to noise power) is 20 dB and the model C multipath fading characteristics defined by ETSI BRAN are given. 7A to 7D correspond to FIGS. 6A to 6D. As can be seen from FIG. 7, according to this embodiment, even if there is multipath fading, a clear peak on the lower side for each preamble section in the signal obtained by the integration of the correlation section integrator 218. Has occurred.
[0037]
The packets used in the simulations shown in FIGS. 6 and 7 have a configuration conforming to the IEEE802.11a specification, and OFDM is used for the transmission method and QPSK is used for the subcarrier modulation. Also, the preamble length is 320 samples (of which 160 samples are used for the time synchronization described above), and the amount of information for one packet is 768 bytes.
[0038]
The signal obtained by the integration of the correlation interval integrator 218 is input to the preamble interval integrator 219 and integrated for the preamble interval (that is, 16 × 10T). An integral value is output from the preamble interval integrator 219 every T.
[0039]
8A and 8B show an enlarged waveform near one peak in the output of the correlation interval integrator 218 and a simulation result of the output waveform of the preamble interval integrator 219 corresponding thereto. Since the preamble section integration unit 219 performs integration in the 160T section, the preamble section integration starts after the value when the output of the correlation section integration section 218 becomes extremely low starts to affect the integration of the preamble section integration section 219. The integrated value of the part 219 starts to decrease. Further, the output of the preamble interval integrator 219 starts to rise after the value when the output of the correlation interval integrator 218 starts to affect the integration of the preamble interval integrator 219. Therefore, a time-synchronized synchronization signal can be obtained by finding a timing at which the integral value of the preamble interval integrator 219 is minimized.
[0040]
The minimum value detector 220 detects a timing at which the integral value output from the preamble interval integrator 219 is minimum, and outputs a synchronization signal.
[0041]
FIG. 5 shows an example of a specific configuration of the minimum value detection unit 220. The minimum value detection unit 220 includes a control unit 2201, a delay unit 2202, a comparison unit 2203, and a determination unit 2204.
[0042]
The control unit 2201 compares the integration value output from the correlation interval integration unit 218 with a predetermined threshold value, and monitors whether the output of the correlation interval integration unit 218 has become extremely low, and the correlation interval integration unit 218. The outputs of the delay unit 2202, the comparison unit 2203, and the discrimination unit 2204 are stopped while the output of the correlation interval integration unit 218 becomes extremely low, while the output of the delay unit 2202, the comparison unit 2203, and the discrimination unit 2204 is extremely low. Enable signals to be operated.
[0043]
By starting this operation, the value obtained by delaying the integral value output from the preamble interval integrating unit 219 by T by the delay unit 2202 is compared with the value not delayed by the comparing unit 2203, and the comparison result is output to the determining unit 2204. The As shown in FIG. 8B, when the output of the preamble interval integrator 219 is reduced, the output of the comparator 2203 becomes a signal indicating a reduced state (for example, a minus signal), and the preamble interval integrator 219 When the output is rising, the output of the comparison unit 2203 is a signal indicating a rising state (for example, a + signal).
[0044]
Accordingly, the determination unit 2204 determines the timing at which the output of the comparison unit 2203 is inverted from the signal indicating the decrease state to the signal indicating the increase state (timing immediately before or after the inversion), thereby outputting the synchronization signal.
[0045]
In addition to the configuration described above, the minimum value detection unit 220 stores the output of the preamble interval integration unit 219 in M memories, and stores the minimum value below the threshold from the M stored values. A value may be specified and a synchronization signal corresponding to the storage position of the stored value may be output. However, in this case, the output of the synchronization signal is delayed in timing by the amount that M outputs of the preamble interval integrator 219 are stored in the memory. Therefore, in the case of this embodiment, the reception signal input to the GI removal unit 22 shown in FIG. 3 is delayed by a time corresponding to the M memories, and the synchronization signal is output within the delay time. To.
[0046]
In the above-described embodiment, the integration interval of the preamble interval integration unit 219 is 160T, which is a preamble interval, but it may be longer than that, or conversely, may be a shorter interval. In the case of a short interval, the synchronization signal is output earlier in terms of timing. However, some systems require an early synchronization signal, which is preferable in such a system.
[0047]
In the above-described embodiment, the correlation interval integration unit 218 and the preamble interval integration unit 219 are provided. However, the correlation interval integration unit 218 may be eliminated and the preamble interval integration unit 219 alone may be used. In this case, the minimum value detection unit 220 constantly monitors the output of the preamble interval integration unit 219, and detects the timing at which the minimum value is below a predetermined threshold from the integration value. For example, as shown in FIG. 9, when the preamble is composed of two repetitive signals (N sample period signals), as shown in FIG. 10, the integration of one repetitive signal section (NT) is performed as a correlation section. This is performed in the integration unit 218, and based on the integration result, the minimum value detection unit 220 detects the minimum value and outputs a synchronization signal. In this case, the synchronization signal is output at an early timing before the completion of the print section.
[0048]
Further, in the above-described embodiment, the time-synchronized synchronization signal is generated using both the I component and the Q component of the received signal, but only one of the I component and the Q component is included in the preamble repetition signal. In the case of a system that uses, a synchronization signal may be generated using a component corresponding to the system.
[0049]
In the above-described embodiment, the difference between two consecutive signals is shown for each of the I component and the Q component of the received signal. However, two signals that take a difference even if they are not consecutive are repeated. It only needs to be different by a predetermined period of the signal.
[0050]
Further, in the various embodiments described above, the configuration of each unit of the receiver can be configured by software in addition to the configuration of hardware logic. For example, with respect to the block-like hardware configuration such as each of the units 21 to 28 shown in FIG. 3B, the computer program (program product) for configuring the computer and causing the computer to execute is stored in a memory serving as a recording medium. The computer program can be stored and transferred from the memory to a hardware configuration such as each of the units 21 to 28 when the power is turned on to operate them. In this case, the computer program may be distributed from a recording medium provided in the server by communication via a network. Moreover, the memory which memorize | stores a computer program may be separately provided with respect to each part 21-28 grade | etc., Besides one provided with respect to the whole each part 21-28 grade | etc.,.
[0051]
Note that the present invention is not limited to the one applied to the communication system using the OFDM method, and other methods are used as long as packet communication is performed in bursts and a repetitive signal is used for the preamble of the packet signal. It can also be applied to a communication system.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a conceptual diagram of a communication system using an OFDM scheme according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining a transmission waveform in the communication system shown in FIG. 1;
FIG. 3 is a diagram illustrating a configuration of a baseband unit in the receiver (TX) and the receiver (RX) in FIG. 1;
4 is a diagram showing a configuration of a synchronization signal generation unit included in the time / frequency synchronization unit 21 in FIG. 3;
5 is a diagram showing a specific configuration of a minimum value detection unit 220 in FIG.
FIG. 6 is a diagram showing a simulation result when there is no noise and multipath fading.
FIG. 7 is a diagram illustrating a simulation result when a multipath fading characteristic of Model C is given.
8 is a diagram illustrating a simulation result of an output waveform of a correlation interval integrator 218 and an output waveform of a preamble interval integrator 219. FIG.
FIG. 9 is a diagram showing a packet configuration when a preamble is composed of two repetitive signals.
10 is a diagram illustrating a configuration of a synchronization signal generation unit applied in the case of the packet configuration illustrated in FIG. 9;
FIG. 11 is a diagram illustrating a configuration of a synchronization signal generation unit examined by the present inventors.
12 is a diagram showing a configuration of the matched filter 102 in FIG.
13 is a diagram showing a configuration of a power detection unit 104 in FIG.
[Explanation of symbols]
211, 214 ... delay unit, 212, 215 ... subtraction unit,
213, 216 ... absolute value part, 217 ... addition part, 218 ... correlation interval integration part,
219 ... Preamble interval integration unit, 220 ... Minimum value detection unit,
2201 ... Control unit, 2202 ... Delay unit, 2203 ... Comparison unit,
2204: A discrimination unit.

Claims (6)

In a synchronization signal generating method for receiving a packet signal with a known repeated signal added at the beginning and generating a synchronization signal from the received signal,
A method for generating a synchronization signal, comprising: taking a difference between two reception signals that differ by a predetermined period of the repetitive signal, integrating the absolute value thereof, and outputting the synchronization signal at a timing at which the integration value is minimized.   In a synchronization signal generation method for receiving a packet signal with a plurality of known repetition signals added to the beginning and generating a synchronization signal from the received signal, the I component and the Q component of the reception signal are respectively The absolute value is obtained by taking the difference between two signals that differ by a predetermined period, adding the respective absolute values, integrating the added values, and outputting the synchronization signal at a timing at which the integrated value is minimized. A method for generating a synchronization signal.   The integration includes a first integration that performs integration for a period of the repetitive signal, and a second integration that performs integration for the length of the repetitive signal for a plurality of times from the integration value. 3. The synchronization signal generation method according to claim 1, wherein the synchronization signal is output at a timing at which an integral value of the integration becomes a minimum equal to or less than a predetermined threshold.   The synchronization signal generation method according to claim 1, wherein the integration is performed in a section shorter than a length of the plurality of repeated signals. A reception device that receives a packet signal with a plurality of known repetition signals added to the head, the reception device includes a synchronization signal generation unit that generates a synchronization signal from the reception signal,
The synchronization signal generator is
Means (211 to 217) for taking a difference between two received signals different by a predetermined period of the repetitive signal and obtaining an absolute value thereof;
Means (218, 219) for integrating the absolute value;
And a means (220) for outputting the synchronization signal at a timing at which the integrated value is minimized. Means (211 to 217) for obtaining the absolute value of a difference between two received signals different from each other by a predetermined period of the repetitive signal with respect to a packet signal to which a plurality of known repetitive signals are added at the beginning;
Means (218, 219) for integrating the absolute value;
A computer-readable recording medium recording a program for causing a computer to execute means (220) for outputting a synchronization signal at a timing at which the integrated value is minimized.

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