JP2000165341A - Ofdm demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a demodulation characteristics more excellent than that of delay detection by an OFDM demodulation circuit while keeping a high transmission efficiency equal to that in the case of the delay detection in the OFDM demodulation circuit. SOLUTION: The OFDM demodulation circuit is provided with an initial estimate AFC circuit 10 that detects and corrects an initial frequency error from a preamble, a transmission line estimate circuit 20 that estimates an impulse response of a transmission line from the preamble, a residual frequency correction circuit 30 that corrects a received signal with a residual frequency error signal after the end of the preamble signal, an FFT circuit that applies S/P conversion to the received signal receiving residual frequency correction and then applies FFT to the converted signal, an initial phase memory circuit 50 that stores an initial phase of each subcarrier, a phase detection circuit 60 that detects the received signal outputted from the FFT circuit 40 at the initial phase of the initial phase memory circuit 50 for each subcarrier, and a residual frequency error detection circuit 70 that detects the residual frequency error from the phase detection signal and obtains the residual frequency error signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to orthogonal frequency division multiplexing (OFDM) used in digital radio communication.
O to process frequency division multiplexing signals
The present invention relates to an FDM demodulation circuit, and more particularly, to detection of a frequency error and detection of an initial phase.

[0002]

2. Description of the Related Art As prior art of this type of OFDM demodulation circuit, for example, the following Documents 1, 2 and 3 are known. Reference 1: Onizawa, Mizoguchi, Kumagaya, Takanashi, Morikura, "High-speed wireless L
A Study on Synchronous System of OFDM Modulation System for AN ", IEICE Technical Report, RCS97-210.

Reference 2: TMSchmid and DCCox, “Low-O
verhead, Low-Complexity [Burst] Synchronization for
OFDM ”, ICC'96, pp. 1301-1306. Reference 3: V. Mignone and A. Morello,“ CD3-OFDM: A Nove
l Demodulation Scheme for Fixed and Mobile Receive
rs ”, IEEE Trans. Commun., pp.1144-1151, vol.44, No.
9, Sept (1996).

[0004] Either synchronous detection or delay detection can be applied to demodulation of an OFDM signal. With respect to demodulation characteristics, using synchronous detection is superior to differential detection. However, the differential detection needs to detect only the carrier frequency error, whereas the synchronous detection must also detect the carrier initial phase. Therefore, there is a problem that transmission efficiency is deteriorated when synchronous detection is used.

When transmitting an OFDM signal in a packet format, a burst format as shown in FIG. 14 or FIG. 15 is conventionally used. In the burst format shown in FIG. 14, the preamble PRE having the same content repeatedly appears at the head of the packet (left end in FIG. 14). After the preamble PRE, an OFDM symbol composed of a guard interval GI and data DATA appears repeatedly.

[0006] As shown in the above-mentioned document 1, an error in the carrier frequency of a received OFDM signal can be detected by referring to the same preamble PRE that appears repeatedly. The circuit for detecting and correcting the carrier frequency error is A
It is an FC (automatic frequency control) circuit. An AFC circuit that detects a carrier frequency error from the same preamble PRE that repeatedly appears using the burst format signal shown in FIG. 14 is advantageous in terms of transmission efficiency because the frequency error estimation time is short.

FIG. 11 shows a conventional OFDM demodulation circuit. In FIG. 11, signals indicated by thick lines represent parallel signals corresponding to the number of subcarriers. In the OFDM demodulation circuit of FIG. 11, the received signal is subjected to fast Fourier transform by an FFT (fast Fourier transform) circuit 201 after a frequency error is corrected by an AFC circuit 200. An OFDM signal is a signal in which a plurality of carriers (carriers) having different frequencies are multiplexed in the time domain, and the components of the plurality of carriers are converted to the frequency domain by Fourier transform and appear as parallel signals. The parallel signal output from the FFT circuit 201 is subjected to delay detection by the delay detection circuit 202 for each subcarrier.

The AFC circuit 200 is configured as shown in FIG. In the AFC circuit 200 of FIG. 12, the phase rotation angle detection circuit 211 detects the phase rotation angle by performing complex conjugate multiplication of the received signal and a signal obtained by delaying the received signal by 1 OFDM. Here, as shown in FIG.
It is assumed that the same preamble PRE is transmitted continuously for OFDM symbols.

The averaging circuit 212 includes a phase rotation angle detection circuit 2
11 calculates the average of the detected phase rotation angles for a certain period of time.
Thereby, the influence of the noise component is removed. The frequency error detection circuit 213 calculates the averaged phase rotation angle by 1 OF
Divide by the period of the DM symbol. Frequency error detection circuit 2
At the output of 13, a phase rotation angle per one cycle of a predetermined clock signal is obtained. The integrating circuit 214 generates a corrected phase signal by integrating the phase rotation angle output from the frequency error detection circuit 213.

The received signal (input signal) is delayed by the received signal delay circuit 215 until a corrected phase signal is generated. The reception signal delayed by the reception signal delay circuit 215 is corrected by the correction phase signal in the frequency correction circuit 216 (see References 1 and 2). A conventional OFDM demodulation circuit using synchronous detection uses, for example, a burst format OFDM signal shown in FIG. Also, O
The FDM demodulation circuit is configured as shown in FIG.

In FIG. 15, a preamble PRE is a known signal and is used for detecting a carrier initial phase. After the preamble PRE, an OFDM symbol composed of a guard interval GI and data DATA appears repeatedly (see Document 3). When synchronous detection is performed using a burst format as shown in FIG. 15, no pilot signal is required, and the detection time of the initial phase is short, which is advantageous.

On the transmitting side, for example, the number of subcarriers is 687
5, 16 QAM modulation, convolutional coding (coding rate = 1 /
2, 3/4, 7/8: constraint length = 7), and transmitted under interleaving conditions. In addition, in order to complete demodulation within one OFDM symbol, in convolutional coding, 10
A tail bit having a length of 6 bits is added to each FDM symbol.

[0013] In the OFDM demodulation circuit shown in FIG. 13, the received signal (OFDM signal) is Fourier-transformed by the FFT circuit 201, and then input to the phase detection circuit 220 and the delay circuit 229. A received signal separated for each subcarrier is obtained as an output of the FFT circuit 201 by the Fourier transform. The phase detection circuit 220 performs complex multiplication of the received signal and the phase signal for each subcarrier to detect the received signal. The detected reception signal is converted to a serial signal by a P / S (parallel-serial conversion) circuit 221, and then passes through a deinterleave circuit 223 to make a soft decision Viterbi (FEC-
DEC) circuit 224. Soft decision Viterbi circuit 2
A demodulated output signal is obtained at 24 outputs.

In order to generate a pseudo transmission signal used for estimating the transmission path, the demodulated output signal obtained at the output of the soft-decision Viterbi circuit 224 is convolved (FEC) similarly to the transmitter side.
-COD) circuit 225, interleave circuit 226 and modulation (MOD) circuit 227, and through S / P (serial / parallel conversion) circuit 228, frequency domain transmission path estimation circuit 23
0 is applied.

The frequency-domain transmission path estimating circuit 230 divides the received signal by the transmitted signal for each subcarrier. Thereby, the phase of the carrier for each subcarrier is detected. A noise component is removed from the detected phase by a frequency domain filter circuit 232, and the detected phase is converted into a phase signal by a phase detection circuit 220.
Is applied to In order to detect the initial phase of the carrier at the head of the packet,
0 divides the received signal by a known preamble for each subcarrier. The known preamble is stored in the initial phase memory 231.
Is held in.

The phase signal applied to the phase detection circuit 220 has an error due to the influence of noise, but an accurate demodulated signal can be obtained by applying strong error correction and interleaving.

[0017]

The AFC circuit used in the conventional OFDM demodulation circuit can detect the frequency error in a short time. However, since the AFC circuit has an open-loop configuration, the corrected signal has a residual frequency error. Exists. This residual frequency error is not a problem in the case of differential detection,
When the synchronous detection is performed, it causes a characteristic deterioration.

In order to correct the residual frequency error caused by the AFC circuit, there is known a method of performing tracking even during the section of the data (DATA) of the OFDM signal. However, since it is necessary to insert a pilot signal in a data section for tracking, there is a problem that transmission efficiency is deteriorated by the pilot signal. Further, when a conventional OFDM demodulation circuit for performing synchronous detection is applied to an OFDM signal having about 48 subcarriers, there is a problem that the transmission efficiency is greatly deteriorated by tail bits provided for each OFDM symbol.

For example, 8PSK (coding rate = ２ / 3,
In the case of the constraint length = 7), the deterioration is about 10%. 1 OFD
If the tail bit is not transmitted for every M symbols, this deterioration is eliminated. However, if the tail bits are not transmitted, the preamble requires several OFDM symbols, which causes a problem that the transmission efficiency is deteriorated. The present invention relates to OF
An object of the present invention is to obtain better demodulation characteristics in a DM demodulation circuit than in the case of performing delay detection, while maintaining the same high transmission efficiency as in the case of performing delay detection.

[0020]

According to the present invention, an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period is input as a received signal, and a frequency error of the orthogonal frequency multiplexed signal and an initial frequency error are calculated. An OFDM demodulation circuit for detecting a phase, detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting an received signal with the detected initial frequency error; A transmission path estimation circuit connected to an estimation AFC circuit for estimating an impulse response of a transmission path from the preamble signal at the head of the packet; and a reception signal output by the transmission path estimation circuit after the end of the preamble signal at the beginning of the packet. A residual frequency correction circuit for correcting with a frequency error signal, and the residual frequency correction A fast Fourier transform circuit for performing a fast Fourier transform after serial-to-parallel conversion of the received signal whose path has been corrected, and a fast Fourier transform of the impulse response estimated at the beginning of a packet, which is connected to an output of the fast Fourier transform circuit. An initial phase memory circuit that stores an initial phase signal for each subcarrier of the orthogonal frequency multiplexed signal obtained by using the initial phase signal held in the initial phase memory circuit, and a reception signal output by the fast Fourier transform circuit. A phase detection circuit that detects each subcarrier of the received signal, and detects a residual frequency error based on a signal output from the phase detection circuit, and provides the detection result to the residual frequency correction circuit as the residual frequency error signal. And a residual frequency error detection circuit.

The OFDM demodulation circuit according to the first aspect is shown in FIG.
It is assumed that an OFDM signal in which the same known preamble signal (PRE) repeatedly appears at the head of a packet as shown in FIG. The OFDM demodulation circuit performs initial frequency error detection and initial phase detection using a preamble. Then, the residual frequency error is tracked using the data signal (DATA) to correct the residual frequency error. Therefore, synchronous detection can be performed, and good demodulation characteristics can be obtained.

Further, since the data signal is used for tracking the residual frequency error, the preamble PRE provided at the head of the packet is sufficient only in the section of 2 OFDM symbols. That is, since the number of bits added to the packet for synchronization is small, the transmission efficiency is almost the same as that in the case of performing the delay detection. Claim 2 provides an OFDM demodulation circuit for inputting, as a received signal, an orthogonal frequency multiplex signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period, and detecting a frequency error and an initial phase of the orthogonal frequency multiplex signal. An initial estimation AFC circuit for detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting the received signal with the detected initial frequency error; A transmission path estimating circuit for estimating an impulse response of a transmission path from the preamble signal of
A fast Fourier transform circuit that performs fast Fourier transform after serial-to-parallel conversion of the received signal output by the transmission path estimating circuit, and a received signal that is output by the fast Fourier transform circuit after the end of the preamble signal at the head of the packet. A residual frequency correction circuit for correcting with a residual frequency error signal for each carrier, and a sub-carrier of an orthogonal frequency multiplexed signal which is connected to an output of the residual frequency correction circuit and is obtained by performing a fast Fourier transform on the impulse response estimated at the head of a packet. An initial phase memory circuit that stores an initial phase signal for each carrier; and a reception signal that is output by the residual frequency correction circuit is detected for each subcarrier of the reception signal using the initial phase signal held in the initial phase memory circuit. And a residual frequency error based on a signal output from the phase detection circuit. Detected, characterized in that a residual frequency error detection circuit for applying to the residual frequency correction circuit the detection result as the residual frequency error signal.

The OFDM demodulation circuit according to claim 2 has a structure shown in FIG.
It is assumed that an OFDM signal in which the same known preamble signal (PRE) repeatedly appears at the head of a packet as shown in FIG. The OFDM demodulation circuit performs initial frequency error detection and initial phase detection using a preamble. Then, the residual frequency error is tracked using the data signal (DATA) to correct the residual frequency error. Therefore, synchronous detection can be performed, and good demodulation characteristics can be obtained.

Since the data signal is used for tracking the residual frequency error, the preamble PRE provided at the head of the packet is sufficient only for the section of 2 OFDM symbols. That is, since the number of bits added to the packet for synchronization is small, the transmission efficiency is almost the same as that in the case of performing the delay detection.

A third aspect of the present invention is for OFDM for inputting an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period as a received signal and detecting a frequency error and an initial phase of the orthogonal frequency multiplexed signal. A demodulation circuit that detects an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and corrects the received signal with the detected initial frequency error; A transmission line estimating circuit for inputting a received signal, and estimating an impulse response of a transmission line of a selected number of taps based on the preamble signal at the head of the packet; and an output of the initial estimation AFC circuit, Delay to estimate the delay profile of the received signal in the transmission path Estimation circuit, connected to the transmission path delay estimation circuit, and tap selection for determining the number of taps used for transmission path estimation of the transmission path estimation circuit based on the delay profile estimated by the transmission path delay estimation circuit A delay circuit for providing a signal obtained by delaying the reception signal output from the initial estimation AFC circuit by the processing time of the transmission path delay estimation circuit and the tap selection circuit to the transmission path estimation circuit; After completion of the signal, a residual frequency correction circuit for correcting the received signal output from the transmission path estimating circuit with a residual frequency error signal, and a fast Fourier transform after the received signal corrected by the residual frequency correction circuit is subjected to serial-parallel conversion. A fast Fourier transform circuit for transforming, and an input connected to an output of the fast Fourier transform circuit and estimated at the beginning of a packet. An initial phase memory circuit for storing an initial phase signal for each subcarrier of an orthogonal frequency multiplexed signal obtained by performing a fast Fourier transform on a Luth response, and a received signal output by the fast Fourier transform circuit are held in the initial phase memory circuit. A phase detection circuit that detects each subcarrier of the received signal using the initial phase signal, and detects a residual frequency error based on a signal output from the phase detection circuit, and uses the detection result as the residual frequency error signal. And a residual frequency error detection circuit provided to the residual frequency correction circuit.

The OFDM demodulation circuit according to the third aspect is shown in FIG.
It is assumed that an OFDM signal in which the same known preamble signal (PRE) repeatedly appears at the head of a packet as shown in FIG. The OFDM demodulation circuit performs initial frequency error detection and initial phase detection using a preamble. Then, the residual frequency error is tracked using the data signal (DATA) to correct the residual frequency error. Therefore, synchronous detection can be performed, and good demodulation characteristics can be obtained.

Since the data signal is used for tracking the residual frequency error, the preamble PRE provided at the head of the packet is sufficient only for the section of 2 OFDM symbols. That is, since the number of bits added to the packet for synchronization is small, the transmission efficiency is almost the same as that in the case of performing the delay detection. A fourth aspect of the present invention relates to an OFDM demodulation circuit for inputting, as a reception signal, an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition period, and detecting a frequency error and an initial phase of the orthogonal frequency multiplexed signal. An initial estimation AFC circuit for detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting the received signal with the detected initial frequency error; and a reception signal corrected by the initial estimation AFC circuit. And a transmission path estimating circuit for estimating an impulse response of a transmission path of a selected number of taps based on the preamble signal at the beginning of a packet, and a transmission signal estimating circuit configured to be connected to an output of the initial estimation AFC circuit. Transmission path delay estimating circuit for estimating delay profile in transmission path A tap selection circuit connected to the transmission path delay estimation circuit, the tap selection circuit determining the number of taps used for transmission path estimation of the transmission path estimation circuit based on the delay profile estimated by the transmission path delay estimation circuit; A delay circuit for providing a signal obtained by delaying the reception signal output by the initial estimation AFC circuit by the processing time of the transmission path delay estimation circuit and the tap selection circuit to the transmission path estimation circuit, and a reception circuit output by the transmission path estimation circuit A fast Fourier transform circuit that performs a fast Fourier transform after serial-to-parallel conversion of the signal, and a received frequency signal output by the fast Fourier transform circuit after the end of the preamble signal at the beginning of a packet is corrected by a residual frequency error signal for each subcarrier. And a residual frequency correction circuit connected to the output of the residual frequency correction circuit, An initial phase memory circuit that stores an initial phase signal for each subcarrier of an orthogonal frequency multiplexed signal obtained by performing a fast Fourier transform of a Luth response, and a received signal output by the residual frequency correction circuit is stored in the initial phase memory circuit. A phase detection circuit that detects each subcarrier of the received signal using the initial phase signal, and detects a residual frequency error based on a signal output from the phase detection circuit, and uses the detection result as the residual frequency error signal. And a residual frequency error detection circuit provided to the residual frequency correction circuit.

The OFDM demodulation circuit according to the fourth aspect is shown in FIG.
It is assumed that an OFDM signal in which the same known preamble signal (PRE) repeatedly appears at the head of a packet as shown in FIG. The OFDM demodulation circuit performs initial frequency error detection and initial phase detection using a preamble. Then, the residual frequency error is tracked using the data signal (DATA) to correct the residual frequency error. Therefore, synchronous detection can be performed, and good demodulation characteristics can be obtained.

Since the data signal is used for tracking the residual frequency error, the preamble PRE provided at the head of the packet is sufficient only for the section of 2 OFDM symbols. That is, since the number of bits added to the packet for synchronization is small, the transmission efficiency is almost the same as that in the case of performing the delay detection. According to a fifth aspect of the present invention, in the OFDM demodulation circuit according to any one of the first, second, third, and fourth aspects, the initial estimation AFC circuit is configured to transmit a received signal to one OFDM.
A delay circuit that delays by a symbol period, a phase rotation angle detection circuit that detects a phase rotation angle by conjugate complex multiplication of a reception signal and a reception signal delayed by the delay circuit, and the phase rotation angle detection circuit outputs An averaging circuit that calculates an average value of the phase rotation angle over a predetermined time, an initial frequency error detection circuit that calculates an initial frequency error from the phase rotation angle averaged by the averaging circuit, and an output from the initial frequency error detection circuit An integration circuit that integrates an initial frequency error and outputs it as an initial frequency error signal; a reception signal delay circuit that delays the reception signal until the initial frequency error signal is output; and a reception circuit that the reception signal delay circuit outputs And an initial frequency correction circuit for correcting the signal with an initial frequency error signal output from the integrating circuit.

The delay circuit delays the received signal by a period of one OFDM symbol. A reception signal and a reception signal delayed by the delay circuit are applied to an input of the phase rotation angle detection circuit. Therefore, the phase rotation angle detection circuits are mutually 1 OF
It is possible to simultaneously refer to two signals shifted in time by the period of the DM symbol. The length of one preamble is 1 OFDM
Assuming the same as the symbol length, the two signals match if there is no frequency error. If there is a frequency error, a difference occurs between the two input signals according to the frequency error.

Since the OFDM signal is a complex signal, the phase rotation angle detection circuit detects the phase rotation angle by conjugate complex multiplication of two input signals. The averaging circuit calculates an average value of the phase rotation angle output from the phase rotation angle detection circuit over a predetermined time. The initial frequency error detection circuit calculates an initial frequency error from the phase rotation angle averaged by the averaging circuit. The integrating circuit integrates the initial frequency error output from the initial frequency error detecting circuit and outputs the result as an initial frequency error signal.

The reception signal delay circuit delays the reception signal until the initial frequency error signal is output. The initial frequency correction circuit corrects the reception signal output by the reception signal delay circuit with an initial frequency error signal output by the integration circuit. According to a sixth aspect of the present invention, in the OFDM demodulation circuit according to any one of the first, second, third, and fourth aspects,
RL is used to estimate the impulse response of the transmission path estimation circuit.
A ROM that uses the S algorithm and holds the result of previously calculating a Kalman gain vector for a known preamble is provided. Further, the number of taps of the impulse response obtained by the RLS algorithm is set to the maximum delay time of the delayed wave, and the maximum delay of the delayed wave is set. The impulse response after time is set to 0.

By using the RLS algorithm,
Impulse response can be estimated in a short time. R
The Kalman gain vector used in the LS algorithm is determined according to the preamble. Since known data is used as the preamble in the present invention, the corresponding Kalman gain vector can be calculated in advance and stored in a ROM (read only memory). By using the result calculated in advance, the amount of calculation of the RLS algorithm is reduced, and the time required for executing the algorithm is reduced.

Further, by setting the number of taps of the impulse response obtained by the RLS algorithm to the maximum delay time of the delay wave and setting the impulse response after the maximum delay time of the delay wave to 0, the characteristics of the transmission path estimation are improved and the calculation is performed. The volume is also reduced. Claim 7 is Claim 1, Claim 2,
5. The OFDM demodulation circuit according to claim 3, wherein the residual frequency error detection circuit is a delay circuit for delaying an input signal for each subcarrier, and an input signal and an input signal delayed by the delay circuit. A difference vector detection circuit that detects a difference vector by conjugate complex multiplication with a signal, a modulation component removal circuit that removes a modulation component from a signal output from the difference vector detection circuit, and an output of the modulation component removal circuit for each subcarrier. A vector addition circuit for adding a signal to remove a noise component included in the output signal; and a residual frequency error per one clock based on the phase information after converting an output signal of the vector addition circuit into phase information. An arc tangent circuit for calculating a residual frequency error signal output by integrating the residual frequency error output from the arc tangent circuit Characterized by being constituted by the that integration circuit.

The delay circuit delays the input signal for each subcarrier. The difference vector detection circuit detects a difference vector by conjugate complex multiplication of the input signal and the input signal delayed by the delay circuit. The modulation component removal circuit
The modulation component is removed from the signal output from the difference vector detection circuit. The vector addition circuit removes a noise component included in the output signal by vector-adding the output signal of the modulation component removal circuit for each subcarrier. The arctangent circuit converts an output signal of the vector addition circuit into phase information, and then calculates a residual frequency error per clock based on the phase information. The integrating circuit integrates the residual frequency error output from the arc tangent circuit and outputs a residual frequency error signal.

According to an eighth aspect, in the OFDM demodulation circuit according to any one of the first, second, third, and fourth aspects, the residual frequency error detection circuit delays an input signal for each subcarrier. A delay circuit, a difference vector detection circuit for detecting a difference vector by conjugate complex multiplication of the input signal and the signal delayed by the delay circuit, and a modulation component for removing a modulation component from the difference vector output from the difference vector detection circuit A removal circuit, an arctangent circuit that converts an output signal of the modulation component removal circuit into phase information for each subcarrier and outputs a phase error signal, and is connected to the arctangent circuit and the initial phase memory circuit; Calculate the power of the initial phase of each subcarrier output from the phase memory circuit, and calculate the phase error signal After averaging, a selection and averaging circuit for calculating a residual frequency error per clock, and an integrating circuit for integrating the residual frequency error output from the selection and averaging circuit and outputting a residual frequency error signal. It is characterized by.

The delay circuit delays the input signal for each subcarrier. The difference vector detection circuit detects a difference vector by conjugate complex multiplication of the input signal and a signal delayed by the delay circuit. The modulation component removal circuit removes a modulation component from the difference vector output from the difference vector detection circuit. The arc tangent circuit converts an output signal of the modulation component elimination circuit into phase information for each subcarrier, and outputs a phase error signal.

The selection / average circuit processes the signals output from the arc tangent circuit and the initial phase memory circuit, calculates the power of the initial phase of each subcarrier output from the initial phase memory circuit, After averaging only the phase error signals for the subcarriers whose power is greater than the threshold, the residual frequency error per clock is calculated. The integrating circuit integrates the residual frequency error output from the selection / averaging circuit and outputs a residual frequency error signal.

According to a ninth aspect of the present invention, in the OFDM demodulation circuit according to any one of the first, second, third, and fourth aspects, the residual frequency error detection circuit includes a modulation component for removing a modulation component from an input signal. A vector addition circuit connected to the removal circuit and the modulation component removal circuit, for adding a vector of the output signal of the modulation component removal circuit for each subcarrier, and removing a noise component of the output signal; and connected to the vector addition circuit. After converting the output signal of the vector adder circuit into phase information, an arc tangent circuit for calculating a residual frequency error per clock is provided.

The modulation component removing circuit removes the modulation component from the input signal. The vector addition circuit vector-adds the output signal of the modulation component removal circuit for each subcarrier, and removes a noise component of the output signal. The arctangent circuit converts the output signal of the vector addition circuit into phase information,
Calculate the residual frequency error per clock. According to a tenth aspect, in the OFDM demodulation circuit according to any one of the first, second, third, and fourth aspects, the residual frequency error detection circuit includes a modulation component removal circuit that removes a modulation component from an input signal. An arc tangent circuit connected to the modulation component elimination circuit, for converting an output signal of the modulation component elimination circuit into phase information for each subcarrier, and outputting a phase error signal; the arc tangent circuit and the initial phase memory circuit Connected to
After calculating the power of the initial phase of each subcarrier output from the initial phase memory circuit, after averaging only the phase error signal for subcarriers whose power is greater than a threshold,
And a selecting / averaging circuit for calculating a residual frequency error per clock.

The modulation component removing circuit removes the modulation component from the input signal. The arc tangent circuit converts an output signal of the modulation component elimination circuit into phase information for each subcarrier, and outputs a phase error signal. The selection and averaging circuit processes the signals output by the arctangent circuit and the initial phase memory circuit, calculates the initial phase power of each subcarrier output from the initial phase memory circuit, and sets the power to a threshold. After averaging only the phase error signals for the larger subcarriers, the residual frequency error per clock is calculated.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An OFDM demodulation circuit according to this embodiment will be described with reference to FIGS. 1, 5, 6, and 10. FIG. This embodiment corresponds to claims 1, 5, 5, and 7.

FIG. 1 is a block diagram showing an OFDM demodulation circuit of this embodiment. FIG. 5 is a block diagram showing a configuration example of the initial estimation AFC circuit. FIG. 6 is a block diagram showing a configuration example of the residual frequency error detection circuit. FIG. 10 is a schematic diagram showing a burst format used in this embodiment.
In this embodiment, the initial estimation AFC circuit, the transmission line estimation circuit, the residual frequency correction circuit, the fast Fourier transform circuit, the initial phase memory circuit, the phase detection circuit, and the residual frequency error detection circuit of the first embodiment are respectively composed of the initial estimation AFC circuit 10 , Transmission line estimation circuit 20, residual frequency correction circuit 30, FFT circuit 40, initial phase memory circuit 50, phase detection circuit 60,
This corresponds to the residual frequency error detection circuit 70.

The delay circuit, the phase rotation angle detection circuit, the averaging circuit, the initial frequency error detection circuit, the integrating circuit, the received signal delay circuit and the initial frequency correction circuit according to the present invention comprise a delay circuit 101 and a phase rotation angle detection circuit, respectively. It corresponds to the circuit 102, the averaging circuit 103, the initial frequency error detection circuit 104, the integrating circuit 105, the received signal delay circuit 100, and the initial frequency correction circuit 106.

A delay circuit, a difference vector detection circuit, a modulation component removal circuit, a vector addition circuit, an arc tangent circuit, and an integration circuit according to claim 7 are a delay circuit 111, a difference vector detection circuit 110, a modulation component removal circuit 112, a vector Adder circuit 120, arc tangent circuit 130, and integrating circuit 140
Corresponding to

The OFDM demodulation circuit shown in FIG. 1 assumes that the received OFDM signal has a burst format shown in FIG. Referring to FIG. 10, in the OFDM signal, the same known preamble PRE repeatedly appears at the beginning of a packet over two OFDM symbols. Also, a guard interval GI is added before the first preamble PRE. Following these preambles PRE, an OFDM composed of a guard interval GI and data DATA
Symbols appear repeatedly.

The OFDM demodulation circuit shown in FIG. 1 includes an initial estimation AFC circuit 10, a transmission line estimation circuit 20, a residual frequency correction circuit 30, an FFT circuit 40, and an initial phase memory circuit 5.
0, phase detection circuit 60 and residual frequency error detection circuit 70
It is composed of The thick solid line shown in FIG. 1 indicates that many subcarrier signal components multiplexed as an OFDM signal appear as parallel signals of the number of subcarriers.

The OFDM signal received by the receiver is converted into a digital signal by an A / D (analog / digital) conversion circuit (not shown), and an initial estimation AFC circuit 1
Input to 0. This OFDM signal is a complex signal. The initial estimation AFC circuit 10 detects an initial frequency error by using the same preamble repeatedly appearing in a section where the preamble PRE appears in the OFDM signal. Further, the initial estimation AFC circuit 10 corrects the entire packet including the preamble PRE based on the detected initial frequency error.

The OFDM signal whose initial frequency error has been corrected by the initial estimation AFC circuit 10 is transmitted to the transmission path estimation circuit 20.
Is input to The transmission path estimating circuit 20 receives the input OF
The impulse response of the transmission path is estimated using the fact that the preamble of the DM signal is known. In this embodiment, the RLS algorithm is used for estimating the impulse response in the transmission path estimation circuit 20. The RLS algorithm is expressed by the following equations (1) to (4).

E (n) = r (n) −W ^H · (n−1) · u (n) (1) W (n) = W (n−1) + k (n) · e ^* (n) (2) P (n) = λ ⁻¹ P (n−1) −λ ⁻¹ k (n) · u ^H (n) · P (n−1) (3) k (n) = (λ ⁻¹ P (n−1) · u (n)) / (1 + λ ⁻¹ u ^H (n) · P (n−1) · u (n)) (4) Where e (n): pre-estimated error vector r (n): received signal u (n): transmitted signal vector W (n): estimated impulse response vector k (n): Kalman gain vector P (n): correlation matrix In this example, since the transmission signal vector u (n) is known,
Equations (3) and (4), which are the equations for updating the Kalman gain vector k (n), can be calculated in advance before inputting the received signal r (n). Therefore, in this embodiment, the ROM storing the data of the calculation results of the equations (3) and (4) is built in the transmission path estimation circuit 20, and the impulse response is estimated using the data of the ROM. .

Therefore, there is no need to execute the calculations of the equations (3) and (4) inside the transmission path estimation circuit 20.
The time required to execute the LS algorithm is reduced. Further, when the number of points of the fast Fourier transform (FFT) is N and the maximum delay amount of the impulse response of the transmission path is M, it is assumed that the condition of (N> M) is satisfied, and the transmission path estimation circuit 20 The number of taps for estimating the response is set to the maximum delay amount M, and the impulse response is fixed to 0 for (N−M) taps.

By limiting the number of taps for obtaining the impulse response to the maximum delay amount M, the transmission path estimation circuit 2
It is possible to reduce the circuit scale of 0. In addition, since the influence of noise is reduced, the characteristics can be improved.

The impulse response estimated by the transmission path estimating circuit 20 passes through the residual frequency correcting circuit 30 and
It is input to the T circuit 40. However, the residual frequency correction circuit 3
If it is 0, nothing is performed on the impulse response, and the input impulse response is output to the FFT circuit 40 as it is. By the fast Fourier transform of the FFT circuit 40, a parallel signal in the frequency domain separated for each subcarrier is obtained at the output of the FFT circuit 40.

The signal output from the FFT circuit 40 first is
The initial phase signal of each subcarrier is input to the initial phase memory circuit 50, and the initial phase signal over one packet section is stored in the initial phase memory circuit 50. After the end of the preamble PRE, the received signal whose initial frequency error has been corrected by the initial estimation AFC circuit 10 is input to the residual frequency correction circuit 30 to correct the residual frequency error. The residual frequency correction circuit 30 corrects the residual frequency using the frequency signal output from the residual frequency error detection circuit 70.

The signal whose residual frequency error has been corrected by the residual frequency correction circuit 30 is input to the FFT circuit 40 and subjected to fast Fourier transform. At the output of the FFT circuit 40, parallel signals in the frequency domain separated for each subcarrier are obtained.
The parallel signal in the frequency domain output from the FFT circuit 40 is input to the phase detection circuit 60 and detected by the initial phase signal for each subcarrier output from the initial phase memory circuit 50. The detection output signal output from the phase detection circuit 60 is applied to a deinterleave circuit and a Viterbi decoding circuit (not shown), and is also input to a residual frequency error detection circuit 70 to detect a residual frequency error.

The residual frequency error detection circuit 70 detects a residual frequency error based on the detection output signal output from the phase detection circuit 60, and applies the detected residual frequency error signal to the residual frequency correction circuit 30. The residual frequency error detection circuit 70 does not require a pilot signal to detect the residual frequency error, and tracks the residual frequency error using the data DATA of the OFDM signal.

As described above, the OFDM demodulation circuit shown in FIG. 1 uses the preamble PRE for detecting the initial frequency error and the initial phase, and uses the data DATA for tracking the residual frequency error. 2 OFDM symbols are sufficient for the preamble PRE to be arranged in the burst format. OFDM shown in FIG.
When using a demodulation circuit for transmission, the preamble P to be transmitted
Since it is not necessary to increase the number of REs or add a special redundant bit to the data DATA, the transmission efficiency does not deteriorate, and the same transmission efficiency as that of the OFDM demodulation circuit that performs the delay detection can be obtained. In addition, since synchronous detection is performed, a high-quality demodulated output can be obtained.

The initial estimation AFC circuit 10 used in the OFDM demodulation circuit shown in FIG. 1 is configured, for example, as shown in FIG.
Referring to FIG. 5, the initial estimation AFC circuit 10 includes a reception signal delay circuit 100, a delay circuit 101, a phase rotation angle detection circuit 102, an averaging circuit 103, an initial frequency error detection circuit 104, an integration circuit 105, and an initial frequency correction circuit 106.
It is composed of

The delay circuit 101 converts the input signal into one OFDM signal.
A signal delayed by a symbol is output. The phase rotation angle detection circuit 102 performs complex conjugate multiplication of the input signal and the delayed signal output from the delay circuit 101. At the timing when the same preamble PRE repeatedly appears in the OFDM signal over two OFDM symbols, the result of the complex conjugate multiplication of the phase rotation angle detection circuit 102 indicates the phase rotation angle according to the initial frequency error of the received signal.

The averaging circuit 103 averages the phase rotation angle signal output from the phase rotation angle detection circuit 102 over a certain period in order to remove the influence of noise components. The initial frequency error detection circuit 104 divides the phase rotation angle averaged by the averaging circuit 103 by the period of one OFDM symbol.

Here, the period of one OFDM symbol is represented by a numerical value with one pulse period of a clock pulse used for control as a unit. Therefore, the initial frequency error detection circuit 104 outputs the phase rotation angle per one clock pulse. The integration circuit 105 includes an initial frequency error detection circuit 104
Are integrated, and the result is generated as an initial frequency error signal.

On the other hand, when the input signal is
In order to compensate for the delay time T0 from when the signal is applied to
The reception signal delay circuit 100 delays an input signal and outputs a signal delayed by the delay time T0. The initial frequency correction circuit 106 corrects the delayed signal output from the reception signal delay circuit 100 with the initial frequency error signal output from the integration circuit 105.

In this embodiment, the residual frequency error detection circuit 70 of the OFDM demodulation circuit shown in FIG. 1 is configured as shown in FIG. Referring to FIG. 6, the residual frequency error detection circuit 70 includes a difference vector detection circuit 110, a delay circuit 11
1, modulation component removal circuit 112, vector addition circuit 12
0, an arc tangent circuit 130 and an integrating circuit 140.

Difference vector detection circuit 110, delay circuit 1
11 and the modulation component elimination circuit 112 are provided in parallel by the number of subcarriers included in the OFDM signal. Input signal (detection output signal) applied from the phase detection circuit 60
Are input to the delay circuit 111 for each subcarrier. Delay circuit 111 outputs a signal obtained by delaying the input signal by one OFDM symbol. The difference vector detection circuit 110 performs complex conjugate multiplication of the input signal and the signal delayed by the delay circuit 111. The result of this complex conjugate multiplication is a difference vector d (n). In order to remove the modulation component, the modulation component elimination circuit 112 performs the following processing on the difference vector d (n) output from the difference vector detection circuit 110.
(5) The operation of the expression is performed.

D (n) = d (n) −tan (2 · i · π / N) (5) where ((2 · i−1) π / N) ≦ tan ⁻¹ (d ( n)) <((2 · i + 1)
π / N) N: modulation multi-level number i: integer from 1 to (N−1)
12 is a difference vector d (n) obtained for each subcarrier.
Is vector-added. This vector addition removes the effect of noise.

Arc tangent circuit 130
Calculates the inverse tangent of the signal output by the vector addition circuit 120 to generate a phase signal. Further, in order to obtain a residual frequency error per one pulse period of the clock pulse,
The phase signal is divided by the period of one OFDM symbol.
The integrating circuit 140 outputs the result of integrating the residual frequency error output from the arc tangent circuit 130 as an output signal (residual frequency error signal). This residual frequency error signal is
It is applied to the residual frequency correction circuit 30 shown in FIG.

(Second Embodiment) OFDM of this embodiment
The demodulation circuit for use will be described with reference to FIGS. This embodiment corresponds to claims 2, 5, 6, and 8. This embodiment is a modification of the first embodiment. FIG. 2 is a block diagram showing an OFDM demodulation circuit of this embodiment. FIG. 7 is a block diagram showing a configuration example of the residual frequency error detection circuit. The thick solid line shown in FIG.
This shows that signal components of many subcarriers multiplexed as an OFDM signal appear as parallel signals of the number of subcarriers. In FIG. 2, the same elements as those in the first embodiment are denoted by the same reference numerals. The description of the same elements is omitted.

In this embodiment, the initial estimation AFC
The circuit, the transmission path estimation circuit, the fast Fourier transform circuit, the residual frequency correction circuit, the initial phase memory circuit, the phase detection circuit, and the residual frequency error detection circuit are respectively an initial estimation AFC circuit 10, a transmission path estimation circuit 20, an FFT circuit 40, It corresponds to the residual frequency correction circuit 35, the initial phase memory circuit 50, the phase detection circuit 60, and the residual frequency error detection circuit 72.

The delay circuit, the difference vector detection circuit, the modulation component removal circuit, the arc tangent circuit, the selection / average circuit, and the integration circuit according to claim 8 are a delay circuit 111, a difference vector detection circuit 110, and a modulation component removal circuit, respectively. 112, arc tangent circuit 135, selection / average circuit 150, and integrating circuit 14
Corresponds to 0. As in the first embodiment, the OFDM demodulation circuit shown in FIG. 2 assumes that the received OFDM signal has a burst format shown in FIG. The OFDM demodulation circuit of FIG.
Compared with the demodulation circuit for use, the method of detecting and correcting the residual frequency error is different, and the method of detecting the initial frequency error and the method of detecting the initial phase are the same.

In the OFDM demodulation circuit shown in FIG.
The initial frequency error is corrected in the preamble section of the FDM signal, and the detected initial phase is stored in the initial phase memory circuit 50. Thereafter, the received OFDM signal is FFT
The signal is input to the circuit 40 and subjected to fast Fourier transform. FFT
At the output of the circuit 40, parallel signals in the frequency domain separated for each subcarrier are obtained. This parallel signal is applied to the residual frequency correction circuit 35 for each subcarrier to correct the residual frequency error. The residual frequency correction circuit 35
The residual frequency error of each subcarrier is corrected using the frequency signal applied from the residual frequency error detection circuit 72.

The signal whose residual frequency error has been corrected by the residual frequency correction circuit 35 is input to the phase detection circuit 60, and is detected for each subcarrier using the phase signal output from the initial phase memory circuit 50. Phase detection circuit 60
Are output to a deinterleave circuit and a Viterbi decoding circuit (not shown), and a residual frequency error detection circuit 7 is provided to detect a residual frequency error.
2 is input.

The residual frequency error detection circuit 72 detects a residual frequency error for each subcarrier using the detection output signal output from the phase detection circuit 60 and the initial phase signal output from the initial phase memory circuit 50. A signal indicating the detected residual frequency error is applied to the residual frequency correction circuit 35. The residual frequency error detection circuit 72 does not require a pilot signal to detect the residual frequency error.

In this embodiment, the residual frequency error detecting circuit 72 of FIG. 2 is configured as shown in FIG. In FIG. 7, the same components as those in FIG. 6 are denoted by the same reference numerals. Referring to FIG. 7, the residual frequency error detection circuit 72 includes a difference vector detection circuit 110, a delay circuit 11
1, a modulation component removal circuit 112, an arc tangent circuit 135, a selection / average circuit 150, and an accumulation circuit 140.

The detection output signal output from the phase detection circuit 60 is applied as an input signal to the residual frequency error detection circuit 72 of FIG. 7 for each subcarrier. The signal of the initial phase output from the initial phase memory circuit 50 is applied to the selection / averaging circuit 150 for each subcarrier. Similar to the residual frequency error detection circuit 70 of FIG. 5, the difference vector detection circuit 110 detects a difference vector for each subcarrier based on the input signal and the signal delayed by the delay circuit 111.
The modulation component elimination circuit 112 includes the differential vector detection circuit 11
The modulation component is removed from the difference vector output by 0.

The arc tangent circuit 135 is provided for each subcarrier.
The phase error signal is generated by calculating the arc tangent of the difference vector output from the modulation component removal circuit 112. The selection / averaging circuit 150 averages the phase error signal output from the arc tangent circuit 135 in order to remove the influence of noise. Choice·
When averaging, the averaging circuit 150 uses only a selected part of the phase error signals of a number of subcarriers. Specifically, first, the power of each phase signal output from the initial phase memory circuit for all subcarriers is obtained. Then, a subcarrier whose obtained power is larger than a predetermined threshold is selected. The phase signals are averaged for the selected subcarriers.

The selection / averaging circuit 150 divides the averaged phase by the period of one OFDM symbol to obtain a residual frequency error per clock pulse period. The integrating circuit 140 integrates the residual frequency error output from the selecting / averaging circuit 150, and applies the result as an output signal (residual frequency error signal) to the residual frequency correction circuit 35.

(Third Embodiment) OFDM of this Embodiment
The demodulation circuit for use will be described with reference to FIGS. This embodiment corresponds to claims 3, 5, 5, and 9. This embodiment is a modification of the first embodiment. FIG. 3 is a block diagram showing an OFDM demodulation circuit of this embodiment. FIG. 8 is a block diagram showing a configuration example of the residual frequency error detection circuit. The thick solid line shown in FIG.
This shows that signal components of many subcarriers multiplexed as an OFDM signal appear as parallel signals of the number of subcarriers. In FIG. 3, the same elements as those in the first embodiment are denoted by the same reference numerals. The description of the same elements is omitted.

In this embodiment, the initial estimated AFC
The circuit, the transmission line estimation circuit, the transmission line delay estimation circuit, the tap selection circuit, the delay circuit, the residual frequency correction circuit, the fast Fourier transform circuit, the initial phase memory circuit, the phase detection circuit, and the residual frequency error detection circuit are each an initial estimation AFC. Circuit 1
0, transmission path estimation circuit 20, transmission path delay estimation circuit 81, tap selection circuit 82, delay circuit 80, residual frequency correction circuit 30, FFT circuit 40, initial phase memory circuit 50, phase detection circuit 60, residual frequency error detection circuit 70 corresponding.

The modulation component elimination circuit, the vector addition circuit and the arc tangent circuit according to the ninth aspect respectively comprise the modulation component elimination circuit 112, the vector addition circuit 120 and the arc tangent circuit
Corresponding to 30. As in the first embodiment, the OFDM demodulation circuit shown in FIG. 3 assumes that the received OFDM signal has a burst format shown in FIG. Regarding the method of detecting the initial frequency error and the method of detecting the initial phase, the OFDM demodulation circuit of FIG. 3 is the same as the OFDM demodulation circuit of FIG. However, the OF of FIG.
A transmission line delay estimation circuit 81 and a tap selection circuit 82 are added to the DM demodulation circuit, and the method of detecting the residual frequency error is changed.

As in the first embodiment, the OFD shown in FIG.
In the OFDM signal input to the M demodulation circuit, an initial frequency error is detected and corrected in a section where the preamble PRE appears. After the preamble PRE section ends, the input OFDM signal is input to the transmission path delay estimating circuit 81 and the delay circuit 80. The transmission line delay estimation circuit 81
The impulse response of the input signal is calculated based on the correlation between the reception signal r (n) and the transmission signal u (n). However, this method cannot completely remove the influence of noise, so that the transmission path delay estimating circuit 81 can only obtain a coarse impulse response.

The transmission path delay estimating circuit 81 compares the obtained power of the impulse response with a predetermined threshold value for each tap to detect the maximum delay time of the impulse response. The tap selection circuit 82 determines the number of taps of the impulse response estimated by the transmission path estimation circuit 20 based on the maximum delay time detected by the transmission path delay estimation circuit 81. The number of taps determined by the tap selection circuit 82 is applied to the transmission path estimation circuit 20.

The delay circuit 80 includes a transmission line delay estimation circuit 81
The OFDM signal input to the transmission path estimating circuit 20 is delayed by a time necessary for the processing of the tap selecting circuit 82.
Accordingly, the transmission path estimation circuit 20 can estimate the impulse response of the transmission path with the number of taps determined by the tap selection circuit 82.

The transmission path estimation in the transmission path estimation circuit 20 and the correction of the residual frequency in the residual frequency correction circuit 30 are the same as those in the first embodiment. In this embodiment, the number of taps used for estimating the impulse response of the transmission path estimation circuit 20 can be dynamically controlled by the transmission path delay estimation circuit 81 and the tap selection circuit 82.
The OFDM demodulation circuit in FIG. 3 can be applied to a plurality of types of transmission lines having different delay times.

In this embodiment, the residual frequency error detection circuit 74 of FIG. 3 is configured as shown in FIG. Referring to FIG. 8, the residual frequency error detection circuit 74 includes a modulation component removal circuit 112, a vector addition circuit 120, and an arc tangent circuit 1
30. The input signal applied to the residual frequency error detection circuit 74 in FIG. 8 is applied to the modulation component removal circuit 112 for each subcarrier, and the modulation component is removed.

The residual frequency error detecting circuit 72 shown in FIG.
Although the modulation component is removed from the phase difference between one OFDM symbol in FIG. 8, the residual frequency error detection circuit 74 in FIG. 8 removes the modulation component from the absolute phase input to the modulation component removal circuit 112. Therefore, the residual frequency error detection circuit 74
Need not be provided with the integrating circuit 140 shown in FIG. Therefore, the circuit configuration of the residual frequency error detection circuit 74 of FIG. 8 is simplified.

(Fourth Embodiment) OFDM of this embodiment
The demodulation circuit for use will be described with reference to FIGS. This embodiment corresponds to claims 4, 5, 6, and 10. This embodiment is a modification of the second embodiment. FIG. 4 is a block diagram showing an OFDM demodulation circuit of this embodiment. FIG. 9 is a block diagram showing a configuration example of the residual frequency error detection circuit. The thick solid line shown in FIG. 4 indicates that signal components of many subcarriers multiplexed as an OFDM signal appear as parallel signals of the number of subcarriers. In FIG. 4, the same elements as those in the second embodiment are denoted by the same reference numerals. The description of the same elements is omitted.

In this embodiment, the initial estimated AFC
The circuit, the transmission line estimation circuit, the transmission line delay estimation circuit, the tap selection circuit, the delay circuit, the fast Fourier transform circuit, the residual frequency correction circuit, the initial phase memory circuit, the phase detection circuit, and the residual frequency error detection circuit are each an initial estimation AFC. Circuit 1
0, transmission line estimation circuit 20, transmission line delay estimation circuit 81, tap selection circuit 82, delay circuit 80, FFT circuit 40, residual frequency correction circuit 35, initial phase memory circuit 50, phase detection circuit 60, and residual frequency error detection circuit 76.

The modulation component elimination circuit, arc tangent circuit and selection / average circuit of the tenth aspect are respectively a modulation component elimination circuit 112, arc tangent circuit 135 and selection / average circuit 15
Corresponds to 0. The method of detecting the initial frequency error and the method of detecting the initial phase in the OFDM demodulation circuit shown in FIG. 4 are the same as those in the second embodiment. Also,
The transmission line delay estimation circuit 81 and the tap selection circuit 82 shown in FIG.
Is the same as in the third embodiment. However, the method of detecting the residual frequency error is different from any of the embodiments.

In this embodiment, the residual frequency error detection circuit 76 of FIG. 4 is configured as shown in FIG. Referring to FIG. 9, the residual frequency error detection circuit 76 includes a modulation component removal circuit 112, an arc tangent circuit 135, and a selection / average circuit 150. The modulation component is removed from the input signal applied to the residual frequency error detection circuit 76 of FIG. Although the residual frequency error detection circuit 72 in FIG. 7 removes the modulation component from the phase difference between one OFDM symbol, the modulation component removal circuit 112 in FIG. 9 removes the modulation component from the absolute phase of the input signal. Therefore, the residual frequency error detection circuit 76 shown in FIG.
Does not require the integrating circuit 140 of FIG. For this reason, the configuration of the residual frequency error detection circuit 76 in FIG. 9 is simplified.

[0090]

According to the present invention, there is no need to insert a pilot signal or a redundant bit into an OFDM signal for tracking, and synchronous detection can be realized with a preamble equivalent to that of differential detection, thereby deteriorating transmission efficiency. Thus, the demodulation characteristics can be improved. Further, since the residual frequency error of the initial frequency error detected in the preamble section is tracked in the data section, the characteristic hardly deteriorates.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an OFDM demodulation circuit according to a first embodiment.

FIG. 2 is a block diagram illustrating an OFDM demodulation circuit according to a second embodiment;

FIG. 3 is a block diagram illustrating an OFDM demodulation circuit according to a third embodiment;

FIG. 4 is a block diagram illustrating an OFDM demodulation circuit according to a fourth embodiment;

FIG. 5 is a block diagram illustrating a configuration example of an initial estimation AFC circuit;

FIG. 6 is a block diagram illustrating a configuration example of a residual frequency error detection circuit.

FIG. 7 is a block diagram illustrating a configuration example of a residual frequency error detection circuit.

FIG. 8 is a block diagram illustrating a configuration example of a residual frequency error detection circuit.

FIG. 9 is a block diagram illustrating a configuration example of a residual frequency error detection circuit.

FIG. 10 is a schematic diagram showing a burst format used in the embodiment.

FIG. 11 is a block diagram showing a configuration (1) of a conventional OFDM demodulation circuit.

FIG. 12 is a block diagram illustrating a configuration of a conventional AFC circuit.

FIG. 13 is a block diagram showing a configuration (2) of a conventional OFDM demodulation circuit.

FIG. 14 is a schematic diagram showing a burst format (1) used in a conventional example.

FIG. 15 is a schematic diagram showing a burst format (2) used in a conventional example.

[Explanation of symbols]

 Reference Signs List 10 initial estimation AFC circuit 20 transmission line estimation circuit 30, 35 residual frequency correction circuit 40 FFT circuit 50 initial phase memory circuit 60 phase detection circuit 70, 72, 76 residual frequency error detection circuit 80 delay circuit 81 transmission line delay estimation circuit 82 tap Selection circuit 100 reception signal delay circuit 101 delay circuit 102 phase rotation angle detection circuit 103 averaging circuit 104 initial frequency error detection circuit 105 integration circuit 106 initial frequency correction circuit 110 difference vector detection circuit 111 delay circuit 112 modulation component removal circuit 120 vector addition circuit 130, 135 Arctangent circuit 140 Integrator circuit 150 Selection / average circuit 200 AFC circuit 201 FFT circuit 202 Delay detection circuit 210 Delay circuit 211 Phase rotation angle detection circuit 212 Average circuit 213 Frequency error detection circuit 214 Arithmetic circuit 215 Received signal delay circuit 216 Frequency correction circuit 220 Phase detection circuit 221 P / S circuit 223 Deinterleave circuit 224 Soft decision Viterbi circuit 225 Convolution circuit 226 Interleave circuit 227 MOD circuit 228 S / P circuit 229 Delay circuit 230 Frequency domain transmission Path estimation circuit 231 initial phase memory 232 frequency domain filter circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Nobuaki Mochizuki 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Masahiro Umehira 3-19, Nishishinjuku, Shinjuku-ku, Tokyo No. 2 Nippon Telegraph and Telephone Corporation F-term (reference) 5K022 DD01 DD33

Claims (10)

[Claims] 1. An OFDM demodulation circuit for inputting an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period as a received signal and detecting a frequency error and an initial phase of the orthogonal frequency multiplexed signal. An initial estimation AFC circuit for detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting the received signal with the detected initial frequency error; A transmission path estimating circuit for estimating an impulse response of a transmission path from the preamble signal, and a residual frequency correction for correcting a received signal output by the transmission path estimating circuit with a residual frequency error signal after completion of the preamble signal at the head of a packet. Circuit, the received signal corrected by the residual frequency correction circuit. And a fast Fourier transform circuit for performing a fast Fourier transform after serial-to-parallel conversion of the signal. An initial phase memory circuit for storing an initial phase signal for each subcarrier, and a received signal output by the fast Fourier transform circuit, for each subcarrier of the received signal using the initial phase signal held in the initial phase memory circuit. And a residual frequency error detection circuit that detects a residual frequency error based on a signal output from the phase detection circuit and provides the detection result to the residual frequency correction circuit as the residual frequency error signal. An OFDM demodulation circuit, comprising: 2. An OFDM demodulation circuit for inputting, as a received signal, an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period and detecting a frequency error and an initial phase of the orthogonal frequency multiplexed signal. An initial estimation AFC circuit for detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting the received signal with the detected initial frequency error; A transmission path estimating circuit for estimating an impulse response of a transmission path from the preamble signal, a fast Fourier transform circuit for performing a high-speed Fourier transform after serial-to-parallel conversion of a received signal output by the transmission path estimating circuit, After the end of the preamble signal, the fast Fourier transform A residual frequency correction circuit that corrects the received signal output by the circuit with a residual frequency error signal for each subcarrier, connected to the output of the residual frequency correction circuit, and performing a fast Fourier transform on the impulse response estimated at the head of the packet. An initial phase memory circuit that stores an initial phase signal for each subcarrier of the obtained orthogonal frequency multiplexed signal, and a received signal output by the residual frequency correction circuit, using an initial phase signal held in the initial phase memory circuit. A phase detection circuit for detecting each sub-carrier of the received signal; and a residual frequency error that is detected based on a signal output from the phase detection circuit, and the detection result is provided to the residual frequency correction circuit as the residual frequency error signal. A demodulation circuit for OFDM, comprising a frequency error detection circuit. 3. An OFDM demodulation circuit for inputting an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period as a received signal and detecting a frequency error and an initial phase of the orthogonal frequency multiplexed signal. An initial estimation AFC circuit for detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting the received signal with the detected initial frequency error; and a reception signal corrected by the initial estimation AFC circuit. And a transmission path estimating circuit for estimating an impulse response of a transmission path of a selected number of taps based on the preamble signal at the beginning of a packet. A transmission path estimation circuit connected to an output of the initial estimation AFC circuit, Delay Estimation Circuit for Estimating Delay Profile of Transmission Path A tap selection circuit connected to the transmission path delay estimation circuit and determining the number of taps used for transmission path estimation of the transmission path estimation circuit based on the delay profile estimated by the transmission path delay estimation circuit; A delay circuit for providing a signal obtained by delaying the reception signal output from the initial estimation AFC circuit by the processing time of the transmission path delay estimation circuit and the tap selection circuit to the transmission path estimation circuit, After completion, a residual frequency correction circuit that corrects the received signal output by the transmission path estimation circuit with a residual frequency error signal, and a fast Fourier transform after serial-parallel conversion of the received signal corrected by the residual frequency correction circuit A fast Fourier transform circuit, the impulse connected to the output of the fast Fourier transform circuit and estimated at the beginning of the packet An initial phase memory circuit that stores an initial phase signal for each subcarrier of an orthogonal frequency multiplexed signal obtained by performing a fast Fourier transform on a spawn; and a received signal output by the fast Fourier transform circuit, which is held in the initial phase memory circuit. A phase detection circuit that detects each subcarrier of the received signal using the initial phase signal, and detects a residual frequency error based on a signal output from the phase detection circuit, and uses the detection result as the residual frequency error signal. A demodulation circuit for OFDM, comprising a residual frequency error detection circuit provided to a residual frequency correction circuit. 4. An OFDM demodulation circuit for inputting an orthogonal frequency multiplexed signal in which the same known preamble signal repeatedly appears at a predetermined repetition time period as a received signal and detecting a frequency error and an initial phase of the orthogonal frequency multiplexed signal. An initial estimation AFC circuit for detecting an initial frequency error from the preamble signal appearing at the head of the packet of the orthogonal frequency multiplexed signal, and correcting the received signal with the detected initial frequency error; and a reception signal corrected by the initial estimation AFC circuit. And a transmission path estimating circuit for estimating an impulse response of a transmission path of a selected number of taps based on the preamble signal at the beginning of a packet. A transmission path estimating circuit connected to an output of the initial estimation AFC circuit and receiving a signal from the preamble signal. Delay Estimation Circuit for Estimating Delay Profile in Transmission Path A tap selection circuit connected to the transmission path delay estimation circuit and determining the number of taps used for transmission path estimation of the transmission path estimation circuit based on the delay profile estimated by the transmission path delay estimation circuit; A delay circuit that provides a signal obtained by delaying the reception signal output by the initial estimation AFC circuit by the processing time of the transmission path delay estimation circuit and the tap selection circuit to the transmission path estimation circuit; A fast Fourier transform circuit for performing a fast-Fourier transform after serial-to-parallel conversion of the received signal to be transmitted, and a residual frequency error signal for each sub-carrier for the received signal output by the fast Fourier transform circuit after the end of the preamble signal at the head of the packet. A residual frequency correction circuit that corrects at An initial phase memory circuit for storing an initial phase signal for each subcarrier of an orthogonal frequency multiplexed signal obtained by performing a fast Fourier transform on an impulse response, and a received signal output by the residual frequency correction circuit held in the initial phase memory circuit A phase detection circuit that detects each subcarrier of the received signal using the initial phase signal, and detects a residual frequency error based on a signal output from the phase detection circuit, and uses the detection result as the residual frequency error signal. A demodulation circuit for OFDM, comprising a residual frequency error detection circuit provided to the residual frequency correction circuit. 5. The OFDM demodulation circuit according to claim 1, wherein said initial estimation AFC circuit is a delay circuit for delaying a received signal by a period of one OFDM symbol. A phase rotation angle detection circuit that detects a phase rotation angle by conjugate complex multiplication of a reception signal and a reception signal delayed by the delay circuit; and an average value of the phase rotation angle output by the phase rotation angle detection circuit over a predetermined time. An initial frequency error detection circuit that calculates an initial frequency error from the phase rotation angle averaged by the averaging circuit; and an initial frequency error output by the initial frequency error detection circuit, An integration circuit that outputs the received signal as an error signal; a reception signal delay circuit that delays the reception signal until the initial frequency error signal is output; OFDM demodulating circuit, characterized in that the received signal is constituted by the initial frequency correction circuit for correcting an initial frequency error signal the integrated circuit outputs the receiving signal delay circuit outputs. 6. The OFDM demodulation circuit according to claim 1, wherein an RLS algorithm is used for estimating an impulse response of said transmission path estimating circuit, and a demodulation circuit for a known preamble is used. A ROM for holding the result of previously calculating the Kalman gain vector is provided, the number of taps of the impulse response obtained by the RLS algorithm is set to the maximum delay time of the delay wave, and the impulse response after the maximum delay time of the delay wave is set to 0. A demodulation circuit for OFDM, comprising: 7. The OFDM demodulation circuit according to claim 1, wherein said residual frequency error detection circuit comprises: a delay circuit for delaying an input signal for each subcarrier. A difference vector detection circuit that detects a difference vector by conjugate complex multiplication of the input signal and the input signal delayed by the delay circuit; and a modulation component removal circuit that removes a modulation component from a signal output from the difference vector detection circuit. A vector addition circuit that removes noise components included in the output signal by vector-adding the output signal of the modulation component removal circuit for each subcarrier, and after converting the output signal of the vector addition circuit into phase information, An arc tangent circuit for calculating a residual frequency error per clock based on the phase information; and a residual frequency error output from the arc tangent circuit. An OFDM demodulation circuit comprising an integration circuit for integrating the difference and outputting a residual frequency error signal. 8. The OFDM demodulation circuit according to claim 1, wherein said residual frequency error detection circuit comprises a delay circuit for delaying an input signal for each subcarrier. A difference vector detection circuit that detects a difference vector by conjugate complex multiplication of the input signal and the signal delayed by the delay circuit; a modulation component removal circuit that removes a modulation component from the difference vector output by the difference vector detection circuit. An inverse tangent circuit that converts an output signal of the modulation component removing circuit into phase information for each subcarrier and outputs a phase error signal; and the initial phase memory circuit is connected to the inverse tangent circuit and the initial phase memory circuit. Calculate the power of the initial phase of each subcarrier output from the subcarrier, average only the phase error signal for the subcarriers whose power is larger than the threshold After that, a selecting / averaging circuit for calculating a residual frequency error per clock, and an integrating circuit for integrating a residual frequency error output from the selecting / averaging circuit and outputting a residual frequency error signal. OFDM demodulation circuit. 9. The OFDM demodulation circuit according to claim 1, wherein the residual frequency error detection circuit comprises a modulation component removal circuit for removing a modulation component from an input signal. A vector addition circuit that is connected to the modulation component removal circuit, adds a vector of the output signal of the modulation component removal circuit for each subcarrier, and removes a noise component of the output signal; An OFDM demodulation circuit comprising: an arc tangent circuit for calculating a residual frequency error per clock after converting an output signal of a vector addition circuit into phase information. 10. The OFDM demodulation circuit according to claim 1, wherein the residual frequency error detection circuit comprises a modulation component removal circuit for removing a modulation component from an input signal. An inverse tangent circuit that is connected to the modulation component elimination circuit, converts an output signal of the modulation component elimination circuit into phase information for each subcarrier, and outputs a phase error signal; and the arc tangent circuit and the initial phase memory circuit. And calculates the power of the initial phase of each subcarrier output from the initial phase memory circuit, averages only the phase error signal for the subcarriers whose power is larger than the threshold, and then calculates the residual frequency error per clock. A demodulation circuit for OFDM, comprising a selection and averaging circuit that calculates