JPS62273667A - Rotary body driving device - Google Patents

Abstract

PURPOSE:To attain the operation processing by making operation processing number of a phase control means driving a rotary body variable in response to a time after a rotational phase detection output is generated till it is generated again so as to prevent phase variation. CONSTITUTION:In closing a motor start switch 1, a system control operation section 2 starts a motor 9 via a D/A converter 7 to apply speed control. A mode changeover switch 11 is thrown to the position (a), the content of a timer counter 3 is held in a latch circuit 4 at the leading of the FG pulse signal 12 and the operation section 2 uses the difference between the period of the held signal 12 and the control object period as a deviation thereby operating a manip ulated variable. When the speed of the motor 9 is stabilized, the switch 11 is switched to the position (b), a reference signal is generated from a control reference signal generating circuit 6, the phase difference between the reference signal and the signal 12 is obtained from the content of the circuit 4 to apply phase control. The operating section 12 makes the number of times of operations of the phase control variable in response to the time after the FG pulse is generated till the pulse is generated again to eliminate phase variation for the operation processing.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to a rotating body driving device.

[Prior Art] In a conventional rotary body drive device, for example, a rotary body drive device such as a disk drive device in an electronic still camera, the phase of the motor is adjusted to a reference signal for regulating the operation timing of the entire camera. The drive was controlled. Therefore, it took a long time to control the speed of the motor (phase control) using the phase, and the start-up characteristics of the camera were poor.

In addition, as a method of phase control, for example, π
FG (Frequency Generator)
) It is conceivable to control the motor by synchronizing the phase of the pulses, but in this case, the range in which the phase can be controlled is limited to a range in which the phase delay of the FG pulse with respect to the reference signal is 0 or more and 2π or less.

However, the phase difference may exceed the controllable range due to sudden changes in the load on the motor.

For example, as shown in Figure 5, when the phase difference between the reference signal and the FG pulse is (15
78) It is near π, and the phase of the FG pulse from the reference signal further increases by (1/8) at the time of the next sample, that is, by the nth time.
If there is a delay of π or more, the phase delay of the FG pulse with respect to the reference signal will become 2π or more. However, the above-described control method has a problem in that in this case, it is determined that the phase shift has become small, making appropriate control impossible.

[Problems to be Solved by the Invention] Therefore, the purpose of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a rotating body driving device that can accurately control the phase of a rotating body even when large load fluctuations occur.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a rotation driving means for driving a rotating body, a detection means for detecting a rotational phase of the rotating body, and a periodic reference signal forming. a reference signal source, a phase control means for controlling the rotation drive means to maintain a constant phase difference by comparing the phase difference between the output of the reference signal source and the output of the detection means with a predetermined value; The present invention is characterized in that it includes a control means that varies the number of arithmetic operations of the phase control means in accordance with the time from when the output is generated until the output of the detection means is generated again.

"Effect" According to the present invention, when detection is performed by the detection means,
That is, for example, in a case where calculations for phase control by the phase control means cannot be completed in time, efficient control is possible by performing only the minimum necessary calculations in response to the detection.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of an electronic still camera including a disk drive device as an embodiment of the rotating body drive device of the present invention. In the figure, 1 is a motor start switch, 2 is a system control calculation unit that controls the entire device and performs various calculations, etc., which includes a CPU in the form of a microcomputer, a RAM having a work area, etc., as shown in FIG. 2 described later. It has a ROM that stores such procedures, a counter, etc. 3 is a timer counter circuit that performs time counting from O by resetting (RESET) at the rising edge of the human input signal; 4 is a latch circuit that holds the contents of the timer counter circuit 3 every time the human input signal rises;
Each part 2.3 and 4 constitute a phase control means. Reference numeral 5 indicates a system reference signal generation port as a synchronization signal source that generates the overall timing signal (synchronization signal) of the electronic still camera in which the motor is incorporated, and reference number 6 indicates a reference signal that generates a signal that serves as a reference for phase control of the motor. Motor control reference signal generation circuit as a signal source, 7 is a D/8 converter, 8 is D
A motor drive circuit amplifies the /A converted motor control signal, and 9 is a motor as a rotation drive means.

IO is an FG (frequency
11 is a mode switching signal 14
A side for setting the speed control mode using speed deviation (hereinafter referred to as speed control mode) and B side for setting the speed control mode using phase synchronization (phase control mode).
19 is a phase signal generator (PG) that outputs a pulse synchronized with the motor phase at H level once per motor rotation; 21 is an AND gate;
12 is the output signal of the FG circuit 1, 13 is the RESET signal manually input to the reset input terminal of the counter circuit 3, 1
5 is a READY signal which is outputted from the calculation unit 2 and is at H level when the phase is synchronized and L level when it is not synchronized; 16 is a reference signal generation timing signal which is output from the calculation unit 2; 17
is the reference signal 1 output from the control reference signal generation circuit 6;
8 is the output signal from PGI1, 20 is the READY signal 1
This is a one-shot circuit that generates an H-level one-shot pulse having a width approximately equal to the period of the FG of the motor when the signal 5 changes from the L level to the H level. 22 is an imaging device, 2
3 is a signal processing circuit, 24 is a head, and 25 is a recording medium as a rotating body to be controlled.

Next, the operation in the configuration shown in the first figure will be explained.

FIG. 2 shows an example of a drive control procedure for a rotating body according to this embodiment. In this embodiment, the motor 9 is synchronized with the vertical synchronization signal of the video signal, and at the time of phase synchronization, the period of the FG signal 12 of the motor 9 and the reference signal 17 from the control reference signal generation circuit are synchronized.
, and the phase difference between the rising edge of the FG signal pulse and the rising edge of the reference signal 17 is set to π.

At the initial stage, it is assumed that the motor 9 is not rotating. At this initial stage, the switch 11 is set to the a side, that is, the speed control mode side. Here, when the motor start switch 1 is closed in step 51, step S2
Then, the system control calculation unit 2 outputs a constant value sufficient to start the motor 9 to the D/A converter 7.

The process then proceeds to step S3, where the speed of the motor 9 is controlled as described below, and then the process proceeds to step S4, where the calculation unit 2 determines whether or not the speed is stable. That is, first, in step S3, a signal from the D/A converter 7 is input to the drive circuit 8, and a signal based on this is supplied to the motor 9 from the drive circuit 8. Then, the motor 9 starts rotating, and an FG pulse signal 12 proportional to the rotation period of the motor 9 is output from the FG circuit IO. Here switch 11
Since is on the a side, the contents of the timer counter circuit 3 are held in the latch circuit 4 at the rising edge of the FG pulse signal 12, and the timer counter circuit 3 is reset to restart time counting from 0. That is, the latch circuit 4 holds the period of the FG pulse every rising edge of the FG pulse signal. The calculation unit 2 calculates the period of the held FG pulse and the control target period (for example, NTSC
In the case of this method, the operation amount is calculated using the difference with the vertical synchronization signal frequency (1/60 seconds) as the deviation amount, and the calculation result is output to the D/C converter 7. In this way, the speed of motor 9 is controlled.

Next, the process proceeds to step S4, in which the calculating section 2 determines whether the speed of the motor 9 is sufficiently stable near the target speed based on the deviation amount. If the amount of deviation is greater than or equal to a predetermined value, it is determined that the speed is not stable, and the process returns to step S3, and if it is within the predetermined value, the speed is determined to be stable and the process proceeds to step S5.

In step S5, the arithmetic unit 2 determines whether or not the FG pulse has risen, and if the determination is affirmative, the process proceeds to step S6, where the arithmetic unit 2 counts a time using a built-in counter from the time of the rise of the FG pulse. Next, proceed to step S7 and start counting [
The calculation unit 2 determines whether 1/21 time of the period of the FG pulse during synchronization minus the period of the FG pulse during synchronization, that is, π time has elapsed.If the determination is affirmative, the process proceeds to step S8.

In step S8, in the calculation section 2, the switch 1
1 to the phase control mode side, that is, to the b side, and then in step S9, the reference signal generation timing signal 16 from the calculation section 2 is manually inputted to the control reference signal generation circuit 6.
When π time has elapsed from the rise of the FG pulse in the arithmetic unit 2, the generation circuit 6 starts outputting the reference signal 17.

FIG. 4 shows the timing of the FG signal and the reference signal at this time. As a result, the counter circuit 3 is reset every time the output signal of the control reference signal generation circuit 6 rises in the phase control mode.

In step 510, the contents of the latch circuit 4 are read by the arithmetic unit 2. The content of the latch circuit 4 is the time count value of the counter circuit 3 from the rise of the reference signal 17 to the rise of the FG pulse, and this indicates the phase difference between the reference signal and the FG pulse signal.

Next, in step 511, a phase difference determination routine, which will be described later, is performed. This routine corrects the amount of deviation between the phase difference between the reference signal and the FG pulse and the target phase difference.

Next, in step S12, the calculation unit 2 calculates the manipulated variable based on the corrected deviation amount, and then proceeds to step 513, where the calculation unit 2 outputs the calculation result, that is, the manipulated variable to the D/A converter 7. do. As a result, rotational phase control of the motor 9 is performed based on the manipulated variable.

Next, proceeding to step 514, the calculation unit 2 calculates the reference signal and the FG based on the read contents of the latch circuit 4.
It is determined whether the phase difference with the pulse is the target phase difference, that is, whether the phase is synchronized. If the phase is not synchronized, the process returns to step 510 and the same procedure is repeated. On the other hand, if it is determined that the phase is synchronized, step S1
5, the H level READY signal 1 is sent from the calculation unit 2.
5 is output, and the process returns to step S10.

Next, the rotating body drive control section, which is the main part of this embodiment, will be explained in detail.

FIG. 3 shows a detailed configuration example of each part 3, 4, 6, and 11, that is, the rotating body drive section shown within the dashed line in FIG. In the figure, 105 and 106 are timer prescalers, and 107 to 110 are clock signals 2 from the initial values set by the timer prescalers 105 and 106.
This is a timer counter that counts by 01, and constitutes the counter circuit 3 in FIG.

Timer latches 111 and 112 hold the values of timer counters 107 to 110 in response to the strobe signal 202, and constitute the latch circuit 4 in FIG. 11
3 is a flip-flop (hereinafter abbreviated as FF) 117.11
114 is a mode setting buffer for controlling the switching of the mode changeover switch 11; 122 is an FF that operates at the timing of the inverted signal 203 of the FG signal 12;
121 is an FF that latches the Q output of FF122 at the timing of the clock signal 201, and 120 is the Q of FF121.
F that latches the output at the timing of clock signal 2Ql
F%116 is an FF that latches the output of the NAND gate 156 at the timing of the clock signal 201.

130-140 are inverter gates, 150-161 are NAND gates, and 170-173 are NOR gates. Note that the reference signal generation circuit 6 also serves as timer counters 107 to 110 in this embodiment.

101 and 102 are a data bus buffer and an address bus buffer, respectively, coupled to the CPU of the system control calculation unit 2 via a data bus and an address bus, and 103 and 104 are address decoders coupled to the address bus buffer 102. Also, C5, RD,
WR and AWR are a chip select signal, a read signal, a write signal, and an address line signal for operating the address bus buffer 102, respectively, which are supplied from the CPU.

Next, an example of the operation of the circuit shown in FIG. 3 will be explained.

First, assume that mode select signals 204 and 205 are set to L level, signal 206 is set to H level, and the device is in phase control mode. At this time, the target period of the FG is set in the prescalers 105 and 106 in two's complement representation, which is an integral multiple of the period of the clock signal 201. Then, the signal 20 delayed slightly from the rise of the FG signal 203
7, the signal 202 goes to L level and the values of timer counters 107 to 110 become timer latches 111 and 11.
2 and an inverted signal 209 of the signal 207.
As a result, the output of the FF 115 becomes H level. In addition, the output of the gate 173 becomes L level due to the overflow signal of the timer counters 107 to 110, and the output of the counter 107 becomes low.
o performs counting again from the values set in prescalers 105 and 106. That is, timer latch 11
1 and 112 hold the values obtained by measuring the time from the start of re-counting of the timer counters 107 to 110 to the rise of the FG signal 203. That is, phase control is performed by controlling the rotational phase of the motor 9 so that this value remains constant.

By the way, as mentioned above, it can be known that the data has been latched in the timer latches 111 and 112 by the Q output of the FF 115 becoming H level.
Consider that the next FG signal 203 rises before the contents of latches 111 and 112 are read. FF1
15 is cleared by the IIEAD strobe signal 210 of the timer latch 112, but if the FG signal 203 is cleared before the 11EAD strobe signal 210 becomes L level.
rises, the output of the NAND gate 153 becomes L level, and the Q output of FF 117 becomes H level. That is, the CPU of the calculation unit 2 performs, for example, the process of phase control processing (
By referring to the contents of the flag buffer 113 corresponding to this signal via the data bus in step Sin-515), it is possible to detect that the FG signal 203 has risen twice or more before reading the contents of the timer latches 111 and 112. .

Generally, when a microcomputer or the like is used to process calculations during phase control, the calculations may not be completed in time as described above. At this time, some of the normal arithmetic processing may be omitted, and only essential processing may be performed in time for the timing of the next FG pulse. For example, even if the phase control calculation is not performed once every few times, the phase of the motor 9 will not be significantly disturbed. Therefore, in such a case, only the process of resetting the FF 117, that is, the process of setting the human power of the gate 139 to the L level, may be performed, and the process may wait for the next data to be latched.

Next, a case will be considered in which the timer counters 107 to 110 overflow, restart counting is started, and the FG signal 203 does not rise even once until the next overflow occurs.

First, when the timer counters 107 to 110 overflow, the output of the NAND gate 156 becomes H level.

Therefore, the Q output of FF 116 is at H level.

In this state, when the FG signal 203 rises and the signal 209 goes to L level, the timer counter 107 is still
110 does not overflow, the output of the NAND gate 156 becomes L level, and the output Q of FF 116 becomes L level, but before the FG signal 203 rises, the overflow signal 2 of the timer counters 107 to 110 again
When 08 goes to H level, both outputs of NANO gate 154 go to H level, and the Q output of FF 118 is set to H level.

As a result, if the CPU of the calculation unit 2 refers to the contents of the flag buffer 113 corresponding to this signal via the data bus in the process of phase control processing, for example, the timer counter 1
It can be detected that there is no rising edge of the FG flaw signal between 07 and 110 overflow and the next overflow.

At this time, the motor may be stopped as an abnormal state, but it is highly likely that phase control will still be necessary. In this case, first, the input of the gate 139 is set to L level to reset the FF 118, and then, based on the signal state of the flag buffer 113 referred to above, or as an interwoven signal, the mode is shifted to the speed control mode. Once stabilized, the phase control mode is entered again.

In speed control mode, mode select signals 204-20
6 are all set to L level, and the prescaler is set to zero. Then, at the rise of signal 207 that is slightly delayed from the rise of FG signal 203, signal 202 becomes L level, the values of timer counters 107 to 110 are held in timer latches 111 and 112, and signal 2
11 becomes L level, gate 173 becomes L level, counters 107 to 110 are loaded with the prescaler value, that is, reset to zero, and start counting again. Since the values of timer latches 111 and 112 at this time indicate the FG flaw signal period, speed control may be performed based on these values.

Next, consider a case where the FG signal 203 rises twice or more between the timer counters 107 to 110 overflow and the overflow of the composition for which re-counting is started.

First, when the timer counters 107 to 110 overflow, the output of the NANO gate 156 becomes H level. Therefore, the Q output of the FF 116 becomes H level, and the 4 output becomes L level. In this state, when the FG signal 203 rises and the signal 209 goes to L level, the timer counters 107 to 110 have not yet overflowed.
The output of NAND gate 156 becomes L level and FF11
The Q output of No. 6 is at L level, and the ζ output is at H level. If counters 107 to 110 overflow here, NA
The output of NO gate 155 becomes H level, and FF116
Q output becomes H level and Q output becomes L level, but if the FG signal 203 rises again before overflow occurs, the NAND gate 155 output becomes L level,
The Q output of FF 119 becomes H level.

As a result, if the CPU of the calculation unit 2 refers to the contents of the flag buffer 113 corresponding to this signal via the data bus in the process of phase control processing, for example, the timer counter 1
It is possible to detect that the FG signal 203 rises twice or more between the overflow of signals 07 to 110 and the next overflow.

At this time as well, the motor 9 may be stopped as in the case described above, but if phase control is still required, the gate 1
After setting the input of FF 119 to L level and resetting the FF 119, return to the speed control mode based on the signal state of the flag buffer 113 referred to above or using this as an interwoven signal, and wait until the speed becomes stable. All you have to do is switch to phase control mode again.

In this way, even if the FG pulse deviates from the reference signal by 2π or more, that is, in the case shown in Figure 5, the phase difference between the two can be quickly, reliably, and stably adjusted from 0 to 2π without erroneous control. Can be within range.

In addition, in this embodiment, since phase control is performed using FG pulses (for example, 16 pulses per motor rotation), PG pulses (
Highly accurate phase synchronization is possible compared to the method using one pulse per motor rotation. After phase synchronization, step S15
As the READY signal 15 at H level is output, the one-shot circuit 20 generates a pulse longer than the cycle of the reference signal 17 and shorter than two cycles. Then, as the motor rotates, the PGI 1 outputs an H level signal 18 at a specific phase once per revolution, so when the output of the one shot circuit 2o becomes H level, that is, it indicates phase synchronization. When the READY signal 15 is at the H level and the output signal 18 of the PGI 1 is at the H level, the output of the AND gate 21 is at the H level, and the system reference signal generating circuit 5 is set.

Therefore, the system reference signal generating circuit 5 can quickly obtain the timing of the video signal processing system, etc., including the imaging system of the electronic still camera.

Moreover, at this time, the recording medium 25 and the reference signal generating circuit 5 are completely synchronized.

As described above, according to this embodiment, only speed control is performed without performing phase control based on a synchronization signal when the motor is started, so that the motor is not affected by the phase error signal. Therefore, it takes less time for the speed to stabilize. Furthermore, according to this embodiment, the motor control is switched from speed control to phase control after the motor speed becomes stable, and the phase control is switched by first matching the phase of the reference signal for phase control with the phase of the motor. It is possible to reduce the motor phase fluctuation during time and achieve phase synchronization quickly. Moreover, synchronization between the phase-synchronized motor and the video signal can be quickly obtained.

Note that in this embodiment, when controlling using FG pulses,
We have described the case where the FG pulse deviates from the reference signal by 2π or more, that is, the case shown in Figure 5, but it can be easily handled by changing the value of the timer prescaler when controlling using the PG pulse. .

Further, in the above-described embodiment, the present invention was applied to an electronic still camera, but it goes without saying that the present invention can be applied very effectively and easily to various devices having a rotating body drive mechanism.

[Effects of the Invention] As explained above, according to the present invention, there is provided a rotating body drive device that can widen the phase control range and can respond quickly, reliably, and stably even when large load fluctuations occur. can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of an electronic still camera to which a rotating body drive device according to an embodiment of the present invention is applied; FIG. 2 is a flowchart showing an example of the operation of the device shown in FIG. 1; FIG. 4 is a circuit diagram showing a detailed configuration example of the main part of the present embodiment, and FIGS. 4 and 5 are timing charts showing two examples of the timing of the reference signal and the PG pulse signal, respectively. 2... System control calculation section, 3... Timer counter circuit, 4... Latch circuit, 6... Control reference signal generation circuit, 9... Motor, lO... FG. 105.106...Timer prescaler, 107-1
10...Timer counter, 111.112...Timer latch, 114...Mode setting buffer.

Claims (1)

[Scope of Claims] Rotary driving means for driving a rotary body, detection means for detecting the rotational phase of the rotary body, a reference signal source for forming a periodic reference signal, and an output of the reference signal source and the detection means. a phase control means for controlling the rotation drive means so that the phase difference is a constant value by comparing the phase difference with the output with a predetermined value; and an output of the detection means again after the output of the detection means is generated. 1. A rotary body driving device comprising: a control means for varying the number of arithmetic operations of the phase control means in accordance with the time until occurrence of the rotation.