JPS61212180A - Driving device for rotating body - Google Patents

Abstract

PURPOSE:To sustain a great variance of load to control the phase of a rotating body accurately by comparing the variation of the phase difference between the output of a reference signal source and the output of a detecting means with a prescribed value to compensate the phase difference and controlling a rotation control means so that the compensated phase difference is a certain value. CONSTITUTION:A motor 9 is synchronized with a vertical synchronizing signal of a video signal; and at the phase synchronizing time, the period of an FG signal of the motor 9 and that of a reference signal 17 from a control reference signal generating circuit 6 are equalized, and the phase difference between the leading edge of the FG signal pulse and that of the reference signal 17 is set to pi. A switch 11 is switched to the phase control mode (side (b)) by an operating part 2, and a reference signal generation timing signal 16 is inputted to the control reference signal generating circuit 6, and the output of the reference signal 17 from the generating circuit 6 is started when a time corresponding to pi elapses after the rise of the FG pulse in the operating part 2. A mainpulated variable is operated on a basis of the diviation quantity compensated by the operating part 2 and is outputted to a D/A converter 7. Thus, the rotation phase of the motor 9 is controlled on a basis of the mainpulated variable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a rotary body driving device, and more particularly to a rotary body driving device that can extremely effectively control the rotational drive of a recording medium.

[Prior Art] Conventionally, in a rotary body drive device such as a disk drive device in an electronic still camera, drive control has been performed to match the phase of the motor with a reference signal for controlling the operation timing of the entire camera. Therefore, it took a long time to control the phase of the motor, and the camera's start-up characteristics were poor.

In addition, as a method of phase control, for example, the FG (Frequency Generator) is
It is conceivable to control the motor so that the phases of the pulses are synchronized, but in this case, the controllable range of the phase is limited to a range in which the phase delay of the FC pulse with respect to the reference signal is in the range of 0 to 2π.

However, due to sudden changes in the load on the motor, etc., it is possible for the samurai signal to exceed the two controllable limits. For example, as shown in Figure 1, the phase difference between the reference signal and the FC pulse is n.
-(15/8)τ at the time of sampling for the first control
If the phase of the FG pulse is delayed by more than (1/8)π from the reference signal at the time of the next sample, that is, by the nth time, the phase delay of the FC pulse from the reference signal will become more than 2π. However, the above-described phase control method has the drawback that in this case, it is determined that the phase shift has become small, making appropriate control impossible.

[Objective] Therefore, one object of the present invention is to solve the above problems and provide a rotary body drive device that can withstand large load fluctuations and perform accurate phase control of a rotary body.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of an electronic still camera including a rotating body driving device according to the present invention. 2nd rI
! In J, l is a motor start switch, and 2 controls the entire motor control device.

A system control calculation unit that performs calculations, etc., comprising a CPU;
It has a RAM, an RO)I that stores procedures as shown in FIGS. 4 and 5, which will be described later, and a counter. 3 is reset (RESET) at the rising edge of the input signal and becomes 0.
4 is a latch circuit that holds the contents of the timer counter circuit 3 at every rising edge of the input signal, and 2, 3.4 constitute a phase control means. 5 is a system reference signal generation circuit as a synchronization signal source that generates a timing signal (synchronization signal) for the entire device (electronic still camera) in which the wood motor is incorporated; 8 is a system reference signal generation circuit that serves as a reference for phase control of the motor; a motor control reference signal generation circuit as a reference signal source to generate;
7 is a D/A converter, 8 is a motor drive circuit that amplifies the D/A-converted motor control signal, and 9 is a motor as rotation drive means.

Reference numeral 10 denotes an FG (Frequency Frequency) as a detection means for generating FC signal pulses corresponding to the rotational phase of the motor (for example, 18 pulses are generated per one rotation of the motor 3).
cy Generator) circuit, 11 is a mode changeover switch that switches to the a side: speed control mode and the b side: phase synchronization mode according to the mode changeover signal 14; 1B is a mode changeover switch that switches a pulse synchronized with the motor phase to H level once per motor rotation; Phase signal generator (PC) that outputs at 21 is AN
D gate, 12 is the output signal from the FG circuit IO, 13 is the RESE input to the reset input terminal of the counter circuit 3.
T signal 15 is a READY signal 1 which is outputted from the calculation unit 2 and has an H level during phase synchronization and an L level when asynchronous.
B is the reference signal generation timing signal outputted from the calculation unit 2, 17 is the reference signal outputted from the control reference signal generation circuit 6, 1st is the output signal from the PCl3, and 20 is the RE.
This is a one-shot circuit that generates a one-shot pulse of H level having a width approximately equal to the FC cycle of the motor when the ADY signal 15 becomes L-H level. 22 is an imaging device, 23 is a signal processing circuit, 24 is a head, and 25 is a recording medium as a rotating body.

Next, the operation of the above configuration will be explained with reference to FIG. 4. In addition, in this embodiment, when the motor is discharged from the cold hill B,
The cycle of the FC signal of the motor is equal to the cycle of the reference signal 17 from the control reference signal generation circuit, and the phase difference between the rising edge of the FC signal pulse and the rising edge of the reference signal 17 is set to π.

Initially, it is assumed that the motor 9 stops rotating. At this initial time, the switch 11 is in the a-side speed control mode. When the switch 1 is turned on in step Sl, the process proceeds to step S2, where the system control calculation unit 2 outputs a constant value sufficient to start the motor 8 to the D/A converter 7.

Next, the process proceeds to step S3, where the speed of the motor 9 is controlled as described below, and the process proceeds to step S4, in which the calculation section 2 determines whether or not the speed is stable. That is,
First, in step S3, the signal from the D/A converter 7 is input to the drive circuit 8, and the signal from the drive circuit 8 based on this is supplied to the motor 3. Then, the motor 9 starts rotating, and an FC proportional to the rotation period of the motor 3 is transmitted from the FG circuit 10.
The pulse Nobunaga is output f1, and the pulse Nobunaga is output. The pulse Nobunaga is output. The pulse Nobunaga is output. and then starts counting again from 0. Therefore, the latch circuit 4 holds the period of the FC pulse every rising edge of the FC pulse signal. The calculation unit 2 calculates the period of the held FG papal and the control target period (for example, in the case of the NTSC system, the vertical synchronization signal period!/flo
The operation amount is calculated using the difference from the [+/A converter 7] as the deviation amount, and the calculation result is output to the [+/A converter 7]. In this way, the motor 8
The speed of is controlled. Next, the process proceeds to step S4, in which the calculating section 2 determines whether the speed of the motor 8 is sufficiently stable near the target speed based on the deviation amount. If the deviation amount is less than a predetermined value, it is determined that the speed is not stable and the process returns to step S3, and if it is within the predetermined value, the speed is determined to be stable and the process proceeds to step S5.

In step S5, the arithmetic unit 2 determines whether the FG papal is rising, and if it is the rising edge, the process proceeds to step S6, where the arithmetic unit 2 counts the time from the rising edge of the FC pulse using a built-in counter, and then proceeds to step S7. The arithmetic unit 2 determines whether [the period of the FG papal at the time of synchronization - 1/2 of the period of the FC pulse at the time of synchronization] (i.e., τ) has elapsed since the start of counting, and if so, the process proceeds to step S8.

In step S8, in the calculation section 2, the switch 1
1 to the phase control mode (b side) and proceeds to step S9, where the reference signal generation timing signal 1B from the calculation section 2 is inputted to the control reference signal generation circuit B, and π from the rising edge of the FG papal in the calculation section 2 is input. When the time elapses, the generation circuit e starts outputting the reference signal 17. The timing at this time is shown in FIG. 3 for reference.

As a result, the counter circuit 3 is now reset every time the output signal of the generating circuit 6 rises.

Next, the process proceeds to step S10, where the arithmetic unit 2 reads the contents of the latch circuit 4. The contents of the latch circuit 4 are the time count value of the counter circuit 3 from the rise of the reference signal 17 to the rise of the FC pulse, and
This indicates the phase difference between the reference signal and the FC pulse signal.

Next, in step Sll, a phase difference determination routine, which will be described later, is performed. Through this routine, the amount of deviation between the phase difference between the reference signal and the FC pulse and the target phase difference is corrected.

Next, in step S12, the calculation unit 2 calculates the manipulated variable based on the corrected deviation amount, and then proceeds to step S13, where the calculation result (i.e., the manipulated variable) is sent from the calculation unit 2 to the D/A converter. Output to 7. As a result, the rotational phase of the motor 9 is controlled based on the manipulated variable. Next, the process proceeds to step S14, where the calculation unit 2 determines whether the phase difference between the reference signal and the FC pulse is the target phase difference, that is, whether they are phase synchronized, based on the read contents of the latch circuit 4. If the phase is not synchronized, the process returns to step SIO, and if the phase is synchronized, the process proceeds to step S15, where the arithmetic unit 2 outputs the READY signal 15 at H level, and the process proceeds to step S10.

In step Sll, a routine is entered to determine the phase difference between the reference signal and the FG Papal signal.

As shown in FIG. 5, first, in step S21, it is determined whether x (n) -x (n-1) < -x-. x(n) indicates the phase difference between the reference signal and the FG Papal signal at time n, and the rate of change of the phase difference with respect to the time constant of the controlled system and the load fluctuation due to disturbance (reference signal 1
(per cycle), the maximum allowable phase change width per cycle of the reference signal is set as Xdw. In other words, it is assumed that the change in phase difference due to normal disturbance etc. is at most Xtws per period of the reference signal.

For example, let X- be (2/8)π. As shown in Figure 8, the phase difference between the reference signal and the FC pulse signal is (15/8)π at the sample time (n-1), and (1/8)π at the next sample time (n). Suppose it was. Therefore, at this point, the FG papal is delayed by 2π or more with respect to the reference signal. Then, in this step S21.

x (n) −x (n−1) =−π−−π=−π<
-x threshold, proceed to step S22, increment the memo IJ CNT (CENT = 0) by 1 (cNT = 1), and proceed to step S25. In step S25, the calculation unit 2 calculates the deviation x'
(n) to X' (n) = GNT
).

In this case, the correction is made as x' (n) = (17/8)π.

Based on this, step S12. S13. S14 Then, SIO is performed, and the process returns to step Sll again, and the period of the FC pulse gradually becomes shorter. Assuming that, then, the process proceeds from step S21 to step S23, and from there to step S24, where the memory CNT is is decremented by 1 to set CNT = 0. Then, in step S25, x' (n+4) = CNT
X2 tc + x (n+4)-0X 2 π+
x(n+4) = x(n+4), i.e. (4/8)
It becomes π. In this way, the FG papal is 2π from the reference signal.
Reliably and stably maintains the phase difference between the two even if the deviation exceeds O~2π
can be within the range of

In addition, in this embodiment, phase control is performed using FC pulses (for example, 1B pulse per motor rotation), so 0 phase synchronization is possible, which enables more accurate phase synchronization than that using PG Papal (l pulse per motor rotation). After that, step S1
5 outputs the READY signal 15 at H level, the one-shot circuit 20 generates a pulse that is longer than the cycle of the reference signal 17 and shorter than two cycles. Then, as the motor rotates, the PCl3 outputs an H level signal at a specific phase once per rotation, so when the output of the one-shot circuit 20 becomes H, that is, it indicates phase synchronization. READY signal 15 is at H level and P
When the output signal 18 of Cl3 is at H level, AN[l gate 21
The output of the system becomes H level, and the system reference signal generation circuit 5
Set.

Therefore, the system reference signal generating circuit 5 can quickly obtain the timing of the video signal processing system, etc., including the imaging system of the electronic still camera.

Moreover, at this time, the recording medium 25 and the reference signal generating circuit 5 are completely synchronized.

In this way, according to this embodiment, by performing only speed control without performing phase control based on a synchronization signal when starting the motor, it is not affected by the phase error signal, and therefore the speed becomes stable quickly. According to this embodiment, after the motor speed becomes stable, the motor control is switched from speed control to phase control, and by first matching the phase of this reference signal for phase control with the phase of the motor, when switching the phase control, It is possible to reduce motor phase fluctuations and achieve phase synchronization quickly. Moreover, synchronization between the phase-synchronized motor and the video signal can be quickly obtained.

[Effect 1] According to the present invention, it is possible to widen the phase control range in a rotary body drive device, and no synchronization occurs in response to large load fluctuations.

1, 3, and 6 are diagrams each showing an example of the timing of a reference signal and an FC pulse signal, and FIG. 2 is a rotating body drive device according to the present invention. FIGS. 4 and 5 are flowcharts showing an example of the operation of the present invention.

2...System control calculation section.

3... timer counter circuit, 4...Latch circuit, 6... Control reference signal generation circuit, 9...Motor, lO...FC.

Claims (1)

[Scope of Claims] Rotary driving means for driving a rotating body, detection means for detecting the rotational phase of the rotating body, a reference signal source for forming a periodic reference signal, and a position between the output of the reference signal source and the output of the detection means. A rotating body driving device comprising: a phase control means that corrects the phase difference by comparing the amount of change in the phase difference with a predetermined value, and controls a rotation control means so that the corrected phase difference becomes a constant value. .