JPH07212040A - Pattern connecting method of circuit board - Google Patents

Pattern connecting method of circuit board

Info

Publication number
JPH07212040A
JPH07212040A JP421994A JP421994A JPH07212040A JP H07212040 A JPH07212040 A JP H07212040A JP 421994 A JP421994 A JP 421994A JP 421994 A JP421994 A JP 421994A JP H07212040 A JPH07212040 A JP H07212040A
Authority
JP
Japan
Prior art keywords
circuit board
electroless plating
plating
hole
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP421994A
Other languages
Japanese (ja)
Inventor
Yoshisato Tsubaki
宜悟 椿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP421994A priority Critical patent/JPH07212040A/en
Publication of JPH07212040A publication Critical patent/JPH07212040A/en
Pending legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To enable a method of electrically connecting conductive patterns provided to the front and rear of a circuit board together through a plated through-hole to be improved so as to restrain excess plating from attaching to the circuit board. CONSTITUTION:A resist film 7 is previously formed as shown in a Figure (A), a through-hole 4 is bored as shown in a Figure (B), and the through-hole 4 is plated with copper 5' through an electroless plating method as shown in a Figure (C). An excess copper plating 5' is restrained from being formed by the action of the resist film 7, and a product with no useless copper plating can be obtained as shown in a Figure (D).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、絶縁板の表,裏それぞ
れに回路パターンが設けられている回路基板を製造する
際、表側の回路パターンおよび裏側の回路パターンに悪
影響を与える虞れ無く、これらを相互に電気的に接続し
て導通せしめる方法に関するものである。ただし、本発
明において絶縁板ないし回路パターンの表と裏とは厳密
に区別して定義されるものではなく、説明の便宜上の呼
び名であって、何れか片方を表と定めれば他方が裏であ
り、相互に呼称を変換し得るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is capable of producing a circuit board having circuit patterns on the front and back sides of an insulating plate without adversely affecting the circuit pattern on the front side and the circuit pattern on the back side. The present invention relates to a method for electrically connecting these elements to each other so as to make them conductive. However, in the present invention, the front side and the back side of the insulating plate or the circuit pattern are not defined to be strictly distinguished from each other, and the names are for convenience of explanation, and if either one is set as the front side, the other side is the back side. , Can exchange names with each other.

【0002】[0002]

【従来の技術】二つの電気回路を電気的に接続して導通
せしめるための古典的な方法は、電線で繋いで半田付け
を行なうことであるが、回路基板の表,裏に設けられて
いる回路パターン相互を導通させるには、一般にスルー
ホールメッキ法が用いられる。この方法は、絶縁板の
表,裏に対向している導電パターンを貫いて絶縁板に透
孔(スルーホール)を穿ち、これに無電解メッキを施
す。これにより、絶縁板の表,裏の導電パターンによっ
て形成されている回路パターンがメッキ被膜で導通され
る。さらに詳しく述べると、回路基板を作成する場合、
絶縁板の表,裏に金属性の導電被膜を成膜した後、これ
にホトレジストを塗布し、露光,現像,エッチングを施
した後にホトレジスト膜を除去して導電パターンを形成
して回路パターンを構成する。而して前記のスルーホー
ルメッキは、導電被膜をエッチング加工して回路パター
ンを構成する以前に予め行われる。従って、前記のスル
ーホールメッキは回路パターンを導通するものではある
が、正しくは、回路パターン(導電パターン)となるべ
き導電被膜を予め電気的に接続して導通させる操作であ
る。本発明の適用対象は回路基板の完成品ではなく、エ
ッチング処理以前の未完成品であって、これを回路基板
半製品と呼ぶ。図2は前記スルーホールメッキ操作の工
程図であって、(A)は加工前を、(B)は透孔を穿っ
た状態を、(C)は無電解メッキを施した状態を、
(D)は上記無電解メッキ層の上に電解メッキ層を形成
した状態を、それぞれ模式的に描いた断面図である。
(A)図のごとく絶縁板1の両面に表側導電被膜2およ
び裏側導電被膜3が成膜され、(B)図のごとく透孔4
を穿ち、(C)図のごとく無電解メッキ(本例では無電
解銅メッキ)5を施す。この段階で表,裏の導電被膜
2,3が上記無電解銅メッキ5の薄層によって導通され
る。さらに(D)図のごとく電解メッキ(本例では電解
銅メッキ)6を重ねて無電解銅メッキ5を補強するとと
もに電気抵抗を減少せしめて導通を完全にする。
2. Description of the Related Art A classical method for electrically connecting two electric circuits to make them electrically conductive is to connect them with electric wires for soldering, which are provided on the front and back of a circuit board. A through-hole plating method is generally used to bring the circuit patterns into conduction with each other. In this method, through holes are formed in the insulating plate by penetrating through the conductive patterns facing the front and back of the insulating plate, and electroless plating is performed on the through holes. As a result, the circuit patterns formed by the conductive patterns on the front and back of the insulating plate are conducted by the plating film. More specifically, when making a circuit board,
After forming a metallic conductive film on the front and back of the insulating plate, apply a photoresist to this, and after exposing, developing and etching, remove the photoresist film to form a conductive pattern to form a circuit pattern. To do. The through-hole plating is performed before the conductive film is etched to form the circuit pattern. Therefore, although the above-mentioned through-hole plating conducts the circuit pattern, it is an operation to electrically connect the conductive film to be the circuit pattern (conductive pattern) in advance so as to be conductive. The application target of the present invention is not a finished product of a circuit board but an unfinished product before the etching treatment, which is called a circuit board semi-finished product. 2A and 2B are process diagrams of the through-hole plating operation. FIG. 2A is a state before processing, FIG. 2B is a state in which through holes are formed, and FIG. 2C is a state in which electroless plating is performed.
(D) is a cross-sectional view schematically illustrating a state in which an electrolytic plating layer is formed on the electroless plating layer.
The front side conductive coating 2 and the back side conductive coating 3 are formed on both surfaces of the insulating plate 1 as shown in FIG.
And electroless plating (electroless copper plating in this example) 5 is applied as shown in FIG. At this stage, the conductive coatings 2 and 3 on the front and back sides are electrically connected by the thin layer of the electroless copper plating 5. Further, as shown in FIG. 3D, electrolytic plating (electrolytic copper plating in this example) 6 is overlaid to reinforce the electroless copper plating 5, and the electrical resistance is reduced to complete conduction.

【0003】[0003]

【発明が解決しようとする課題】図3に示した従来例の
スルーホールメッキによる導電パターン(詳しくは、導
電パターンとなるべき導電被膜)の接続方法において、
(C)図の段階で必要にして充分な条件は透孔4の内周
面に無電解銅メッキが成膜されて、表,裏の導電被膜が
導通されることである。しかし、この従来技術において
は(C)図に示されているように、必要でない部分、す
なわち、表,裏の導電被膜2が無電解銅メッキ5で覆わ
れる。その結果、(D)図のように表,裏の導電被膜
2,3は無電解銅メッキ5、および電解メッキ6によっ
て覆われる。このように、不必要なメッキが行われるこ
とはメッキ薬品およびメッキ電流の浪費を招く。のみな
らず、これらの無益なメッキは被膜厚さ寸法のコントロ
ールが容易でなく、結果において表,裏の導電被膜2,
3が無制御ないし制御不完全の状態で過度の厚さとな
り、しかも膜厚寸法の均一性が損われる。膜厚寸法が不
均一になると、後工程において高密度,高精度の回路パ
ターンを構成することが困難になるので甚だ好ましくな
い。本発明は上述の事情に鑑みて為されたものであっ
て、前縁板表,裏の回路パターンとなるべき導電被膜
を、必要にして充分なメッキ層によって電気的に接続し
て導通せしめ、該導電被膜に対して無益有害のメッキ層
を付着させない回路パターン接続方法を提供することを
目的とする。これにより、メッキ用の薬液の浪費を節減
し、かつ、最終製品としての回路パターンの高密度・高
精度化が期待され、回路基板の製造技術の向上に貢献す
ることができる。
In the method of connecting a conductive pattern (more specifically, a conductive film to be a conductive pattern) by through-hole plating of the conventional example shown in FIG.
A necessary and sufficient condition in the stage of FIG. 3C is that electroless copper plating is formed on the inner peripheral surface of the through hole 4 so that the front and back conductive films are electrically connected. However, in this conventional technique, as shown in FIG. 7C, unnecessary portions, that is, the front and back conductive films 2 are covered with the electroless copper plating 5. As a result, the front and back conductive coatings 2 and 3 are covered with the electroless copper plating 5 and the electrolytic plating 6 as shown in FIG. Thus, unnecessary plating leads to waste of plating chemicals and plating current. Not only that, but these useless platings are not easy to control the thickness of the coating film.
No. 3 has an excessive thickness in the uncontrolled or incompletely controlled state, and the film thickness uniformity is impaired. If the film thickness dimension is not uniform, it becomes difficult to form a high-density and high-precision circuit pattern in a subsequent process, which is extremely undesirable. The present invention has been made in view of the above circumstances, the front edge plate, the conductive coating to be the circuit pattern on the back, electrically connected by a necessary and sufficient plating layer, to make it conductive. An object of the present invention is to provide a circuit pattern connecting method in which a useless and harmful plating layer is not attached to the conductive film. As a result, it is expected that the waste of the plating chemical liquid will be reduced, and that the circuit pattern as the final product will have a high density and high accuracy, which will contribute to the improvement of the circuit board manufacturing technology.

【0004】[0004]

【課題を解決するための手段】上記の目的(不必要なメ
ッキ防止)を達成するため本発明に係る回路基板のパタ
ーン接続方法は、絶縁板の表,裏それぞれに回路パター
ン構成用の導電被膜が設けられた回路基板半製品に透孔
を穿ち、上記回路基板半製品に無電解メッキを施して前
記透孔の内周面に無電解メッキ層を形成し、該無電解メ
ッキ層を介して絶縁板表,裏の回路パターンを接続,導
通せしめる方法において、回路基板半製品に透孔を穿っ
て無電解メッキを施す前に、表,裏の導電被膜の上に無
電解メッキの付着を妨げるレジストの被膜を形成して、
前記絶縁板の表,裏それぞれに設けられた導電被膜の平
面部に無電解メッキが付着して成層することを防止し、
前記透孔の内周面にのみ無電解メッキ層を形成し、上記
透孔内周面に無電解メッキ層を介して回路基板の表,裏
の導通パターンを接続,導通せしめることを特徴とす
る。
In order to achieve the above-mentioned object (prevention of unnecessary plating), a circuit board pattern connecting method according to the present invention comprises a conductive coating for forming a circuit pattern on each of the front and back of an insulating plate. Is provided with a through hole in the circuit board semi-finished product, electroless plating is applied to the circuit board semi-finished product to form an electroless plating layer on the inner peripheral surface of the through hole, and the electroless plating layer is interposed. In the method of connecting and electrically connecting the circuit patterns on the front and back sides of the insulating plate, prevent the electroless plating from adhering to the conductive coating on the front and back sides before the electroless plating is performed by making holes in the semi-finished circuit board. Form a resist film,
Prevents electroless plating from adhering to the flat surface of the conductive coating provided on each of the front and back of the insulating plate to form a layer,
An electroless plating layer is formed only on the inner peripheral surface of the through hole, and conductive patterns on the front and back of the circuit board are connected to and electrically connected to the inner peripheral surface of the through hole via the electroless plating layer. .

【0005】[0005]

【作用】本発明を適用すると、回路基板半製品の両面に
導電被膜を設けて穿孔し、スルーホールメッキを施すに
先立って、上記導電被膜の上にレジストの薄層が形成さ
れる。このため、上記レジストによって覆われる表,裏
の導電被膜にメッキが付着しない。これによりスルーホ
ールメッキが必要かつ充分な個所にのみ施されてメッキ
薬品やメッキ電力の浪費が防止されるとともに、前記導
電被膜にメッキが付着しないため、該導電被膜のエッチ
ング加工が精密に行なわれ、高密度,高精度の回路パタ
ーンが得られる。
When the present invention is applied, a thin film of resist is formed on the conductive film before the conductive film is provided on both surfaces of the semi-finished circuit board and perforated and prior to through-hole plating. Therefore, the plating does not adhere to the front and back conductive films covered by the resist. As a result, through-hole plating is applied only at necessary and sufficient places to prevent waste of plating chemicals and plating power, and since the plating does not adhere to the conductive coating, the conductive coating is precisely etched. A high-density, high-precision circuit pattern can be obtained.

【0006】[0006]

【実施例】次に図1を参照しつつ本発明方法の実施例に
ついて詳しく説明する。本図1は本発明に係る回路基板
のパターン接続方法の1実施例を示す工程図であって、
(A)は絶縁板の表,裏に導電被膜を成膜した状態を、
(B)は上記絶縁板に透孔を穿った状態を、(C)は無
電解メッキを施した状態を、(D)は電解メッキを施し
終った状態を、それぞれ模式的に描いた断面図である。
上記の図1(A)は前述の従来例を描いた図2(A)に
比して、レジストの薄層7が成膜されている。(B)図
に示したごとく表,裏の導電被膜2,3およびレジスト
の薄層7を貫いて透孔4を穿つ。
EXAMPLE An example of the method of the present invention will be described in detail with reference to FIG. FIG. 1 is a process diagram showing one embodiment of a circuit board pattern connecting method according to the present invention.
(A) shows a state where conductive films are formed on the front and back of the insulating plate,
(B) is a cross-sectional view schematically illustrating a state in which through holes are formed in the insulating plate, (C) is a state in which electroless plating is performed, and (D) is a state in which electrolytic plating is finished. Is.
In FIG. 1A, a thin layer 7 of resist is formed as compared with FIG. (B) As shown in the drawing, the through holes 4 are formed through the front and back conductive films 2 and 3 and the thin layer 7 of resist.

【0007】次いで上記(B)図の回路基板半製品に無
電解銅メッキ5′を施す。このとき、前記レジストの薄
層7に覆われている表,裏の導電被膜2,3には(C)
図に仮想線で示したような無電解銅メッキ5″が付着し
ない。このようにして施した無電解銅メッキ5′の上
に、(D)図の如く電解銅メッキ6′を成膜して、無駄
の無い製品が得られる。
Next, electroless copper plating 5'is applied to the circuit board semi-finished product shown in FIG. At this time, (C) is applied to the front and back conductive films 2 and 3 covered with the thin layer 7 of the resist.
The electroless copper plating 5 "as shown by the phantom line in the figure does not adhere. The electrolytic copper plating 6'is formed as shown in FIG. As a result, a lean product can be obtained.

【0008】ここで、表,裏の導電被膜2,3に無電解
メッキが付着しないということは、必ずしもレジストの
薄層7に無電解メッキが付着しないことを保証しない。
そこで、無電解メッキの薬剤とレジストの種類とを選択
して、無電解メッキの付着しないレジストを用いること
が望ましい。
Here, the fact that the electroless plating does not adhere to the front and back conductive coatings 2 and 3 does not necessarily guarantee that the electroless plating does not adhere to the thin layer 7 of the resist.
Therefore, it is desirable to select the electroless plating agent and the type of resist and use a resist that does not adhere to electroless plating.

【0009】[0009]

【発明の効果】本発明を適用すると、回路基板半製品の
両面に導電被膜を設けて穿孔し、スルーホールメッキを
施すに先立って、上記導電被膜の上にレジストの薄層が
形成される。このため、上記レジストによって覆われる
表,裏の導電被膜にメッキが付着しない。これにより、
スルーホールメッキが必要かつ充分な個所にのみ施され
てメッキ薬品やメッキ電力の浪費が防止されるととも
に、前記導電被膜にメッキが付着しないため、該導電被
膜のエッチング加工が精密に行なわれ、高密度,高精度
の回路パターンが得られるという優れた実用的効果を奏
する。
When the present invention is applied, a thin layer of resist is formed on the conductive film before the conductive film is provided on both surfaces of the semi-finished circuit board and perforated, and prior to through-hole plating. Therefore, the plating does not adhere to the front and back conductive films covered by the resist. This allows
Through-hole plating is applied only at necessary and sufficient places to prevent waste of plating chemicals and plating power, and since plating does not adhere to the conductive coating, the conductive coating can be precisely etched, It has an excellent practical effect of obtaining a circuit pattern with high density and high accuracy.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る回路基板のパターン接続方法の1
実施例を示す工程図である。
FIG. 1 is a method 1 of a pattern connection method for a circuit board according to the present invention.
It is process drawing which shows an Example.

【図2】前記スルーホールメッキ操作の工程図であっ
て、(A)は加工前を、(B)は透孔を穿った状態を、
(C)は無電解メッキを施した状態を、(D)は上記無
電解メッキ層の上に電解メッキ層を形成した状態を、そ
れぞれ模式的に描いた断面図である。
2A and 2B are process diagrams of the through-hole plating operation, in which FIG. 2A is before processing, and FIG.
(C) is a cross-sectional view schematically showing a state where electroless plating is applied, and (D) a state where an electroplating layer is formed on the electroless plating layer.

【符号の説明】[Explanation of symbols]

1…絶縁板、2…表側導電被膜、3…裏側導電被膜、4
…透孔、5,5′無電解銅メッキ、5″…余分に付着し
た無電解銅メッキ、6,6′…電解銅メッキ、7…レジ
スト。
1 ... Insulating plate, 2 ... Front side conductive coating, 3 ... Back side conductive coating, 4
... through holes, 5,5 'electroless copper plating, 5 "... extra electroless copper plating, 6,6' ... electrolytic copper plating, 7 ... resist.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁板の表,裏それぞれに回路パターン
構成用の導電被膜が設けられた回路基板半製品に透孔を
穿ち、上記回路基板半製品に無電解メッキを施して前記
透孔の内周面に無電解メッキ層を形成し、該無電解メッ
キ層を介して絶縁板表,裏の回路パターンを接続,導通
せしめる方法において、 回路基板半製品に透孔を穿って無電解メッキを施す前
に、表,裏の導電被膜の上に無電解メッキの付着を妨げ
るレジストの被膜を形成して、前記絶縁板の表,裏それ
ぞれに設けられた導電被膜の平面部に無電解メッキが付
着して成層することを防止し、前記透孔の内周面にのみ
無電解メッキ層を形成し、 上記透孔内周面に無電解メッキ層を介して回路基板の
表,裏の導通パターンを接続,導通せしめることを特徴
とする、回路基板のパターン接続方法。
1. A circuit board semi-finished product having a conductive coating for forming a circuit pattern on each of the front and back sides of an insulating plate is provided with a through hole, and the circuit board semi-finished product is electroless plated to form a through hole. In the method of forming an electroless plating layer on the inner peripheral surface and connecting and electrically connecting the circuit patterns on the front and back of the insulating plate through the electroless plating layer, the electroless plating is performed by forming a through hole in the semi-finished circuit board product. Before applying, a resist film that prevents the adhesion of electroless plating is formed on the front and back conductive films, and electroless plating is applied to the flat surface portions of the conductive films provided on the front and back of the insulating plate, respectively. A conductive pattern on the front and back of the circuit board is formed by forming an electroless plating layer only on the inner peripheral surface of the through hole to prevent adhesion and layering, and through the electroless plating layer on the inner peripheral surface of the through hole. A circuit board pattern that connects and conducts Connection method.
【請求項2】 前記無電解メッキを施した後、その上に
電解メッキを施し、無電解メッキ層を補強して導通を確
実ならしめることを特徴とする、請求項1に記載した回
路基板のパターン接続方法。
2. The circuit board according to claim 1, wherein, after the electroless plating is applied, electrolytic plating is applied on the electroless plating to reinforce the electroless plating layer to ensure conduction. Pattern connection method.
【請求項3】 前記絶縁板の表,裏それぞれに設ける導
電被膜を銅によって構成することを特徴とする、請求項
1若しくは請求項2に記載した回路基板のパターン接続
方法。
3. The circuit board pattern connection method according to claim 1, wherein the conductive films provided on the front and back of the insulating plate are made of copper.
【請求項4】 前記のレジストは、回路基板半製品の導
電被膜を覆って該導電被膜に対する無電解メッキの付着
を防止する機能を有するとともに、電解メッキの付着を
防止する機能を有し、かつ、該レジストの被膜それ自体
も無電解メッキが付着しない性質のものを用いることを
特徴とする、請求項2に記載した回路基板のパターン接
続方法。
4. The resist has a function of covering a conductive coating of a circuit board semi-finished product to prevent adhesion of electroless plating to the conductive coating, and a function of preventing adhesion of electrolytic plating. The pattern connection method for a circuit board according to claim 2, wherein the resist film itself has a property such that electroless plating does not adhere thereto.
JP421994A 1994-01-19 1994-01-19 Pattern connecting method of circuit board Pending JPH07212040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP421994A JPH07212040A (en) 1994-01-19 1994-01-19 Pattern connecting method of circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP421994A JPH07212040A (en) 1994-01-19 1994-01-19 Pattern connecting method of circuit board

Publications (1)

Publication Number Publication Date
JPH07212040A true JPH07212040A (en) 1995-08-11

Family

ID=11578504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP421994A Pending JPH07212040A (en) 1994-01-19 1994-01-19 Pattern connecting method of circuit board

Country Status (1)

Country Link
JP (1) JPH07212040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011168808A (en) * 2010-02-16 2011-09-01 Meiko:Kk Through-hole plating method and substrate produced by using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011168808A (en) * 2010-02-16 2011-09-01 Meiko:Kk Through-hole plating method and substrate produced by using the same

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